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TL500!, TLS00C, TL501!, TL501C, TL502C, TL503C ANALOG-TO-DIGITAL-CONVERTER BUILDING BLOCKS

02477 DECEMBER 1979 REVISED JANUARY 1989

TLSOOI, TLS00C, TL5O1I, TL501C ANALOG PROCESSORS © True Differential inputs © Automatic Zero @ Automatic Polarity © High Input Impedance . . . 109 Ohms. Typically TLS5001I, TL500C CAPABILITIES TLS5011, TL501C CAPABILITIES @ 4 1/2-Digit Readout Accuracy with External @ 3 1/2-Digit Readout Accuracy Precision Reference TL502C CAPABILITIES TL502C/TL503C DIGITAL PROCESSORS © Compatible with Popular Seven-Segment Common-Anode Displays e . Fast Display Soan Rates © High-Sink-Current Segment Driver for Large © Internal Oscillator May Be Driven or Displays Free-Running © Interdigit Blanking TL503C CAPABILITIES © Over-Range Blanking © Multiplexed BCD Outputs © 4 1/2-Digit Display Circuitry © High-Sink-Current BCD Outputs @ = High-Sink-Current Digit Driver for Large Displays y Caution. These devices have limited built-in gate protection. The leads should be shorted together or the wy device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS Mtad Gates.

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The TLSOO!, TLS500C, TL5011, and TL501C analog processors and TL502C and TL503C digital processors provide the basic functions for a dual-slope-integrating analog-to-digital converter The TL500 and TL501 contain the necessary analog switches and decoding circuits, reference voltage | generator, buffer, integrator, and comparator. These devices may be controlled by the TL502C, TL503C, by discrete logic, or by a software routine in a microprocessor. The TL502C and TL5O3C each includes oscillator, counter, control logic, and digit enable circuits. The TL502C provides multiplexed outputs for seven-segment displays, while the TL503C has multiplexed BCD outputs. When used in complementary fashion, these devices form a system that features automatic zero-offset compensation, true differential inputs, high input impedance, and capability for 4 1/2-digit accuracy. Applications include the conversion of analog data from high-impedance sensors of pressure, temperature, light, moisture, and position. Analog-to-digital-logic conversion provides display and control signals for weight scales, industrial controllers, thermometers, light-level indicators, and many other applications. PRODUCTION OATA document contain information ; Copyigh © 1978, Texas inawuments Incorporated Cent as ot pubicton date: Products conform fecessriy include tasting of al parameters INSTRUMENTS 20ST OFFICE 80x 655303 - DALLAS, TEXAS 75265, 297

TL500I, TL500C, TL5011, TL501C, TL502C, TL503C ANALOG-TO-DIGITAL-CONVERTER BUILDING BLOCKS ee principles of operation The basic principle of dual-slope-integrating converters is relatively simple. A capacitor, Cx, is charged through the integrator from VCT for a fixed period of time at a rate determined by the value of the unknown voltage input. Then the capacitor is discharged at a fixed rate (determined by the reference voltage) back to VCT where the discharge time is measured precisely. The relationship of the charge and discharge values are shown below (see Figure 1). Vitd Vi = Vet - > Charge (1) cx = Vet ~ ey 9 Vref 2 Vet = Vex- =— Discharge (2) ct = Vox- Fy 9 Combining equations 1 and 2 results in vi t2 Viet tt (3) where: VcT = Comparator (offset) threshold voltage Vex = Voltage change across Cx during ty and during t2 (equal in magnitude) V| = Average value of input voltage during ty ty = Time period over which unknown voltage is integrated t2 = Unknown time period over which a known reference voltage is integrated. Equation (3) illustrates the major advantages of a dual-slope converter: a. Accuracy is not dependent on absolute values of ty and tz, but is dependent on their ratios. Long- term clock frequency variations will not affect the accuracy. b. Offset values, VcT. are not important. The BCD counter in the digital processor (see Figure 2) and the control logic divide each measurement cycle into three phases. The BCD counter changes at a rate equal to one-half the oscillator frequency. auto-zero phase The cycle begins at the end of the integrate-reference phase when the digital processor applies low levels to inputs A and 8 of the analog processor. If the trigger input is at a high level, 2 free-running condition exists and continuous conversions are made. However, if the trigger input is low, the digital processor stops the counter at 20,000, entering a hold mode. In this mode, the processor samples the trigger input every 4000 oscillator pulses until a high level is detected. When this occurs, the counter is started again and is carried to completion at 30,000. The reference voltage is stored on reference capacitor Cref, comparator offset voltage is stored on integration capacitor Cx, and the sum of the buffer and integrator offset voltages is stored on zero capacitor Cz. During the auto-zero phase, the comparator output is characterized by an oscillation (limit cycle) of indeterminate waveform and frequency that is filtered and d-c shifted by the level shifter. integrate-input phase The auto-zero phase is completed at a BCD count of 30,000, and high levels are applied to both control inputs to initiate the integrate-input phase. The integrator charges Cx for a fixed time of 10,000 BCD counts at a rate determined by the input voltage. Note that during this phase, the analog inputs see only the high impedance of the noninverting operational amplifier input. Therefore, the integrator responds only to the difference between the analog input terminals, thus providing true differential inputs. tS TEXAS % INSTRUMENTS 2-78 POST OFFICE OX 655309 - DALLAS, TEXAS 75265

activated, the over-range indication blanks all but the most significant digit and sign. segment drivers (TL502C) at a rate equal to the oscillator frequency divided by 200. FIGURE 1. VOLTAGE WAVEFORMS AND TIMING DIAGRAM

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TL5001, TL500C, TL5011, TL501C ANALOG PROCESSORS description of analog processors J PACKAGE (ToP view The TL500 and TL5O1 analog processors are designed to automatically compensate for anacoc input 1 (1 Ore) de internal zero offsets, integrate a differential ANALOG INPUT 22171) z voltage at the analog inputs, integrate a voltage ReF ourpuTG3—s6[ Vcc + at the reference input in the opposite direction, ReF INPUT(J¢ —15[) BUFFER OUTPUT and provide an indication of zero-voltage ANALOG GND [Js 14P INTEGRATOR INPUT crossing. The external control mechanism may Cret« Ge 13 INTEGRATOR OUTPUT be a microcomputer and software routing, Cet-Q? 120) Vcc - discrete logic, or a TL502C or TL503C controller. CONTROL B INPUT (Je —_11[] DIGITAL COMMON The TL500 and TL5O1 are designed primarily for © CONTROL A INPUT []9__10f] COMPARATOR OUTPUT simple, cost-effective, dual-slope analog-to- digital converters. Both devices feature true OW PACKAGE differential analog inputs, high input impedance, (TOP VIEW) and an internal reference-voltage source. The ANALOG INPUT +f) Cao cz TL5OO provides 4-1/2-digit readout accuracy ANALOG INPUT 2(]2 19] Cz when used with a precision external reference rer outPuT(2 ssf] vec. voltage. The TL501 provides 100-ppm linearity er inpuTCla —17f] BUFFER OUTPUT error and 3-1/2-digit accuracy capability. These ANALOG GND(|s 16 ] INTEGRATOR INPUT devices are manufactured using TI's advanced Cret» Cs 15{) INTEGRATOR OUTPUT technology to produce JFET, MOSFET, and Cet C? El vec - bipolar devices on the same chip. The TL500C neGle hue and TL501C are characterized for operation over conTRoL BiNPUTE|2 126] DIGITAL COMMON the temperature range of O°C to 70°C. The — conTROL A INPUTL}10 11] COMPARATOR OUTPUT TL5001 and TL501I are characterized for operation from — 40°C to 85°C. NC. No internal connection AVAILABLE OPTIONS [__packace 4) (ow) | o.os% rs [ Tisoicy |" TLsoicow _ | | sore wasee fACme ES | Tisead fo | [ oos% rs | Tisons | Tusowow | TEXAS Kd INSTRUMENTS POST OFFICE BOX 655303 » DALLAS. TEXAS 75265 2-81

TL5001, TL500C, TL5011, TL501C ANALOG PROCESSORS ee schematics of inputs and outputs CONTROL A AND CONTROL B INPUTS. COMPARATOR OUTPUT Ey oureur INPUT —— DIGITAL ° COMMON Vo absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Negative supply voltage, VCC — - 6 eee cee eee -18V Input voltage, Vj : . . +Vcc Comparator output voltage range (see Note 2) . OV to Vec4 Comparator output sink current (see Note 2) . . reas . wee - 20 mA Operating free-air temperature range: TL500I, TL5011 . . 40 to 85°C TL500C, TL501C . O°C to 70°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW package . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . 300°C NOTES: 1. Voltage values. except differential voltages. are with respect to the analog ground common pin tied together DISSIPATION RATING TABLE PACKAGE Ta = 25°C DERATING FACTOR Ta = 70°C Ta = 85°C POWER RATING ABOVE Ta = 25°C POWER RATING POWER RATING ow 1125 mw 9 mw/°C 720 mw 585 mW J 1025 mw 8.2 mwiec 656 mw 533 mw TEXAS 4% INSTRUMENTS 2-82 POST OFFICE BOX 688303 - OALLAS, TEXAS 75265

TL5001, TL500C, TL5011, TL501C ANALOG PROCESSORS recommended operating conditions | mun _wom Max UNIT Positive supply voltage, VCs Negative supply voltage. Voc ~ Tes Reference input voltage, Vrefil a Analog input voltage. Vi ss Differential analog input voltege, Vip [to | High-level input voltage, Vin [Gontrotinputs Low-level input voltage, Vj [controtinputs TV | Peak positive integrator output voltage, VOM + Peak negative integrator output voltage, Vom ~ a Full scale input voltage 7 | ‘Autozero and reference capacitors, Cz and Grey Lo. +i i Integrator capacitor, Cx po2 TF Integrator resistor, Rx [is soo ka | Free-air operating temperature, T, TL8001, FLEON =*0 S85) ec speraung remporane TA TLS0OC, TLEOIC Maximum conversion rate with TLS02C or TLS03C 312s ‘system electrical characteristics at VcC+ = +12 V. Vref = 1,000 + 0.03 mV, Ta = 25°C (unless otherwise noted) (see Figure 3) PARAMETER TEST CONDTTIONS tuson {| __ 14800 Tr MIN_TYP_MAX | MIN TYP MAX | Zero error 80300 [00 Linearity error relative to full scale Vi=2Vw2V 0.005 0.05 0.001 0.005 Full scale temperature coefficient a ee Cd Ta = tall a ‘nee a [ Rotiover error 200 soo 30 too |v | Equivalent peak-to-peak input noise voltage] 2020 | Analog inputresistance TT Pindor2 P08 to | Commonmode rejection ratio [igs ~tvto+tv [ee] Cd M= #5V a Supply voltage rejection ratio a | "Rollover error is the voltage difference between the conversion results of the full-scale positive 2 V and the full-scale negative 2 V NOTE 3. The minimum integrator time constant may be found by use of the following formula: Vip full scale) Minimum RxCx = Vid Mul scale) t1_ |VYom =| =Vilpin 2) where Vip = voltage at pin with respect to pin 2 Vitpin 2) = voltage at pin 2 with respect to analog ground 11 = input integration time seconds TEXAS 2 INSTRUMENTS POST OFFICE 6OX 655309 - OALLAS, TEXAS 76265 2-83

TL500I, TL500C, TL5011, TLS01C ANALOG PROCESSORS pr electrical characteristics at VCC + = +12 V, Vref = 1V, TA = 25°C (see Figure 3) integrator and buffer operational amplifiers PARAMETER TEST CONDITIONS [ww typ max | unit | [Vig trput offset votage | CCST” CTC [ig Input Bias cuvent SS SC*d Sid [Vows Positive output voltage swing | SSCS | id Cd | Vom Negative output vottage swing [8 [Avp Voltage amplification [tg a [81 Unity-gain bandwigth Pe [EMA Common mode rejection __—+4| Sie > Vie viv S«dYSSCOOSC*dSC [Sk Oupursiowrato SSS SSS iY Vin] comparator PARAMETER [| __ test conpirions | Min typ MAX | Unit [Vio Input offset votage Pg [ig Input bias current 0 a [Avp Voltage emplifcation | Cid OO —C*dYC | Lio High-level output current Ton = SV 20 Tn voltage reference output [ PaRaMereR TEST CONDITIONS MIN” TYP_MAX [ Wretioy Reference voltage J 218 Reterence-voltage are mi [ov fongenursemncans | TAM | 80 oie [ig Reference output resistance [a logic control section PARAMETER ‘TEST CONDITIONS MIN TYP MAX | UNIT | [ig Wighevel input curent P21 | total device [ panamerer —[testconpirions | MIN tvP_ max | unit | [icc Positive supply current Pt 20 Tm [icc Negative supply cunen’ | 2 18 | ma | SS TEXAS 4 INSTRUMENTS 2-84 POST OFFICE BOX 655303 - DALLAS. TEXAS 75265

FIGURE 3. TEST CIRCUIT CONFIGURATION because of their relatively high-leakage characteristics. film dielectrics are usually suitable. Ceramic and electrolytic capacitors are not recommended. at the package, for example, by a 0.01-uF ceramic capacitor. be within 4 V of positive or negative supply with the logic decode still functioning properly. Vi(pin2) = Voltage on pin 2 with respect to analog ground.

TL502C, TL503C DIGITAL PROCESSORS description of digital processors TESO2C . . - N PACKAGE (TOP view) The TL502C and TL503C are control logic conrrot 8 oureut fr 201 vec jevices designed to complement the TL500 and D1 (Ls) G2 19[.] CONTROL A OUTPUT TL501 analog processors. They feature interdigit picit o2 Fla taf) 20,0007 blanking, over-range blanking, an internal ENABLE p3C}s7Floscitator inpur oscillator, and a fast display scan rate. The ouTPUTS oa Cs re] TRIGGER interal-oscillator input is a Schmitt trigger circuit bs mss)? (le 1s] COMPARATOR INeuT that can be driven by an external clock pulse or 7.SEGMENT (aC? ak] provide its own time base with the addition of DRIVER Bfle 3t}r USEGMENT ‘@ capacitor. The typical oscillator frequency is outputs Les he ¢_DRIVER 120 kHz with a 470-pF capacitor connected DIGITAL COMMON fio nfo J OUTPUTS between the oscillator input and ground. The TL502C provides seven-segment-display TLS03C 'N PACKAGE output drivers capable of sinking 100 mA and (TOP VIEW) compatible with popular common-anode controt @ oureur fT Ore vec displays. The TL503C has four BCD output 01 LSB) Fz 1s] CONTROL A OUTPUT drivers capable of 100-mA sink currents. The biGiT 023 aE Joscittator INPUT code (see next page and Figure 4) for each digit ENABLE 03H spl triccer is multiplexed to the output drivers in phase with | OUTPUTS 04Es — 12L]} comparator INPUT a pulse on the appropriate digit-enable line at a osimseite fag digit rate equal to fosc. divided by 200. Each QQ r0PJa> digit-enable output is capable of sinking 20-mA oiciTaL common EJs ofa; The comparator input of each device, in addition ‘Pin 18 of TL502C provides an output of tose (oscillator to monitoring the output of the zero-crossing frequency) ~ 20,000 detector in the analog processor, may be used DS, the most significant bit, is also the sign bit. in the display test mode to check for wiring and display faults. A high logic level (2 to 6.5 V) at the trigger input with the comparator input at or below 6.5 V starts the integrate-input phase. Voltage levels equal to or greater than 7.9 V on both the trigger and comparator inputs clear the system and set the BCD counter to 20,000. When normal operation resumes, the conversion cycle is restarted at the auto zero phase. These devices are manufactured using |2L and bipolar techniques. The TL502C and TL503C are characterized for operation from 0°C to 70°C. TABLE OF SPECIAL FUNCTIONS Voc = 5 V £10% INPUT INPUT Both inputs to go Vj>7.9V System clear: Sets BCD counter to 20,000 CE TEXAS % INSTRUMENTS 2-86 POST OFFICE BOX 655209 « DALLAS. TEXAS 75266

TL502C, TL503C DIGITAL PROCESSORS a DIGIT § (MOST SIGNIFICANT DIGIT) CHARACTER CODES ‘TL502C SEVEN-SEGMENT LINES TL503C BCD OUTPUT LINES cHaRacTER 7 \\C" A B c D E F A a3 a2 Q a0 8 4 2 1 a Y

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a Pe ee eG DIGITS 1 THRU 4 NUMERIC CODE (See Figure 4) TUS020 SEVEN SEGMENT LINES T15036 BOD OUTPUT LINES a3 a2 Qi a0 8 4 2 1 a a Hot tb Ww w# Hw w]e ie ein 2 a a 3 u L t L H H L t L H H rr a Fn a 6 a 7 fe a A H = high level, L = tow level schematics of inputs and outputs COMPARATOR AND TRIGGER INPUT SEGMENT DRIVERS-TL5026 BCD DRIVERS—TLS03C 25kaQ ] DISPLAY 7500 ne TESTOR - System . 2ske {eke CLEAR a _oureur 4 seat ike iweui [fe 4 + COMMON | conanon~ ~~ CONTROL A AND 8 OUTPUTS DIGIT- ENABLE OUTPUTS rks 1WBkKLQ WOkD OUTPUT OUTPUT Thay 110 273 tke common: common-—— *Shorted on TL503C TO TEXAS. % INSTRUMENTS

TL502C, TL503C DIGITAL PROCESSORS ———— absolute maximum ratings [ Supply votage. Voc weeNowe 4) Input voltage, V; [_Oscitator ee BCD or Segment drivers Output current | Digit-enable outputs [40 Pin 18 (TL502C only) [20 Total power dissipation at (or below) 30°C free oir temparature (see Note 6) [1100 | mw] Storage temperature range J =65t0 150 ec Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds [260 ~~—SC«&YsC=é‘(d NOTES: 4, Voltage values are with respect to the network ground termina 5. For operation above 30°C free-air temperature, derate linearly to 736 mW at 70°C at the rate of 9.2 mW/°C. recommended operating conditions | Supply voltage. Vcc a P| | High-level input voltage. Vin | Comparator and trigger inputs | [Low-level input voltage, Vi | Comparator and wiggerinputs_————~+| ost _v_| TEXAS % INSTRUMENTS

288 POST OFFICE BOX 655303 - DALLAS, TEXAS 75265

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The comparator and trigger inputs may be used in the normal mode or to perform special functions. See the Table of Special Functions. NOTE E: The BCD or seven-segment driver outputs are present for a particular digit slightly before the falling edge of thet digit enable. FIGURE 4. TL502C, TL503C DIGIT TIMING WITH 120-kHz CLOCK SIGNAL AT OSCILLATOR INPUT

Product Information

TL503C specifications and overview.

Summary

ANALOG TO DIGITAL CONVERTER BUILDING BLOCKS

Description

ANALOG TO DIGITAL CONVERTER BUILDING BLOCKS

Source title TL503C Datasheet(PDF) - Texas Instruments

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