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Technical content
/C0084/C0076/C0053/C0048/C0048/C0050 /C0080/C0085/C0076/C0083/C0069/C0262/C0087/C0073/C0068/C0084/C0072/C0262/C0077/C0079/C0068/C0085/C0076/C0065/C0084/C0073/C0079/C0078 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0067/C0073/C0082/C0067/C0085/C0073/C0084 /C0261 /C0261 SLVS304A − SEPTEMBER 2000 − REVISED AUGUST 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Complete PWM Power Control /C00683.6-V to 40-V Operation /C0068Internal Undervoltage-Lockout Circuit /C0068Oscillator Frequency...2 0 kHz to 500 kHz /C0068Variable Dead Time Provides Control Over Total Range /C0068Ideal Controller for DDR Memory Application /C0068Uncommitted Error Amplifier Inputs
description
The TL5002 incorporates on a single monolithic chip all the functions required for a pulse-width-modulation (PWM) control circuit. Designed primarily for power-supply control, the TL5002 contains an error amplifier, a regulator, an oscillator, a PWM comparator with a dead-time-control input, undervoltage lockout (UVLO), and an open-collector output transistor. The error-amplifier input common-mode voltage ranges from 0.9 V to 1.5 V. Dead-time control (DTC) can be set to provide 0% to 100% dead time by connecting an external resistor between DTC and GND. The oscillator frequency is set by terminating RT with an external resistor to GND. During low V CC conditions, the UVLO circuit turns the output off until VCC recovers to its normal operating range. The TL5002 is characterized for operation from −40°C to 85°C. AVAILABLE OPTIONS TA SMALL OUTLINE (D) −20°C to 85°C TL5002CD −40°C to 85°C TL5002ID The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL5002CDR). functional block diagram GND OUT COMP INV 4 − DTCRT PWM/DTC ComparatorOSC Amplifier Error UVLO VCC 2 1 Reference Voltage IDT 2.5 V NI Copyright 2002, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0261 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OUT VCC COMP INV GND RT DTC NI D PACKAGE (TOP VIEW)
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A 2.5-V regulator operating from VCC is used to power the internal circuitry of the TL5002.
5 NIVref
Figure 1. Error-Amplifier Gain Setting for stability. Because the amplifier can only source 45 µA, the total dc load resistance should be 100 kΩ or more. by using the graph shown in Figure 5. the lesser of the two inputs.
Figure 2. Soft-Start Circuit every time UVLO becomes active. lower than both the DTC voltage and the error-amplifier output voltage, and the UVLO circuit is inactive.
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW recommended operating conditions MIN MAX UNIT Supply voltage, VCC 3.6 40 V Amplifier input voltage, VI(INV), VI(NI) 0.9 1.5 V Output voltage, VO , OUT 50 V Output current, IO , OUT 20 mA COMP source current 45 µA COMP dc load resistance 100 kΩ Oscillator timing resistor, Rt 15 250 kΩ Oscillator frequency, fosc 20 500 kHz Operating ambient temperature, TA −40 85 °C
/C0084/C0076/C0053/C0048/C0048/C0050 /C0080/C0085/C0076/C0083/C0069/C0262/C0087/C0073/C0068/C0084/C0072/C0262/C0077/C0079/C0068/C0085/C0076/C0065/C0084/C0073/C0079/C0078 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 /C0067/C0073/C0082/C0067/C0085/C0073/C0084 /C0261 /C0261 SLVS304A − SEPTEMBER 2000 − REVISED AUGUST 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, fosc = 100 kHz (unless otherwise noted) undervoltage lockout PARAMETER TEST CONDITIONS TL5002C UNITPARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Upper threshold voltage TA = 25°C 3 V Lower threshold voltage TA = 25°C 2.8 V Hysteresis TA = 25°C 100 200 mV † All typical values are at TA = 25°C. oscillator PARAMETER TEST CONDITIONS TL5002C UNITPARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Frequency R t = 100 kΩ 100 kHz Standard deviation of frequency 15 kHz Frequency change with voltage VCC = 3.6 V to 40 V 1 kHz TA = −40°C to 25°C −4 −0.4 4 kHz Frequency change with temperature TA = −20°C to 25°C −4 −0.4 4 kHzFrequency change with temperature TA = 25°C to 85°C −4 −0.2 4 kHz Voltage at RT 1 V † All typical values are at TA = 25°C. dead-time control PARAMETER TEST CONDITIONS TL5002C UNITPARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Output (source) current TL5002 V(DT) = 1.5 V 0.9 × IRT ‡ 1.2 × IRT µA Input threshold voltage Duty cycle = 0% 0.5 0.7 VInput threshold voltage Duty cycle = 100% 1.3 1.5 V † All typical values are at TA = 25°C. ‡ Output source current at RT error amplifier PARAMETER TEST CONDITIONS TL5002C UNITPARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Input voltage VCC = 3.6 V to 40 V 0.3 1.5 V Input bias current −160 −500 nA Output voltage swing Positive 1.5 2.3 V Output voltage swing Negative 0.3 0.4 V Open-loop voltage amplification 80 dB Unity-gain bandwidth 1.5 MHz Output (sink) current VI(INV) = 1.2 V,COMP = 1 V 100 600 µA Output (source) current VI(INV) = 0.8 V,COMP = 1 V −45 −70 µA † All typical values are at TA = 25°C.
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† All typical values are at TA = 25°C. † All typical values are at TA = 25°C. Figure 3. PWM Timing Diagram
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1.5 1.2 0.6 0.3 1.8 0.9 10 k 100 k 1 M 10 M PWM Triangle Wave Amplitude Voltage − V fosc − Oscillator Frequency − Hz Voscmin (zero duty cycle) VCC = 6 V TA = 25 °C PWM TRIANGLE WAVE AMPLITUDE VOLTAGE vs OSCILLATOR FREQUENCY Voscmax (100% duty cycle) Figure 9 ERROR AMPLIFIER OUTPUT VOLTAGE vs OUTPUT (SINK) CURRENT − Error Amplifier Output Voltage − VVO IO − Output (Sink) Current − mA 1.5 0.5 0 0.2 0.4 2.5 0.6 VCC = 6 V VI(INV) = 1.2 V VI(NI) = 1 V TA = 25 °C Figure 10 1.5 0.5 02 04 0 − Error Amplifier Output Voltage − V 2.5 60 80 100 120 VO IO − Output (Source) Current − µA VCC = 6 V VI(INV) = 0.8 V VI(NI) = 1 V TA = 25 °C ERROR AMPLIFIER OUTPUT VOLTAGE vs OUTPUT (SOURCE) CURRENT Figure 11 2.43 2.42 2.41 2.40 − 50 − 25 0 − Error Amplifier Output Voltage − V 2.44 2.45 2.46 25 50 75 100 VO TA − Ambient Temperature − °C VCC = 6 V VI(INV) = 0.8 V VI(NI) = 1 V No Load ERROR AMPLIFIER OUTPUT VOLTAGE vs AMBIENT TEMPERATURE
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− 30 − 20 − 10 0 − 10 − 20 − DTC Output Current − − 40 − 50 − 60 − 30 − 40 − 50 − 60 DT Voltage = 1.3 V TA = 25 °C IO − RT Output Current − µA AµIO(DT) DTC OUTPUT CURRENT vs RT OUTPUT CURRENT Figure 16 0.5 1.5 0 5 10 15 20 − Output Saturation Voltage − V IO − Output (Sink) Current − mA VCE VCC = 6 V TA = 25 °C OUTPUT SATURATION VOLTAGE vs OUTPUT (SINK) CURRENT
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APPLICATION INFORMATION
2 PGND
1 OUT
+ + VTT GN D Figure 17. DDRI Application
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QUANTITY REF DES PART NUMBER DESCRIPTION MANUFACTURER SIZE 1 C1 UUD1C471MNR1GS Capacitor, aluminum Nichicon 0.327 x 0.327
6 C2 − C6, C13 EMK325BJ106MN−B Capacitor, ceramic Taiyo Yuden 1210
3 C7, C8, C20 GRM40X7R105K16PT Capacitor, ceramic, jumper Murata 805
2 C9, C10 EEF−CD0D101R Capacitor, aluminum Panasonic 7343
1 C14 08055A102JAT2A Capacitor, ceramic AVX 805
1 C15 GRM39X7R104K016D Capacitor, ceramic Murata 603
1 C16 NMC0805X7R224K16TR Capacitor, ceramic NIP 603
1 C17 VJ0603Y222KXANT Capacitor, ceramic Murata 603
1 C18 C0603C223J3RACTU Capacitor, ceramic Kemet 603
1 C19 GRM39X7R223K16 Capacitor, ceramic Murata 603
1 D1 1SMB5919BT3 Diode, zener, 5.6 V On Semi SMB
2 J1, J2 ED1609 Terminal block, 2-pin OST
1 J3 PTC36SAAN Header, 4-pin Sullins
1 JP1 PTC36SAAN Header, 2-pin Sullins
1 L1 UP2B−1R0 Inductor, SMT Coiltronics 0.55 x 0.41
1 L2 UP4B−2R2 Inductor, SMT Coiltronics
4 Q1 − Q4 IRF7811 MOSFET, N−ch, 30 V IR SO8
3 R1, R2, R4 Std Resistor, chip, 4.7 Ω Std 603 1 R3 Std Resistor, chip, 2.49 KΩ Std 603
2 R5, R6 Std Resistor, chip, 0 Ω Std 603
1 R7 Std Resistor, chip, 20 KΩ Std 603
1 R8 Std Resistor, chip, 162 KΩ Std 603
1 R9 Std Resistor, chip, 1.74 KΩ Std 603 1 R10 Std Resistor, chip, 7.32 KΩ Std 603
1 R11 Std Open Std 603
1 R12 Std Resistor, chip, 15 KΩ Std 603
1 R13 Std Resistor, chip, 10 Ω Std 603
1 R14 Std Resistor, chip, 10 KΩ Std 603
4 TP1 − TP3, TP5 240-345 Test point, red, 1 mm Farnell 0.038 1 TP4 131-4244-00 or 131-5031-00 Adaptor, 3.5 mm probe Tektronix 0.200 1 TP6 1045-3-17-15-30-14-02-0 Post, wirewrap Mill-Max 0.043
1 U1 TPS2837D IC, MOSFET driver Texas Instruments SO8
1 U2 TL5002D IC, low-cost PMW Texas Instruments SO8
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TL5002CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL5002IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL5002CDR SOIC D 8 2500 340.5 338.1 20.6 TL5002IDR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2
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