TL4581 TI | Alldatasheet
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DUAL LOW-NOISE HIGH-DRIVE OPERATIONAL AMPLIFIER SLVS457A – JANUARY 2003 – REVISED MARCH 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Equivalent Input Noise Voltage 5 nV/√Hz Typ at 1 kHz /C0068 Unity-Gain Bandwidth. . . 10 MHz Typ /C0068 High Slew Rate...9 V /µs Typ /C0068 Peak-to-Peak Output Voltage Swing
32 V Typ, With VCC ± = ±18 V and RL = 600 Ω
/C0068 Wide Supply-Voltage Range . . .±3 V to ±20 V /C0068 Common-Mode Rejection Ratio. . . 100 dB Typ /C0068 High dc Voltage Gain. . . 100 V/mV Typ /C0068 Applications: Audio PreAmps, Active Filters, Headphone Amps /C0068 End Equipment: DVD/CD/CDRW Players; Set-Top Boxes description/ordering information The TL4581 is a dual operational amplifier that has been designed optimally for audio applications, such as improving tone control. It offers low noise, high-gain bandwidth, good slew, and high output current drive for driving capacitive loads. These features make the TL4581 ideally suited for audio applications, such as audio preamps and active filters. When high output current is required, the TL4581 also can be used as a headphone amplifier.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – P Tube of 50 TL4581P TL4581P 0°Ct o7 0°C SOIC D Tube of 75 TL4581D T45810°C to 70°C SOIC – D Reel of 2500 TL4581DR T4581 SOP – PS Reel of 2000 TL4581PSR T4581 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated 1OUT 1IN– 1IN+ VCC– VCC+ 2OUT 2IN– 2IN+ D, P, OR PS PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
DUAL LOW-NOISE HIGH-DRIVE OPERATIONAL AMPLIFIER SLVS457A – JANUARY 2003 – REVISED MARCH 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC –. 2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage. 3. Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some limiting resistance is used. 4. The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the maximum dissipation rating is not exceeded. 5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC – Supply voltage –5 –15 V TA Operating free-air temperature range 0 70 °C
DUAL LOW-NOISE HIGH-DRIVE OPERATIONAL AMPLIFIER SLVS457A – JANUARY 2003 – REVISED MARCH 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VCC ± = +15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT VIO Input offset voltage VO =0 TA = 25°C 0.5 4 mVVIO Input offset voltage VO = 0 TA = 0°C to 70°C 5 mV IIO Input offset current TA = 25°C 10 150 nAIIO Input offset current TA = 0°C to 70°C 200 nA IIB Input bias current TA = 25°C 200 800 nAIIB Input bias current TA = 0°C to 70°C 1000 nA VICR Common-mode input-voltage range ±12 ±13 V VOPP Maximum peak-to-peak R L ≥ 600 Ω VCC ± = ±15 V 24 26 VVOPP output-voltage swing R L ≥ 600 Ω VCC ± = ±18 V 30 32 V R L ≥ 600 Ω , TA = 25°C 15 50 AVD Large-signal L , VO = ±10 V TA = 0°C to 70°C 10 V/mVAVD gg differential-voltage amplificationR L ≥ 2 kΩ , TA = 25°C 25 100 V/mV L , VO = ±10 V TA = 0°C to 70°C 15 Avd Small-signal differential-voltage amplificationf = 10 kHz 2.2 V/mV BOM Maximum output swing bandwidth R L = 600Ω VO = ±10 V 140 kHzBOM Maximum -output-swing bandwidth R L = 600 Ω VCC ± = ±18 V, VO = ±14 V 100 kHz B1 Unity-gain bandwidth R L = 600 Ω , C L = 100 pF 10 MHz ri Input resistance 30 300 kΩ zo Output impedance AVD = 30 dB, R L = 600 Ω , f = 10 kHz 0.3 Ω CMRR Common-mode rejection ratio VIC = VICR min 70 100 dB kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VCC ± = ±9 V to ±15 V, VO = 0 80 100 dB IOS Output short-circuit current 10 38 60 mA ICC Total supply curent VO = 0, No load 8 16 mA Crosstalk attenuation (VO1 /VO2 ) V01 = 10 V peak, f = 1 kHz 110 dB † All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. operating characteristics, VCC ± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate at unity gain 9 V/µs Overshoot factor VI = 100 mV, R L = 600 Ω , AVD = 1, C L = 100 pF 10 % V Equivalent input noise voltage f = 30 Hz 8 nV/√HzVn Equivalent input noise voltage f = 1 kHz 5 nV/√H z I Equivalent input noise current f = 30 Hz 2.7 pA/√HzIn Equivalent input noise current f = 1 kHz 0.7 pA/√Hz
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL4581D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T4581 TL4581D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T4581 TL4581DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T4581 TL4581DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T4581 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL4581DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL4581D D SOIC 8 75 507 8 3940 4.32 TL4581D.A D SOIC 8 75 507 8 3940 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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