TL3842

TLx84x Current-Mode PWM Controllers datasheet (Rev. J)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLVS038,J]
• PDF pages: 30

Technical content

TLx84x Current-Mode PWM Controllers

1 Features

• Optimized for off-line and DC-to-DC converters
• Low start-up current (< 1mA)
• Automatic feed-forward compensation
• Pulse-by-pulse current limiting
• Enhanced load-response, characteristics
• Undervoltage lockout with hysteresis
• Double-pulse suppression
• High-current totem-pole output
• Internally trimmed bandgap reference
• 500kHz operation
• Error amplifier with low output resistance
• Designed to be interchangeable with UC2842 and UC3842 series

2 Applications

• Switching regulators of any polarity
• Transformer-coupled DC/DC convertors

3 Description

The TL284x and TL384x series of control integrated circuits provide the features that are necessary to implement off-line or DC-to-DC fixed-frequency current-mode control schemes, with a minimum number of external components. Some of the internally implemented circuits are an undervoltage lockout (UVLO), featuring a start-up current of less than 1mA, and a precision reference trimmed for accuracy at the error amplifier input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator (that also provides current-limit control), and a totem-pole output stage designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off state.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TLx84x D (SOIC, 8) 4.90mm × 6.00mm D (SOIC, 14) 8.65mm × 6.00mm P (PDIP, 8) 9.81mm × 9.43mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. D Package 14-Pin SOIC Top View D or P Package 8-Pin SOIC or PDIP Top View TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. D Package 14-Pin SOIC Top View Figure 4-2. D or P Package 8-Pin SOIC or PDIP Top View Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME D D or P COMP 1 1 I/O Error amplifier compensation pin GND 9 5 — Device power supply ground terminal ISENSE 5 3 I Current sense comparator input NC 2, 4, 6, 13 — — Do not connect OUTPUT 10 6 O PWM Output POWER GROUND 8 — — Output PWM ground terminal REF 14 8 O Oscillator voltage reference RT/CT 7 4 I/O Oscillator RC input VC 11 — — Output PWM positive voltage supply VCC 12 7 — Device positive voltage supply VFB 3 2 I Error amplifier input (1) I = Input; O = Output; I/O = Input or Output www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply Voltage(2) Self limiting — VI Analog input voltage range, VFB and ISENSE –0.3 6.3 V VO Output Voltage 35 V VI Input Voltage, VC and D Package only 35 V ICC Supply current 30 mA IO Output current ±1 A error amplifier output sink current 10 mA TJ Virtual junction temperature 150 °C Output energy (capacitive load) 5 µJ Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltages are with respect to the device GND pin.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±2000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VCC and VC(1) Supply Voltage 30 V VI, RT/CT Input Voltage 0 5.5 V VI, VFB and ISENSE Input Voltage 0 5.5 V VO, OUTPUT Output voltage 0 30 V VO, POWER GROUND(1) Output voltage –0.1 1 V ICC Supply current, externally limited 25 mA IO Average output current 200 mA IO(ref) Reference output current –20 mA fOSC Oscillator frequency 100 500 kHz TA Operating free-air temperature TL284x –40 85 TL384x 0 70 (1) These recommended voltages for VC and POWER GROUND apply only to the D package.

5.4 Thermal Information

THERMAL METRIC(1) TLx84x UNITD (SOIC) D (SOIC) P (PDIP)

8 PINS 14 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 117.4 87.9 74.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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5.5 Electrical Characteristics

over operating free-air temperature range, VCC = 15 V(1), RT = 10 kΩ, CT = 3.3 nF (unless otherwise noted) PARAMETER TEST CONDITIONS(2) TL284x TL384x UNIT MIN TYP(2) MAX MIN TYP(2) MAX Reference Section Output voltage IO = 1 mA, TA = 25°C 4.95 5 5.05 4.9 5 5.1 V Line regulation VCC = 12 V to 25 V 6 20 6 20 mV Load regulation IO = 1 mA to 20 mA 6 25 6 25 mV Temperature coefficient of output voltage 0.2 0.4 0.2 0.4 mV/°C Output voltage with worst-case variation VCC = 12 V to 25 V, IO = 1 mA to 20 mA 4.9 5.1 4.82 5.18 V Output noise voltage f = 10 Hz to 10 kHz, TA = 25°C 50 50 µV Output-voltage long-term drift After 1000 h at TA = 25°C 5 25 5 25 mV Short-circuit output current –30 –100 –180 –30 –100 –180 mA Oscillator Section Oscillator frequency(3) TA = 25°C 47 52 57 47 52 57 kHz Frequency change with supply voltage VCC = 12 V to 25 V 2 10 2 10 Hz/kHz Frequency change with temperature 50 50 Hz/kHz peak-to-peak amplitude at RT/CT 1.7 1.7 V Error-Amplifier Section Input bias current –0.3 –1 –0.3 –2 µA Open-loop voltage amplification VO = 2 V to 4 V 65 90 65 90 dB Gain-bandwidth product 0.7 1 0.7 1 MHz Supply-voltage rejection ratio VCC = 12 V to 25 V 60 70 60 70 dB Output sink current VFB, at 2.7 V, COMP at 1.1 V 2 6 2 6 mA Hihg-level output voltage VFB, at 2.3 V, RL = 15 kΩ to GND 5 6 5 6 V Low-level output voltage VFB, at 2.7 V, RL = 15 kΩ to GND 0.7 1.1 0.7 1.1 V Current-sense Section Voltage amplification See(4) (5) 2.85 3 3.13 2.85 3 3.15 V/V Current-sense comparator threshold COMP at 5 V, see(4) 0.9 1 1.1 0.9 1 1.1 V Supply-voltage rejection ratio VCC = 12 V to 25 V, see(4) 70 70 dB Input bias current –2 –10 –2 –10 µA Delay time to output 150 300 150 300 ns Output Section High-level output voltage IOH = –20 mA 13 13.5 13 13.5 V IOH = –200 mA 12 13.5 13 13.5 Low-level output voltage IOH = 20 mA 0.1 0.4 0.1 0.4 V IOH = 200 mA 1.5 2.2 1.5 2.2 Rise time CL = 1 nF, TA = 25°C 25 150 25 150 ns fall time CL = 1 nF, TA = 25°C 25 150 25 150 ns Undervoltage-Lockout Section Start threshold voltage TLx842, TLx844 15 16 17 14.5 16 17.5 V TLx843, TLx845 7.8 8.4 9 7.8 8.4 9 Minimum operating voltage after startup TLx842, TLx844 9 10 11 8.5 10 11.5 V TLx843, TLx845 7 7.6 8.2 7 7.6 8.02 Pulse-Width-Modulator Section www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

5.5 Electrical Characteristics (continued)

over operating free-air temperature range, VCC = 15 V(1), RT = 10 kΩ, CT = 3.3 nF (unless otherwise noted) PARAMETER TEST CONDITIONS(2) TL284x TL384x UNIT MIN TYP(2) MAX MIN TYP(2) MAX Maximum duty cycle TLx842, TLx843 92% 97% 100% 92% 97% 100% TLx844, TLx845 46% 48% 50% 46% 48% 50% Minimum duty cycle 0% 0% Supply Voltage Start-up current 0.5 1 0.5 1 mA Operating supply current VFB and ISENSE at 0 V 11 17 11 17 mA Limiting voltage ICC = 25 mA 39 39 V (1) Adjust VCC above the start threshold before setting it to 15 V. (2) All typical values are at TA = 25°C. (3) Output frequency equals oscillator frequency for the TLx842 and TLx843. Output frequency is one-half the oscillator frequency for the TLx844 and TLx845. (4) These parameters are measured at the trip point of the latch, with VFB at 0 V. (5) Voltage amplification is measured between ISENSE and COMP, with the input changing from 0 V to 0.8 V.

5.6 Typical Characteristics

-75 - 5 0 -25 0 2 5 50 75 100 125 1 5 0 T e m p e r a t u r e ( C ) 7.4 7.6 7.8 8.2 8.4 8.6 8.8 9.2 I DISCHARGE (mA) Figure 5-1. Oscillator Discharge Current vs Temperature for VIN = 15 V and VOSC = 2V VO, Error Amp Output Voltage (V) VTH, Current Sense Input Threshold (A) 0 2 4 6 8 0.2 0.4 0.6 0.8 1.2 D002 Ta = 125 C Ta = 25 C Ta = -55 C Figure 5-2. Current Sense Input Threshold vs Error Amplifier Output Voltage for VIN = 15 V Freq (Hz) Gain (dB) 10 100 1000 10000 100000 1000000 1E+7 -20 -100 0 -50 20 0 40 50 60 100 80 150 100 200 D003 Gain Phase Figure 5-3. Error Amplifier Open-Loop Gain and Phase vs Frequency VCC = 15 V, RL = 100 kΩ, and TA = 25 °C 0 . 1 1 10 0.2 0.3 0.5 2 3 5 R T , T i m i n g R e s i s t o r ( k Ω ) 1 0 0 D MAX , Maximum Output Duty Cycle (%) Figure 5-4. Max Output Duty Cycle vs Timing Resistor for VCC = 15, CT = 3.3 nF, TA = 25 °C TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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5.6 Typical Characteristics (continued)

IO, Output Load Current (mA) Source Saturation Voltage (V) Sink Saturation Voltage (V) 0 100 200 300 400 500 600 700 800 -10 0 -9 1 -8 2 -7 3 -6 4 -5 5 -4 6 -3 7 -2 8 -1 9 0 10 D005 Source Saturation at 25 C Source Saturation at -55 C Sink Saturation at -55 C Sink Saturation at 25 C Figure 5-5. Output Saturation Voltage vs Load Current for VCC =

15 V with 5-ms Input Pulses

Temperature (C) ISC (mA) -75 -50 -25 0 25 50 75 100 125 150 100 120 140 160 180 D006 Figure 5-6. Reference Short Circuit Current vs Temperature for VIN = 15 V Source Current (mA) Reference Voltage Delta (mV) 0 20 40 60 80 100 120 140 160 -60 -50 -40 -30 -20 -10 D007 Ta = 125 C Ta = 25 C Ta = -40 C Figure 5-7. Reference Voltage vs Source Current Temperature (C) VREF (V) -75 -50 -25 0 25 50 75 100 125 150 4.8 4.85 4.9 4.95 5.05 5.1 5.15 5.2 D008 Figure 5-8. Reference Voltage vs Temperature 1 10 1002 3 5 20 30 50 C T , T i m i n g C a p a c i t a n c e ( n F ) 0.1 100 0.2 0.3 0.5 Dead Time(μs) V C C = 1 5 V R T ≥ 5 k Ω T A = 2 5 o C Figure 5-9. Dead Time vs Timing Capacitance 0.1 1 10 100 10000.3 3 30 300 f , F r e q u e n c y ( kHz ) 100 R T ,Timing Resistance(kΩ) n F T C n F T C n F T C n F T C n F T C n F T C n F T C V C C = 1 5 V T A = 2 5 o C Figure 5-10. Timing Resistance vs Frequency www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

6 Detailed Description

6.1 Overview

The TL284x and TL384x series of control integrated circuits provide the features that are necessary to implement off-line or DC-to-DC fixed-frequency current-mode control schemes, with a minimum number of external components. Some of the internally implemented circuits are an undervoltage lockout (UVLO), featuring a start-up current of less than 1 mA, and a precision reference trimmed for accuracy at the error amplifier input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator (that also provides current-limit control), and a totem-pole output stage designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off state. Major differences between members of these series are the UVLO thresholds and maximum duty-cycle ranges. Typical UVLO thresholds of 16 V (on) and 10 V (off) on the TLx842 and TLx844 devices make them ideally suited to off-line applications. The corresponding typical thresholds for the TLx843 and TLx845 devices are 8.4 V (on) and 7.6 V (off). The TLx842 and TLx843 devices can operate to duty cycles approaching 100%. A duty-cycle range of 0 to 50% is obtained by the TLx844 and TLx845 by the addition of an internal toggle flip-flop, which blanks the output off every other clock cycle. The TL284x-series devices are characterized for operation from −40°C to +85°C. The TL384x devices are characterized for operation from 0°C to 70°C.

6.2 Functional Block Diagram

A A. The toggle flip-flop is present only in TL2844, TL2845, TL3844, and TL3845. Pin numbers shown are for the D (14-pin) package.

6.3 Feature Description

6.3.1 Pulse-by-Pulse Current Limiting

Pulse-by-pulse limiting is inherent in the control scheme. An upper limit on the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while ensuring reliable supply operation TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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6.3.2 Error Amplifier With Low Output Resistance

With a low output resistance, various impedance networks may be used on the compensation pin input for error amplifier feedback.

6.3.3 High-Current Totem-Pole Output

The output of the TLx84x devices can sink or source up to 1 A of current.

6.4 Device Functional Modes

6.4.1 Shutdown Technique

The PWM controller (see Figure 6-1 ) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (see Functional Block Diagram ). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset. Figure 6-1. Shutdown Techniques

6.4.2 Slope Compensation

A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 6-2). Note Capacitor C forms a filter with R2 to suppress the leading-edge switch spikes. Figure 6-2. Slope Compensation www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Typical Application

The following application is an open-loop laboratory test fixture. This circuit demonstrates the setup and use of the TL284x and TL384x devices and their internal circuitry. In the open-loop laboratory test fixture (see Figure 7-1), high peak currents associated with loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to the GND terminal in a single-point ground. The transistor and 5-k Ω potentiometer sample the oscillator waveform and apply an adjustable ramp to the ISENSE terminal. Figure 7-1. Open-Loop Laboratory Test Fixture

7.1.1 Design Requirements

The design techniques in the following sections may be used for power supply PWM applications which fall within the following requirements.

• 500-kHz or lower operation
• 30-V or less output voltage
• 200-mA or less output current TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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7.1.2 Detailed Design Procedure

7.1.2.1 Current-Sense Circuit

A. Peak current (IS) is determined by the formula: /c40 /c41S max S

1 VI R/c61 A small RC filter formed by resistor Rf and capacitor Cf may be required to

suppress switch transients. Figure 7-2. Current-Sense Circuit Schematic

7.1.2.2 Error-Amplifier Configuration

A. Error amplifier can source or sink up to 0.5 mA. Figure 7-3. Error-Amplifier Configuration Schematic

7.1.2.3 Oscillator Section

A. For RT > 5 kΩ: T T 1.72f R C/c187 Figure 7-4. Oscillator Section Schematic www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

7.1.3 Application Curve

The application curve shows oscillator characteristics for chosen capacitor and resistor values. 0 5 10 15 20 25 30 35 40 45 V C C – S u p p l y V o l t a g e – V I CC – Supply Current – mA T L T L Figure 7-5. Supply Current vs Supply Voltage

7.2 Power Supply Recommendations

See Recommended Operating Conditions for the recommended power supply voltages for the TL284x and TL384x devices. TI also recommends to have a decoupling capacitor on the output of the device's power supply to limit noise on the device input.

7.3 Layout

7.3.1 Layout Guidelines

Always try to use a low EMI inductor with a ferrite type closed core. Some examples would be toroid and encased E core inductors. Open core can be used if they have low EMI characteristics and are located a bit more away from the low power traces and components. Make the poles perpendicular to the PCB as well if using an open core. Stick cores usually emit the most unwanted noise.

7.3.1.1 Feedback Traces

Try to run the feedback trace as far from the inductor and noisy power traces as possible. Also, keep the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but keeping it away from inductor EMI and other noise sources is the more critical of the two. Run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two.

7.3.1.2 Input/Output Capacitors

When using a low value ceramic input filter capacitor, it should be located as close to the V CC pin of the IC as possible. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner voltage supply. Some designs require the use of a feed-forward capacitor connected from the output to the feedback pin as well, usually for stability reasons. In this case it should also be positioned as close to the IC as possible. Using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into the effective antenna created by through-hole components.

7.3.1.3 Compensation Components

External compensation components for stability should also be placed close to the IC. Surface mount components are recommended here as well for the same reasons discussed for the filter capacitors. These should not be located very close to the inductor either. TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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7.3.1.4 Traces and Ground Planes

Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. The inductor, output capacitors, and output diode should be as close to each other possible. This helps reduce the EMI radiated by the power traces due to the high switching currents through them. This will also reduce lead inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of the PCB. This will reduce noise as well by reducing ground loop errors as well as by absorbing more of the EMI radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to separate the power plane (where the power traces and components are) and the signal plane (where the feedback and compensation and components are) for improved performance. On multi-layer boards the use of vias will be required to connect traces and different planes. It is good practice to use one standard via per 200 mA of current if the trace will need to conduct a significant amount of current from one plane to the other. Arrange the components so that the switching current loops curl in the same direction. Due to the way switching regulators operate, there are two power states. One state when the switch is on and one when the switch is off. During each state there will be a current loop made by the power components that are currently conducting. Place the power components so that during each of the two states the current loop is conducting in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces radiated EMI.

7.3.2 Layout Example

2 VFB

4 RT/CT 13

Figure 7-6. Layout of D-8 or P Package for TLx84x Devices www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

8 Device and Documentation Support

8.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (July 2016) to Revision J (October 2024) Page

• Changed the OUTPUT SECTION: Rise and fall time, typical value from 50ns to 25ns in the Electrical
• Changed the PWM: maximum duty cycle of TLx842/3B, minimum value from 95% to 92% in the Electrical
• Changed the TOTAL STANDBY CURRENT, VCC Zener voltage, typical value from 34V to 39V in the
• Updated the Typical Characteristics graphs for Idischarge vs Ta, Maximum Duty Cycle vs Rt, Deadtime vs Ct, Rt Changes from Revision H (January 2015) to Revision I (July 2016) Page
• Changed TLx842, TLx844 to TLx842, TLx843 and TLx843, TLx845 to TLx844, TLx845 in Pulse-Width- TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 www.ti.com

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Changes from Revision G (February 2008) to Revision H (January 2015) Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TL2842, TL2843, TL2844, TL2845 TL3842, TL3843, TL3844, TL3845 SLVS038J – JANUARY 1989 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845

www.ti.com 22-May-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL2842D Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 TL2842 TL2842D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL2842 TL2842DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TL2842 TL2842DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TL2842 TL2842DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TL2842 TL2842DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 TL2842 TL2842P NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2842P TL2842P.A NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2842P TL2843D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL2843 TL2843DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2843 TL2843DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2843 TL2843DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2843 TL2843DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2843 TL2843DRE4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2843 TL2843DRG4-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2843 TL2843P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2843P TL2843P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2843P TL2844D Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 TL2844 TL2844D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL2844 TL2844DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2844 TL2844DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2844 TL2844DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2844 TL2844DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2844 TL2844DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2844 TL2844P NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2844P TL2844P.A NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2844P TL2844PE4 NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2844P TL2845D Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 TL2845 TL2845D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL2845 Addendum-Page 1

www.ti.com 22-May-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL2845DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2845 TL2845DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2845 TL2845DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2845 TL2845DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2845 TL2845DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL2845 TL2845P NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2845P TL2845P.A NRND Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL2845P TL3842D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL3842 TL3842DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL3842 TL3842DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL3842 TL3842DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL3842 TL3842DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL3842 TL3842DRE4-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL3842 TL3842P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3842P TL3842P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3842P TL3842PE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3842P TL3843D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL3843 TL3843D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL3843 TL3843DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3843 TL3843DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3843 TL3843DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3843 TL3843DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3843 TL3843P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3843P TL3843P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3843P TL3844D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL3844 TL3844D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL3844 TL3844DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3844 TL3844DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3844 TL3844DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3844 TL3844DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3844 TL3844P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3844P Addendum-Page 2

www.ti.com 22-May-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL3844P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3844P TL3844PE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3844P TL3845D Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3845 TL3845D-8 Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL3845 TL3845D.A Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3845 TL3845DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3845 TL3845DR-8 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3845 TL3845DR-8.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3845 TL3845DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3845 TL3845P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3845P TL3845P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3845P TL3845PE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3845P (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 3

www.ti.com 22-May-2026 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL2842DR SOIC D 14 2500 353.0 353.0 32.0 TL2842DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL2843DR SOIC D 14 2500 353.0 353.0 32.0 TL2843DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL2844DR SOIC D 14 2500 353.0 353.0 32.0 TL2844DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL2845DR SOIC D 14 2500 353.0 353.0 32.0 TL2845DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL3842DR SOIC D 14 2500 353.0 353.0 32.0 TL3842DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL3843DR SOIC D 14 2500 353.0 353.0 32.0 TL3843DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL3844DR SOIC D 14 2500 353.0 353.0 32.0 TL3844DR-8 SOIC D 8 2500 353.0 353.0 32.0 TL3845DR SOIC D 14 2500 353.0 353.0 32.0 TL3845DR-8 SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL2842P P PDIP 8 50 506 13.97 11230 4.32 TL2842P.A P PDIP 8 50 506 13.97 11230 4.32 TL2843P P PDIP 8 50 506 13.97 11230 4.32 TL2843P.A P PDIP 8 50 506 13.97 11230 4.32 TL2844P P PDIP 8 50 506 13.97 11230 4.32 TL2844P.A P PDIP 8 50 506 13.97 11230 4.32 TL2844PE4 P PDIP 8 50 506 13.97 11230 4.32 TL2845P P PDIP 8 50 506 13.97 11230 4.32 TL2845P.A P PDIP 8 50 506 13.97 11230 4.32 TL3842P P PDIP 8 50 506 13.97 11230 4.32 TL3842P.A P PDIP 8 50 506 13.97 11230 4.32 TL3842PE4 P PDIP 8 50 506 13.97 11230 4.32 TL3843P P PDIP 8 50 506 13.97 11230 4.32 TL3843P.A P PDIP 8 50 506 13.97 11230 4.32 TL3844P P PDIP 8 50 506 13.97 11230 4.32 TL3844P.A P PDIP 8 50 506 13.97 11230 4.32 TL3844PE4 P PDIP 8 50 506 13.97 11230 4.32 TL3845D D SOIC 14 50 506.6 8 3940 4.32 TL3845D.A D SOIC 14 50 506.6 8 3940 4.32 TL3845P P PDIP 8 50 506 13.97 11230 4.32 TL3845P.A P PDIP 8 50 506 13.97 11230 4.32 TL3845PE4 P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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