TL3695

Differential Bus Transceiver datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLLS044,D]
• PDF pages: 23

Technical content

DIFFERENTIAL BUS TRANSCEIVER SLLS044D − NOVEMBER 1988 − REVISED DECEMBER 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Bidirectional Transceiver /C0068Meets or Exceeds the Requirements of TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendation V.11 /C0068High-Speed Advanced Low-Power Schottky Circuitry /C0068Low Skew ...6 n s M a x /C0068Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments /C0068Low Supply-Current Requirements . . . 30 mA Max /C0068Wide Positive and Negative Input/Output Bus-Voltage Ranges /C0068Driver Output Capacity . . . ±60 mA /C0068Thermal-Shutdown Protection /C0068Driver Positive and Negative Current Limiting /C0068Receiver Input Impedances...1 2 k Ω Min /C0068Receiver Input Sensitivity... ±200 mV Max /C0068Receiver Input Hysteresis . . . 120 mV Typ /C0068Fail Safe ...H igh Receiver Output With Inputs Open /C0068Operates From a Single 5-V Supply /C0068Glitch-Free Power-Up and Power-Down Protection /C0068Interchangeable With National DS3695 and DS3695A

description

The TL3695 differential bus transceiver is designed for bidirectional data communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendation V.11. The TL3695 combines a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can be externally connected together to function as a directional control. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or V CC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party line applications. The TL3695 is characterized for operation from 0°C to 70°C. Copyright © 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. R RE DE D VCC B A GND D OR P PACKAGE (TOP VIEW)

DIFFERENTIAL BUS TRANSCEIVER SLLS044D − NOVEMBER 1988 − REVISED DECEMBER 1999

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(D) PLASTIC DIP (P) 0°C to 70°C TL3695D TL3695P The D package is available taped and reeled. Add the suffix R to device type (e.g., TL3695DR). Function Tables DRIVER INPUT ENABLE OUTPUTSINPUT D ENABLE DE A B H H H L L H L H X L Z Z H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) RECEIVER DIFFERENTIAL INPUTS ENABLE OUTPUTDIFFERENTIAL INPUTS A − B ENABLE RE OUTPUT R VID ≥ 0.2 V L H −0.2 V < VID < 0.2 V L ? VID ≤ −0.2 V L L X H Z Inputs open L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. EN13DE EN22 A61 B71 R 1 2 RE logic diagram (positive logic) 3DE Bus RE

DIFFERENTIAL BUS TRANSCEIVER SLLS044D − NOVEMBER 1988 − REVISED DECEMBER 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic of inputs and outputs EQUIVALENT OF EACH INPUT VCC R(eq) Input Driver Input: R(eq) = 3 kΩ NOM Enable Inputs: R(eq) = 8 kΩ NOM R(eq) = equivalent resistor TYPICAL OF A AND B I/O PORTS VCC 180 kΩ NOM Connected on A Port 180 kΩ NOM Connected on B Port A or B 18 kΩ NOM 3 kΩ NOM 1.1 kΩ NOM TYPICAL OF RECEIVER OUTPUT VCC 85 Ω NOM Output absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51.

DIFFERENTIAL BUS TRANSCEIVER SLLS044D − NOVEMBER 1988 − REVISED DECEMBER 1999

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recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V Voltage at any bus terminal (separately or common mode) V or V VVoltage at any bus terminal (separately or common mode), VI or VIC −7 V High-level Input voltage, VIH D, DE, and RE 2 V Low-level Input voltage, VIL D, DE, and RE 0.8 V Differential input voltage, VID (see Note 3) ±12 V High level output current I Driver −6 0 mA High-level output current, IOH Receiver − 400 μA Low level output current I Driver 60 mALow-level output current, IOL Receiver 8 mA Operating free-air temperature, TA 0 70 °C NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

DIFFERENTIAL BUS TRANSCEIVER SLLS044D − NOVEMBER 1988 − REVISED DECEMBER 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT VIK Input clamp voltage II = −18 mA −1.5 V VO Output voltage IO = 0 0 6 V |VOD1| Differential output voltage IO = 0 1.5 5 V R 100 Ω See Figure 1 1/2VOD1 V |VOD2| Differential output voltage RL = 100 Ω, See Figure 1 1/2VOD1 or 2§ V |VOD2| Differential output voltage RL = 54 Ω, See Figure 1 1.5 2.5 5 V VOD3 Differential output voltage Vtest = −7 V to 12 V, See Figure 2 1.5 5 V Δ |VOD| Change in magnitude of differential output voltage¶ ±0.2 V VOC Common-mode output voltage RL = 54 Ω, See Figure 1 3 V Δ |VOC| Change in magnitude of common-mode output voltage¶ RL 54 Ω, See Figure 1 ±0.2 V I Output current Output disabled, VO = 12 V 1 mAIO Output current Output disabled, See Note 4 VO = −7 V −0.8 mA IIH High-level input current VI = 2.4 V 20 μA IIL Low-level input current VI = 0.4 V −200 μA VO = −6 V −250 I Short circuit output current# VO = 0 −150 mAIOS Short-circuit output current# VO = VCC 250 mA VO = 8 V 250 I Supply current No load Outputs enabled 23 50 mAICC Supply current No load Outputs disabled 19 35 mA † The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs. ‡ All typical values are at VCC = 5 V and TA = 25°C. § The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater. ¶ Δ |VOD| and Δ |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. # Duration of the short circuit should not exceed one second for this test. NOTE 4: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not a pply for a combined driver and receiver terminal. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT td(OD) Differential-output delay time 8 22 ns Skew (|td(ODH) − td(ODL)|) CL1 = CL2 = 100 pF, RL = 60 Ω, See Figure 3 1 8 ns tt(OD) Differential output transition time CL1 CL2 100 pF, RL 60 Ω, See Figure 3 8 18 ns tPZH Output enable time to high level CL = 100 pF, RL = 500 Ω, See Figure 4 50 ns tPZL Output enable time to low level CL = 100 pF, RL = 500 Ω, See Figure 5 50 ns tPHZ Output disable time from high level CL = 15 pF, RL = 500 Ω, See Figure 4 8 30 ns tPLZ Output disable time from low level CL = 15 pF, RL = 500 Ω, See Figure 5 8 30 ns ‡ All typical values are at VCC = 5 V and TA = 25°C.

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DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A VO Voa, Vob Voa, Vob |VOD1| Vo Vo |VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω) |VOD3| Vt (test termination measurement 2) Vtest Vtst VOC |Vos| |Vos| IOS | Isa |, | Isb | IO | Ixa |, | Ixb | Iia, Iib RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = −0.4 mA 0.2 V VIT− Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA −0.2 ‡ V Vhys Hysteresis voltage (VIT+−V IT−) VOC = 0 70 mV VIK Enable-input clamp voltage II = −18 mA −1.5 V V High level output voltage VID = 200 mV or inputs open, 24 VVOH High-level output voltage VID = 200 mV or inputs open, IOH = −400 μA, See Figure 6 2.4 V V Low level output voltage VID = −200 mV, IOL = 16 mA 0.5 VVOL Low-level output voltage VID = 200 mV, See Figure 6 IOL = 8 mA 0.45 V IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 μA I Line input current Other input = 0, VI = 12 V 1 mAII Line input current Other input = 0, See Note 5 VI = −7 V −0.8 mA IIH High-level enable-input current VIH = 2.7 V 20 μA IIL Low-level enable-input current VIL = 0.4 V −100 μA rI Input resistance 12 kΩ IOS Short-circuit output current§ VO = 0 −15 −85 mA I Supply current No load Outputs enabled 23 50 mAICC Supply current No load Outputs disabled 19 35 mA † All typical values are at VCC = 5 V and TA = 25°C. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. § Duration of the short circuit should not exceed one second for this test. NOTE 5: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions.

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0 V to 3 V 3 V

NOTES: A. C L includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms

3 V or 0 V

NOTES: A. C L includes probe and jig capacitance. Figure 5. Driver Test Circuit and Voltage Waveforms

Figure 6. Receiver VOH and VOL

0 V 0 V

NOTES: A. C L includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms

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NOTES: A. C L includes probe and jig capacitance. Figure 8. Receiver Test Circuit and Voltage Waveforms

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TYPICAL CHARACTERISTICS† Figure 12 −10 RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT IOH − High-Level Output Current − mA V0H − High-Level Output Voltage − VVOH VCC = 5.25 V VCC = 4.75 V −20 −30 −40 −50 VID = 0.2 V TA = 25°C VCC = 5 V 2 0 2 04 06 08 0 100 120 RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE V0H − High-Level Output Voltage − VVOH TA − Free-Air Temperature − °C −40 −20 VCC = 5 V VID = 200 mV IOH = −440 μA Figure 13 Figure 14 0.3 0.2 0.1 051 0 0.4 0.5 0.6 15 20 25 30 RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT IOL − Low-Level Output Current − mA VOL − Low-Level Output Voltage − VVOL VCC = 5 V TA = 25°C Figure 15 −40 0.3 0.2 0.1 02 0 4 0 6 0 0.4 0.5 0.6 80 100 120 RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE VOL − Low-Level Output Voltage − VVOL TA − Free-Air Temperature − °C VCC = 5 V VID = −200 mV IOL = 8 mA −20 † Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL3695D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3695 TL3695D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3695 TL3695DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3695 TL3695DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3695 TL3695DRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL3695 TL3695P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3695P TL3695P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL3695P (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 11-Nov-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL3695DR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL3695D D SOIC 8 75 507 8 3940 4.32 TL3695D.A D SOIC 8 75 507 8 3940 4.32 TL3695P P PDIP 8 50 506 13.97 11230 4.32 TL3695P.A P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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