TL331 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Wide Single Supply V oltage Range or Dual Supplies
- Low Supply Current: 0.5 mA Typical
- Low Input Bias Current: 25 nA Typical
- Low Input Offset Current: ±5 nA Typical
- Low Input Offset V oltage: ±2 mV Typical
- Input Common Mode V oltage Range includes Ground
- Low Output Saturation V oltage: 150 mV Typ at IO = 4 mA
- Differential Input V oltage Range Equal to the Supply V oltage
- TTL, DTL, ECL, CMOS Compatible Devices
- TL331V for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable*
- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant VEE VEE VCC IN+ IN− VEE Vout www.onsemi.com TSOP−5 SN SUFFIX CASE 483 TL3 = Specific Device Code A = Assembly Location Y = Year W = Work Week /C0071= Pb−Free Package TL3AYW/C0071 /C0071 (Note: Microdot may be in either location) Device Package Shipping †
ORDERING INFORMATION
TL331SN4T3G TSOP−5 (Pb−Free) 3000 / Tape & Reel MARKING DIAGRAM
4 OUT
VCCIN− VEE IN+ PIN CONNECTIONS †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. TL331VSN4T3G* TSOP−5 (Pb−Free) 3000 / Tape & Reel
Table 1. MAXIMUM RATINGS (Over operating free−air temperature, unless otherwise stated) should not be assumed, damage may occur and reliability may be affected.
- Positive excursions of the input voltage may exceed the power supply level. The low input voltage state must not be less than 0.3 V below
- Short circuits from the output to V
Table 2. THERMAL INFORMATION (Note 3)
- Short−circuits can cause excessive heating and destructive dissipation. These values are typical.
- Values based on a 1S standard PCB according to JEDEC 51−3 with 1.0 oz copper and a 400 mm 2 copper area
- Values based on a 1S2P standard PCB according to JEDEC 51−7 with 1.0 oz copper and a 25 mm 2 copper area
Table 3. OPERATING CONDITIONS the Recommended Operating Ranges limits may affect device reliability.
Table 4. ELECTRICAL CHARACTERISTICS (Vs=+5.0 V, At TA = +25°C, VCM = mid−supply, unless otherwise noted) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- The input common mode voltage of either input signal should not be allowed to go negative by more than 0.3 V. The upper end of the common
mode voltage range is VCC – 1.5 V, but either or both inputs can go to +36 V without damage.
- Positive excursions of the input voltage may exceed the power supply level. As long as the other voltage remains within the common mode
- TL331 is an open collector comparator. Rise time is a function of the RC time constant. A 5.1 k /C0087 pull−up resistor was used for these
Figure 5. Low−to−High Propagation Delay vs. Figure 6. High−to−Low Propagation Delay vs. Figure 7. Quiescent Current vs. Temperature
1.0 INPUT (V)
Figure 8. Low Level Output Voltage vs. Output
TSOP−5 CASE 483 ISSUE N DATE 12 AUG 2020 SCALE 2:1 XXX M/C0071 /C0071 GENERIC MARKING DIAGRAM* 0.7 0.028 1.0 0.039 /C0466mm inches/C0467SCALE 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week /C0071= Pb−Free Package XXXAYW/C0071 /C0071 Discrete/LogicAnalog (Note: Microdot may be in either location) XXX = Specific Device Code M = Date Code /C0071= Pb−Free Package NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY . DIM MIN MAX MILLIMETERS A B C 0.90 1.10 D 0.25 0.50 G 0.95 BSC H 0.01 0.10 J 0.10 0.26 K 0.20 0.60 M 0 10 S 2.50 3.00 12 3 S A G B D H C J /C0095/C0095 0.20 C ABT0.102X 2X T0.20 NOTE 5 C SEATING PLANE 0.05 K M DETAIL Z DETAIL Z TOP VIEW SIDE VIEW A B END VIEW 1.35 1.65 2.85 3.15 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ARB18753CDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1TSOP−5 © Semiconductor Components Industries, LLC, 2018 www.onsemi.com
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