TL191CN TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 6
Technical content
TL182, TL185, TL188, TL191 BI-MOS SWITCHES 02234, JUNE 1976—REVISED SEPTEMBER 1986 © Functionally Interchangeable with Siliconix © Uniform On-State Resistance for Minimum. DG182, DG185, DG188, DG191 with Same Signal Distortion Terminal Assignments @ +10-V Analog Voltage Range © Monolithic Construction © TTL, MOS, and CMOS Logic Control © Adjustable Reference Voltage Compatibility © JFET Inputs qus2 et N PACKAGE Gescription (TOP VIEW) The TL182, TL185, TL188, and TL191 are sf Ump 2s monolithic high-speed analog switches using Bl 1oG2 136} 20 MOS technology. They comprise JFET-input neGa 12h Nc buffers, level translators, and output JFET nee fp Nc switches. The TL182 switches are SPST; the 1s sof] 24 TL185 switches are SPDT. The TL188 is a pair vecHe of} v ra cc EE of complementary SPST switches as is each half vic G sf Vier of the TL191. A high level at a control input of the TL182 turns T1185 the associated switch off. A high level at a N PACKAGE control input of the TL185 turns the associated (rop VIEW) switch on. For the TL188, a high level at the 101 Cf, OreD 181 control input turns the associated switches $1 ncCj2 isf]1a on and S2 off. 102(]3 sal] Vee The threshold of the input buffer is determined 1 He ian ver by the voltage applied to the reference input ote lve (Vref). The input threshold is related to neH> woh) red the reference input by the equation zo2Ge ‘S282 Vth = Vref + 1.4. Thus, for TTL compati- bility, the Vref input is connected to ground. The. qLi88 JFET input makes the device compatible with N PACKAGE bipolar, MOD, and CMOS logic families (TOP VIEW Threshold compatibility may, again, be ne (fay ne determined by Vth = Vref +1.4 V. Ne? 13t)Ne The output switches are junction field-effect ors 12h} 2 transistors featuring low on-state resistance and si(js nf s2 high off-state resistance. The monolithic aC}s — 10f} nc structure ensures uniform matching. vee Ue 30) Vee BI-MOS technology is a major breakthrough in vic Q2_sh) Veet linear integrated circuit processing. BI-MOS can q91 have ion-implanted JFETs, p-channel MOS-FETs, N PACKAGE plus the usual bipolar components all on the (Top views same chip. BLMOS provides for monolithic tor fr Od 1s circuit designs that previously have been Nee Elia available only as expensive hybrids. wots \\eE] vee M-suffix devices are characterized for operation 182s 1310 Vier over the full military temperature range of 2s2s Dv -55°C to 125°C. I-suffix devices are 202s uP) vec characterized for operation from -25°C to ne (7 —10f) 2a 85°C, and C-suffix devices are characterized for 201 Js__af} 281 operation from 0°C to 70°C. NC_No internal connection —_ ee PRODUCTION DATA dovanests contaa Information Copyraht © 1984, Texas Instruments Incorporsted Start rity: eacon iprocassing docs ot TEXAS stzuaery cde test ol paromsre INSTRUMENTS POST OFFICE BOX 655203 « OALLAS, TEXAS 75265, La)
TL182, TL185 BI-MOS SWITCHES oo TL182 TWIN SPST SWITCH schematic (each channel) symbol Vit Vee f 4] roommen nace } . 1” (s) in ss] _+4Le,, i b $ » $s sa J 2a 110) ae rs rs | 25 Lt) AL 13) 05 as fx FUNCTION TABLE (EACH HALF) i ff TWPUT SwiTcH { 3 A s aoe {jf t ‘ON (CLOSED) TO OTHER HALF H OFF (OPEN) Vee Vret ee TL185 TWIN DPST SWiTCH schematic (each channel) symbol Viet Yeo }ro OTHER HALF 1” (15) bt i 2 -_ Lo 12 (a) — Le 12 st Gor A be 2s1 SL] ——_ |) a0 2s2-8} ——_ 18) 252 FUNCTION TABLE (EACH HALF) iNPuT | SWITCHES a__|_swiano swe OFF (OPEN) TO OTHER HALF On cLoseb) VEE Vret rn TEXAS 4 INSTRUMENTS 7-4 POST OFFICE BOX 655303 + DALLAS, TEXAS 75265
L188, TL191 BI-MOS SWITCHES SE TL188 DUAL COMPLEMENTARY SPST SWITCH schematic symbol Yuu Vec A (5) s 2 (1) val (12) bz A oz FUNCTION TABLE INPUT SWITCHES A swt swe OFF (OPEN) ON (CLOSED) ON (CLOSED) _OFF (OPEN) Vee Vret EERE . TL191 TWIN DUAL COMPLEMENTARY SPST SWITCH schematic (each channel) symbol Mic Yee ro omer Hate watts o qs1 29) Ls 182 (a) —t (3) 102 st , a D2 281 {9) —— s) 201 ve) tL 202 FUNCTION TABLE A swt swe OFF (OPEN) ON (CLOSED) ON (CLOSED) _OFF (OPEN) }roomen wate VEE Vref i TEXAS 4 INSTRUMENTS
TL182, TL185, TL188, TL191 BI-MOS SWITCHES functional block diagram DonD1 pe | 1 > - a 7 ! sors1 8 See the preceding two pages for operation of the switches. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Positive supply to negative supply voltage, Vcc - Vee . sees CY Positive supply voltage to either drain, Vcc - Vp . . : 33V Drain to negative supply voltage, Vp - VEE . . . 33.V Logic supply to logic input voltage, VLL - Vi ee ceeee bees ceeeeee, 83V Logic supply to reference voltage, Vit - Vret 33 V Logic input to reference voltage, Vi — Vref . 33.V Reference to logic input voltage, Vref — V).. . ne 2] Current (any terminal) vee . . cae ae ae vere eeee. B3OMA Operating free-air temperature range: TL182M, TL185M, TL188M, TL191M -55°C to 125°C TL182I, TL1851, TL188I, TL1911 —25°C to 85°C Storage temperature range eee eens ween eee seeseeeees =65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds vee wae . 260°C a TEXAS % INSTRUMENTS 76 FOST OFFICE BOX 658303» DALLAS. TEXAS 75265
TL182, TL185, TL188, TL191 BI-MOS SWITCHES i z ° 7 2 > a 3 ' 2 Fle}. |” io a 8 jelz e . F yer" 5 5 > 2 > ° Py ' 5 ‘ ‘ > = ‘SIslF , ae - x x lp >
2 S lolx) = lolxlolslole|8lxl8]z| ¢ ° 6
iS £ jels| 2 jets |s|3le]zl2|3|2/3| = & t [Flale © P lslel * lelslslsielspistls| =x | oy ‘ < s s i aig > 2|8 8 8/2 5 8 ar ele e q : is > H Fa sje s|i 5] Fs > > w oF rs en ee 3 2 wl 2te uy veleeee be 3 = |>|8)2 uy gslysles| os H : . 8 > - i 3 z\\2l q : i 2 > >slosles| 35 3 3 e[ slo 1 " e x} oF € € Fle i) : dela taada | 2 ° g Ele s |SVEIEIEIEEl-| & « Fs 2 |e l2 jf | 2) s jee] of JElE]Elelelil 4
2 B sl8 sls lB =| E] 2 |B 5/5 (2/5| £8 $
8 ERE SUE S/F 3) S| 2 les) 22 [alzleléletelzl§) $s [EE
§ eale slealsz)2]2 2 2] ¢% |ssyeieyeyeys = s SRERE HEE Sl] s ls2) S& lalalalalaalajal S| & [sls s 3 o| 2/55 3 fa £| 2 [Fle 2 + = El\\é¢ 3 5 NT Texas INSTRUMENTS
- Vo is the steady-state output with the switch on. Feed through via the gate capacitance may result in spikes {not shown) at
FIGURE 1. VOLTAGE WAVEFORMS.