TL081ACP

TL081 TI | Alldatasheet

Document overview

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Technical content

TL08xx FET-Input Operational Amplifiers

1 Features

• High slew rate: 20V/μs (TL08xH, typ)
• Low offset voltage: 1mV (TL08xH, typ)
• Low offset voltage drift: 2μV/°C
• Low power consumption: 940μA/ch (TL08xH, typ)
• Wide common-mode and differential voltage ranges – Common-mode input voltage range includes VCC+
• Low input bias and offset currents
• Low noise: Vn = 37nV/√Hz (typ) at f = 1kHz
• Output short-circuit protection
• Low total harmonic distortion: 0.003% (typ)
• Wide supply voltage: ±2.25V to ±20V, 4.5V to 40V

2 Applications

• Solar energy: string and central inverter
• Motor drives: AC and servo drive control and power stage modules
• Single phase online UPS
• Three phase UPS
• Pro audio mixers
• Battery test equipment

3 Description

The TL08xH (TL081H, TL082H, and TL084H) family of devices are the next-generation versions of the industry-standard TL08x (TL081, TL082, and TL084) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1mV, typical), high slew rate (20V/ μs), and common-mode input to the positive supply. High ESD (1.5kV, HBM), integrated EMI and RF filters, and operation across the full –40°C to 125°C enable the TL08xH devices to be used in the most rugged and demanding applications. Device Information PART NUMBER CHANNEL COUNT PACKAGE(1) TL081x Single P (PDIP, 8) DCK (SC70, 5) PS (SO, 8) D (SOIC, 8) DBV (SOT-23, 5) TL082x Dual P (PDIP, 8) PS (SO, 8) D (SOIC, 8) DDF (SOT-23, 8) PW (TSSOP, 8) TL082M Dual JG (CDIP, 8) FK (LCCC, 20) TL084x Quad N (PDIP, 14) D (SOIC, 14) DYY (SOT-23, 14) PW (TSSOP, 14) TL084M Quad J (CDIP, 14) FK (LCCC, 20) (1) For more information, see Section 11. IN+ IN- OUT OFFSET N1 OFFSET N2 TL081 (SO, 8) Only IN+ IN- OUT TL081 (Each Amplifier) TL082 (Each Amplifier) TL084 (Each Amplifier) Logic Symbols TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

5.8 Electrical Characteristics (DC): TL08xC,

5.9 Electrical Characteristics (AC): TL08xC,

11 Mechanical, Packaging, and Orderable

TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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4 Pin Configuration and Functions

VCC– IN+ VCC+ IN– Not to Scale Figure 4-1. TL081H: DBV Package, 5-Pin SOT-23 (Top View) IN+ VCC– IN– VCC+ OUT Not to Scale Figure 4-2. TL081H: DCK Package, 5-Pin SC70 (Top View) 1NC 8 NC 2IN– 7 VCC+ 3IN+ 6 OUT 4VCC– 5 NC Not to scale Figure 4-3. TL081x: D Package, 8-Pin SOIC, P Package, 8-Pin PDIP (Top View) Table 4-1. Pin Functions: TL081x PIN TYPE(1) DESCRIPTION NAME NO. D DBV DCK P NC 1 — — 1 — Do not connect IN– 2 4 3 2 I Inverting input IN+ 3 3 1 3 I Non inverting input VCC– 4 2 2 4 — Power supply NC 5 — — 5 — Do not connect OUT 6 1 4 6 O Output VCC+ 7 5 5 7 — Power supply NC 8 — — 8 — Do not connect (1) I = input, O = output. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

2IN± 7 VCC+ 3IN+ 6 OUT 4VCC± 5 OFFSET N2 Not to scale Figure 4-4. TL081C PS Package, 8-Pin SO (Top View) Table 4-2. Pin Functions: TL081C PIN TYPE(1) DESCRIPTION NAME NO. OFFSET N1 1 — Input offset adjustment IN– 2 I Inverting input IN+ 3 I Non inverting input VCC– 4 — Power supply OFFSET N2 5 — Input offset adjustment OUT 6 O Output VCC+ 7 — Power supply NC 8 — Do not connect (1) I = input, O = output. TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

21IN± 7 2OUT 31IN+ 6 2IN ± 4VCC± 5 2IN+ Not to scale Figure 4-5. TL082x D, DDF, DGK, JG, P, PS, and PW Packages, 8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP (Top View) Table 4-3. Pin Functions: TL082x PIN TYPE(1) DESCRIPTION NAME NO. 1OUT 1 O Output 1IN– 2 I Inverting input 1IN+ 3 I Non inverting input VCC– 4 — Power supply 2IN+ 5 I Non inverting input 2IN– 6 I Inverting input 2OUT 7 O Output VCC+ 8 — Power supply (1) I = input, O = output. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

51IN± 6NC 71IN+ 8NC 9NC 10VCC± 11NC 122IN+ 13NC 14 NC 15 2IN ± 16 NC 17 2OUT 18 NC 19 NC

20 VCC+

Figure 4-6. TL082 FK Package, 20-Pin LCCC (Top View) Table 4-4. Pin Functions: TL082x PIN TYPE(1) DESCRIPTION NAME NO. 1IN– 5 I Inverting input 1IN+ 7 I Non inverting input 1OUT 2 O Output 2IN– 15 I Inverting input 2IN+ 12 I Non inverting input 2OUT 17 O Output NC 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 — Do not connect VCC– 10 — Power supply VCC+ 20 — Power supply (1) I = input, O = output. TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

21IN± 13 4IN ± 31IN+ 12 4IN+ 4VCC+ 11 VCC ± 52IN+ 10 3IN+ 62IN± 9 3IN ± 72OUT 8 3OUT Not to scale Figure 4-7. TL084x D, N, NS, PW, J, and DYY Package, 14-Pin SOIC, PDIP, SO, TSSOP, CDIP, and SOT-23 (14) (Top View) Table 4-5. Pin Functions: TL084x PIN TYPE(1) DESCRIPTION NAME NO. 1IN– 2 I Inverting input 1IN+ 3 I Non inverting input 1OUT 1 O Output 2IN– 6 I Inverting input 2IN+ 5 I Non inverting input 2OUT 7 O Output 3IN– 9 I Inverting input 3IN+ 10 I Non inverting input 3OUT 8 O Output 4IN– 13 I Inverting input 4IN+ 12 I Non inverting input 4OUT 14 O Output VCC– 11 — Power supply VCC+ 4 — Power supply (1) I = input, O = output. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

92IN± 102OUT 11NC 123OUT 133IN± 14 3IN+ 15 NC

16 VCC ±

19 4IN ± 20 4OUT 1 NC 2 1OUT 3 1IN ± Not to scale Figure 4-8. TL084 FK Package, 20-Pin LCCC (Top View) Table 4-6. Pin Functions: TL084x PIN TYPE(1) DESCRIPTION NAME NO. 1IN– 3 I Inverting input 1IN+ 4 I Non inverting input 1OUT 2 O Output 2IN– 9 I Inverting input 2IN+ 8 I Non inverting input 2OUT 10 O Output 3IN– 13 I Inverting input 3IN+ 14 I Non inverting input 3OUT 12 O Output 4IN– 19 I Inverting input 4IN+ 18 I Noninverting input 4OUT 20 O Output 17 — Do not connect VCC– 16 — Power supply VCC+ 6 — Power supply (1) I = input, O = output. TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VS = (V+) – (V–) All NS and PS packages; All TL08xM devices –0.3 36 V All other devices 0 42 V Signal input pins Common-mode voltage (3) All NS and PS packages; All TL08xM devices (V–) – 0.3 (V–) + 36 V All other devices (V–) – 0.5 (V+) + 0.5 V Differential voltage (3) All NS and PS packages; All TL08xM devices All other devices VS + 0.2 V Current (3) All NS and PS packages; All TL07xM devices 50 mA All other devices –10 10 mA Output short-circuit (2) Continuous Operating ambient temperature, TA –55 150 °C Junction temperature, TJ 150 °C Case temperature for 60 seconds - FK package 260 °C Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Short-circuit to ground, one amplifier per package. (3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. (4) Differential voltage only limited by input voltage.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage, (VCC+) – (VCC– ) All NS and PS packages; All TL08xM devices(1) 10 30 V All other devices 4.5 40 V VI Input voltage range All NS and PS packages; All TL08xM devices (VCC–) + 2 (VCC+) + 0.1 V All other devices (VCC– ) + 4 (VCC+) + 0.1 V TA Specified temperature TL08xM –55 125 °C TL08xH –40 125 °C TL08xI –40 85 °C TL08xC 0 70 °C (1) V+ and V– are not required to be of equal magnitude, provided that the total VS (V+ – V–) is between 10 V and 30 V. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

5.4 Thermal Information for Single Channel

THERMAL METRIC (1) TL081xx UNITD (SOIC) DCK (SC70) DBV (SOT-23) P (PDIP) PS (SO)

8 PINS 5 PINS 5 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 158.8 217.5 212.2 85 95 °C/W RθJC(top) Junction-to-case (top) thermal resistance 98.6 113.1 111.1 – – °C/W RθJB Junction-to-board thermal resistance 102.3 63.8 79.4 – – °C/W ψJT Junction-to-top characterization parameter 45.8 34.8 51.8 – – °C/W ψJB Junction-to-board characterization parameter 101.5 63.5 79.0 – – °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metric application report.

5.5 Thermal Information for Dual Channel

THERMAL METRIC (1) TL082xx UNITD (SOIC) DDF (SOT-23) FK (LCCC) JG (CDIP) P (PDIP) PS (SO) PW (TSSOP) U (CFP)

8 PINS 8 PINS 20 PINS 8 PINS 8 PINS 8 PINS 8 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 147.8 181.5 – – 85 95 200.3 169.8 °C/W RθJC(top) Junction-to-case (top) RθJB Junction-to-board thermal resistance 91.4 98.2 – – – – 131.0 176.2 °C/W ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A – – – – N/A 5.4 °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metric application report. TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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5.6 Thermal Information for Quad Channel

THERMAL METRIC (1) TL084xx UNITD (SOIC) DYY (SOT-23) FK (TSSOP) J (TSSOP) N (TSSOP) NS (TSSOP) PW (TSSOP) W (TSSOP)

14 PINS 14 PINS 20 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 114.2 153.2 – – 80 76 – 128.8 °C/W Rθ JC(top) Junction-to-case (top) thermal RθJB Junction-to-board thermal resistance 70.2 65.4 – – – – – 127.6 °C/W ψJT Junction-to-top characterization parameter 28.8 9.5 – – – – – 29 °C/W ψJB Junction-to-board characterization parameter 69.8 65.0 – – – – – 106.1 °C/W Rθ JC(bot) Junction-to-case (bottom) thermal resistance N/A N/A – – – – – 0.5 °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metric application report. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

5.7 Electrical Characteristics: TL08xH

For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and Vout = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±1 ±4 mV TA = –40°C to +125°C ±5 dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±2 µV/℃ PSRR Input offset voltage versus power supply VS = 5V to 40V, VCM = VS/2 TA = –40°C to +125°C ±1 ±10 μV/V Channel separation f = 0 Hz 10 µV/V INPUT BIAS CURRENT IB Input bias current ±1 ±120 pA DCK and DBV packages ±1 ±300 pA TA = –40°C to +125°C (1) ±5 nA IOS Input offset current ±0.5 ±120 pA DCK and DBV packages ±0.5 ±250 pA TA = –40°C to +125°C (1) ±5 nA NOISE EN Input voltage noise f = 0.1 Hz to 10 Hz 9.2 μVPP 1.4 µVRMS eN Input voltage noise density f = 1 kHz 37 nV/√Hz f = 10 kHz 21 iN Input current noise f = 1 kHz 80 fA/√Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range (VCC–) + 1.5 (VCC+) V CMRR Common-mode rejection ratio VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) – 1.5 V 100 105 dB TA = –40°C to +125°C 95 dB VS = 40 V, (VCC–) + 2.5 V < VCM < (VCC+) 90 105 dB TA = –40°C to +125°C 80 dB INPUT CAPACITANCE ZID Differential 100 || 2 MΩ || pF ZICM Common-mode 6 || 1 TΩ || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2, (VCC–) + 0.3 V < VO < (VCC+) – 0.3 V TA = –40°C to +125°C 118 125 dB AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2, RL = 2 kΩ, (VCC–) + 1.2 V < VO < (VCC+) – 1.2 V TA = –40°C to +125°C 115 120 dB FREQUENCY RESPONSE GBW Gain-bandwidth product 5.25 MHz SR Slew rate VS = 40 V, G = +1, CL = 20 pF 20 V/μs tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.63 μs To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.56 To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.91 To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.48 Phase margin G = +1, RL = 10kΩ, CL = 20 pF 56 ° Overload recovery time VIN × gain > VS 300 ns THD+N Total harmonic distortion + noise VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz 0.00012 % EMIRR EMI rejection ratio f = 1 GHz 53 dB TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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5.7 Electrical Characteristics: TL08xH (continued)

For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and Vout = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Voltage output swing from rail Positive rail headroom VS = 40 V, RL = 10 kΩ 115 210 mV VS = 40 V, RL = 2 kΩ 520 965 Negative rail headroom VS = 40 V, RL = 10 kΩ 105 215 VS = 40 V, RL = 2 kΩ 500 1030 ISC Short-circuit current ±26 mA CLOAD Capacitive load drive 300 pF ZO Open-loop output impedance f = 1 MHz, IO = 0 A 125 Ω POWER SUPPLY IQ Quiescent current per amplifier IO = 0 A 937.5 1125 µA IO = 0 A, (TL081H) 960 1156 IO = 0 A TA = –40°C to +125°C 1130 IO = 0 A, (TL082H) 1143 IO = 0 A, (TL071H) 1160 Turn-On time At TA = 25°C, VS = 40V, VS ramp rate > 0.3V/µs 60 μs (1) Max IB and Ios data is specified based on characterization results. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

5.8 Electrical Characteristics (DC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM

For VS = (VCC+) – (VCC–) = ±15 V at TA = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT VOS Input offset voltage VO = 0 V RS = 50 Ω TL08xC 3 10 mV TA = Full range 13 TL08xAC 3 6 TA = Full range 7.5 TL08xBC 2 3 TA = Full range 5 TL08xI 3 6 TA = Full range 8 TL081M, TL082M 3 6 TA = Full range 9 TL084M 3 9 TA = Full range 15 dVOS/dT Input offset voltage drift VO = 0 V, RS = 50 Ω TA = Full range ±18 µV/℃ IOS Input offset current VO = 0 V TL08xC 5 100 pA TA = Full range 10 nA TL08xAC, TL08xBC, TL08xI 5 100 pA TA = Full range 2 nA TL08xM 5 100 pA TA = Full range 20 nA IB Input bias current VO = 0 V TL08xC, TL08xAC, TL08xBC, TL08xI 65 200 pA TA = Full range 7 nA TL081M, TL082M 65 200 pA TA = Full range 50 nA TL084M 65 200 pA TA = Full range 20 nA VCM Common-mode voltage range ±11 –12 to 15 V VOM Maximum peak output voltage swing RL = 10 kΩ ±12 ±13.5 VRL ≥ 10 kΩ TA = Full range ±12 RL ≥ 2 kΩ ±10 AOL Open-loop voltage gain VO = 0 V TL08xC 25 200 V/mV TA = Full range 15 TL08xAC, TL08xBC, TL08xI 50 200 TA = Full range 25 TL08xM 35 200 TA = Full range 15 GBW Gain-bandwidth product All NS and PS packages; All TL08xM devices 3 MHz All other devices 5.25 RID Common-mode input resistance 1 TΩ CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 V RS = 50 Ω TL08xC 70 100 dBTL08xAC, TL08xBC, TL08xI 75 100 TL08xM 80 86 PSRR Input offset voltage versus power supply VS = ±9 V to ± 18 V VO = 0 V RS = 50 Ω TL08xC 70 100 dBTL08xAC, TL08xBC, TL08xI 80 100 TL08xM 80 86 TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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5.8 Electrical Characteristics (DC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM (continued)

For VS = (VCC+) – (VCC–) = ±15 V at TA = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT IQ Quiescent current per amplifier VO = 0 V; no load 1.4 2.5 mA Channel separation f = 0 Hz 1 µV/V (1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) Full range is TA = 0°C to 70°C for the TL07xC, TL07xAC, and TL07xBC; TA = –40°C to 85°C for the TL07xI; and TA = –55°C to 125°C for the TL07xM. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

5.9 Electrical Characteristics (AC): TL08xC, TL08xAC, TL08xBC, TL08xI, TL08xM

For VS = (VCC+) – (VCC–) = ±15 V at TA = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate VI = 10 V, CL = 100 pF, RL = 2 kΩ TL08xM 5 20 V/μs TL08xC, TL08xAC, TL08xBC, TL08xI 8 20 V/μs tS Settling time VI = 20 V, CL = 100 pF, RL = 2 kΩ 0.1 μs 20% eN Input voltage noise density All PS and NS packages; All TL08xM devices RS = 20 Ω, f = 1 kHz 18 nV/√Hz All other devices f = 1 kHz 37 nV/√Hz f = 10 kHz 21 EN Input voltage noise All PS and NS packages; All TL08xM devices RS = 20 Ω, f = 10 Hz to 10 kHz 4 μVRMS All other devices f = 0.1 Hz to 10 Hz 1.4 µVRMS iN Input current noise RS = 20 Ω, f = 1 kHz 10 fA/√Hz Phase margin TL08xC, TL08xAC, TL08xBC, TL08xI G = +1, RL = 10kΩ, CL = 20 pF 56 ° Overload recovery time VIN × gain > VS 300 ns THD+N Total harmonic distortion + noise All PS and NS packages; All TL08xM devices VO = 6 VRMS, RL ≥ 2 kΩ, f = 1 kHz, G = +1, RS ≤ 1 kΩ 0.003 % All other devices VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz 0.00012 % EMIRR EMI rejection ratio TL08xC, TL08xAC, TL08xBC, TL08xI f = 1 GHz 53 dB ZO Open-loop output impedance TL07xC, TL07xAC, TL07xBC, TL07xI f = 1 MHz, IO = 0 A 125 Ω TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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5.10 Typical Characteristics: TL08xH

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted) TA = 25°C Figure 5-1. Offset Voltage Production Distribution Figure 5-2. Offset Voltage Drift Distribution VCM = VS / 2 Figure 5-3. Offset Voltage vs Temperature TA = 25°C Figure 5-4. Offset Voltage vs Common-Mode Voltage TA = 125°C Figure 5-5. Offset Voltage vs Common-Mode Voltage TA = –40°C Figure 5-6. Offset Voltage vs Common-Mode Voltage www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

5.10 Typical Characteristics: TL08xH (continued)

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted) Figure 5-7. Offset Voltage vs Power Supply Figure 5-8. Open-Loop Output Impedance vs Frequency Figure 5-9. Open-Loop Gain and Phase vs Frequency Figure 5-10. Closed-Loop Gain vs Frequency Figure 5-11. Input Bias Current vs Common-Mode Voltage Figure 5-12. Input Bias Current vs Temperature TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted) Figure 5-13. Output Voltage Swing vs Output Current (Sourcing) Figure 5-14. Output Voltage Swing vs Output Current (Sinking) T e m p e r a t u r e ( ° C ) Common-Mode Rejection Ratio (dB) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 1 5 1 1 7 . 5 1 2 0 1 2 2 . 5 1 2 5 1 2 7 . 5 1 3 0 1 3 2 . 5 1 3 5 V S = 4 0 V ; ( V C C – ) + 2 . 5 V < V C M < ( V C C + ) – 1 . 5 V V S = 4 0 V ; ( V C C – ) + 2 . 5 V < V C M < ( V C C + ) f = 0Hz Figure 5-15. CMRR vs Temperature (dB) f = 0Hz Figure 5-16. PSRR vs Temperature (dB) T i m e ( 1 s / d i v ) Voltage (1 µV/div) - 5 - 4 - 3 - 2 - 1 Figure 5-17. 0.1Hz to 10Hz Noise Figure 5-18. Input Voltage Noise Spectral Density vs Frequency www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted) VCM = VS / 2 Figure 5-19. Quiescent Current vs Supply Voltage Figure 5-20. Quiescent Current vs Temperature Figure 5-21. Open-Loop Voltage Gain vs Temperature (dB) Figure 5-22. Short-Circuit Current vs Temperature G = –1, 25mV output step Figure 5-23. Small-Signal Overshoot vs Capacitive Load G = 1, 10mV output step Figure 5-24. Small-Signal Overshoot vs Capacitive Load TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted) Figure 5-25. Phase Margin vs Capacitive Load VS = ±10V, VIN = VOUT Figure 5-26. No Phase Reversal G = –10 Figure 5-27. Positive Overload Recovery G = –10 Figure 5-28. Negative Overload Recovery CL = 20pF, G = 1, 10mV step response Figure 5-29. Small-Signal Step Response, Rising CL = 20pF, G = 1, 10mV step response Figure 5-30. Small-Signal Step Response, Falling www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

at TA = 25°C, VS = 40V ( ±20V), VCM = VS / 2, RLOAD = 10kΩ connected to VS / 2, and CL = 20pF (unless otherwise noted) CL = 20pF, G = 1 Figure 5-31. Large-Signal Step Response (Rising) CL = 20pF, G = 1 Figure 5-32. Large-Signal Step Response (Falling) CL = 20pF, G = 1 Figure 5-33. Large-Signal Step Response Figure 5-34. Maximum Output Voltage vs Frequency Figure 5-35. Channel Separation vs Frequency Figure 5-36. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

6 Parameter Measurement Information

+VI CL=100pF RL=2K Figure 6-1. Test Figure 1 OUT VI CL=100pFRL 10KΩ 1KΩ Figure 6-2. Test Figure 2 IN– OUT 100k C1 500pF Figure 6-3. Test Figure 3 IN– OUT 1.5k N2IN+ VCC– TL081 Figure 6-4. Test Figure 4 (for SO Package Only) www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

7 Detailed Description

7.1 Overview

The TL08xH family (TL081H, TL082H, and TL084H) is the next-generation family of the industry standard TL08x (TL081, TL082, and TL084) high-voltage general purpose amplifiers. These devices provide outstanding value for cost-sensitive applications requiring high slew rate with high voltage signals, such as motor drive and inverter systems. A robust MUX-friendly input stage enhances flexibility in design, with common-mode voltage range extending to the positive rail as well as improved settling time in multi-channel applications. Low offset voltage (1mV, typ) and low offset voltage drift (2µV/°C) allows the TL08xH family to be used in rugged applications requiring precision current and voltage sensing. High voltage operation (up to 40V) and high slew rate (20V/µs) make the TL08xH family a premier choice for high-voltage applications with fast transients.

7.2 Functional Block Diagram

VIN– VCC– (Ground) VBIAS2 VBIAS1 Class AB Control Circuitry VO Reference Current

7.3 Feature Description

7.3.1 Total Harmonic Distortion

Electronic components within a circuit generate harmonic distortion in the audio signal. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices have a very low THD of 0.003% meaning that the TL08x devices generate little harmonic distortion when used in audio signal applications.

7.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier changes the output when there is a change on the input. These devices have a 20V/μs slew rate.

7.4 Device Functional Modes

These devices are powered on when the supply is connected. This device operates as a single-supply operational amplifier or dual-supply amplifier depending on the application. TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

8 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TL08x series of operational amplifiers can be used in countless applications. The few applications in this section show principles used in all applications of these parts.

8.2 Typical Applications

8.2.1 Inverting Amplifier Application

A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage on the input, and makes positive voltage as a negative voltage of the same magnitude. In the same manner, amplifier also makes negative voltages positive. Vsup+ VOUT RF VIN RI Vsup- Figure 8-1. Schematic for Inverting Amplifier Application

8.2.1.1 Design Requirements

Choose the supply voltage higher than input and output ranges. For instance, this application scales a signal of ±0.5V to ±1.8V. Setting the supply at ±12V is sufficient to accommodate this application.

8.2.1.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier: A V = VOUT VIN (1) A V = 1.8 − 0.5 = − 3.6 (2) After the desired gain is determined, choose a value for RI or RF. Choosing a value in the k Ω range is desirable because the amplifier circuit uses currents in the milliampere range. This example chooses 10k Ω for RI, which means that 36kΩ is used for RF. RF value is determined by Equation 3. A V = – RF RI (3) www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

8.2.1.3 Application Curve

-1.5 -0.5 0.5 1.5 0 0.5 1 1.5 2 Volts Time (ms) VIN VOUT Figure 8-2. Input and Output Voltages of the Inverting Amplifier

8.3 Power Supply Recommendations

Supply voltages larger than 36V for a single-supply or outside the range of ±18V for a dual-supply can permanently damage the device (see Section 5.1). Place 0.1μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, see Section 8.4.

8.4 Layout

8.4.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCB are typically devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Keep digital and analog grounds physically separate, and pay attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If not possible to keep them separate, cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 8.4.2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring significantly helps reduce leakage currents from nearby traces that are at different potentials. TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

8.4.2 Layout Examples

Run the input traces as far away from the supply lines as possible Only needed for dual- supply operation Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor (or GND for single supply) Ground (GND) plane on another layerVOUT Figure 8-3. Operational Amplifier Board Layout for Non-inverting Configuration VIN VOUT RF RIN RG Figure 8-4. Operational Amplifier Schematic for Non-inverting Configuration www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

9 Device and Documentation Support

9.1 Device Support

9.1.1 Device Nomenclature

Table 9-1. Device Nomenclature PART NUMBER DEFINITION TL08xyzzzzzz x is the channel count If y = H, the die is manufactured on the latest flow (CSO: RFB). Section 5.7 and Section 5.10 describe the performance of the new die. If y ≠ H and y ≠ M, the die is manufactured on the legacy flow (CSO: SFAB) or the latest flow (CSO: RFB). Section 5.8 and Section 5.9 describe the performance of the original die. If y = M, the device is specified for the extended temperature range of –55°C to +125°C. The die is manufactured on the legacy flow (CSO:SFAB). The letters and numbers represented by z are grade-out and package options described in Section 5.8 and the Package Option Addendum at the end of this data sheet.

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (June 2024) to Revision O (September 2025) Page TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

• Deleted plots for THD+N Ratio vs Frequency, THD+N vs Output Amplitude, and CMRR and PSRR vs Changes from Revision M (December 2021) to Revision N (June 2024) Page
• Changed Absolute Maximum Ratings, ESD Ratings, Recommended Operating Conditions, and Thermal
• Changed Electrical Characteristics tables by merging TL08xC, TL08xAC, TL08xBC, TL08xI, and TL08xM
• Increased gain bandwidth of all non-NS/non-PS packages and non-TL08xM devices from 3 MHz to 5.25
• Merged TL08xC, TL08xAC, TL08xBC, TL08xI, and TL08xM Switching Characteristics tables and renamed to
• Changed input voltage noise density at 1 kHz for all non-PS/non-NS packages and all non-TL08xM devices Changes from Revision L (July 2021) to Revision M (December 2021) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TL081, TL081A, TL081B, TL081H TL082, TL082A, TL082B, TL082H TL084, TL084A, TL084B, TL084H SLOS081O – FEBRUARY 1977 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B TL084H

www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 5962-9851501Q2A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962- 9851501Q2A TL082MFKB 5962-9851501QPA Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 9851501QPA TL082M 5962-9851503Q2A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962- 9851503Q2A TL084 MFKB 5962-9851503QCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB TL081ACD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 081AC TL081ACDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 081AC TL081ACDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 081AC TL081ACP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL081ACP TL081ACP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL081ACP TL081BCD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 081BC TL081BCDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 081BC TL081BCDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 081BC TL081BCP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL081BCP TL081BCP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL081BCP TL081CD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 TL081C TL081CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C TL081CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C TL081CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL081CP TL081CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL081CP TL081CPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70 TL081CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T081 TL081CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T081 TL081HIDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 T81V Addendum-Page 1

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL081HIDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T81V TL081HIDCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1IP TL081HIDCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1IP TL081HIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL081D TL081HIDR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL081D TL081HIDR.B Active Production SOIC (D) | 8 3000 | LARGE T&R - Call TI Call TI -40 to 125 TL081ID Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 TL081I TL081IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I TL081IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I TL081IP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL081IP TL081IP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL081IP TL082ACD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 082AC TL082ACDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 082AC TL082ACDRE4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI 0 to 70 TL082ACP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL082ACP TL082ACP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL082ACP TL082ACPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082A TL082ACPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082A TL082BCD Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 082BC TL082BCDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 082BC TL082BCP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL082BCP TL082BCP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL082BCP TL082BCPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI 0 to 70 TL082CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C TL082CDRE4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI 0 to 70 TL082CDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI 0 to 70 Addendum-Page 2

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL082CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL082CP TL082CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL082CP TL082CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPSRG4 Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T082 TL082CPWRG4 Active Production TSSOP (PW) | 8 2000 | LARGE T&R - Call TI Call TI 0 to 70 TL082HIDDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 082F TL082HIDDFR.A Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 082F TL082HIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL082D TL082HIDR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL082D TL082HIPWR Active Production TSSOP (PW) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 082HPW TL082HIPWR.A Active Production TSSOP (PW) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 082HPW TL082IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I TL082IDRE4 Active Production SOIC (D) | 8 2500 | LARGE T&R - Call TI Call TI -40 to 85 TL082IP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL082IP TL082IP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL082IP TL082IPE4 Active Production PDIP (P) | 8 50 | TUBE - Call TI Call TI -40 to 85 TL082IPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z082 TL082IPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 Z082 TL082MFKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962- 9851501Q2A TL082MFKB TL082MFKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962- 9851501Q2A TL082MFKB TL082MJG Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL082MJG TL082MJG.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL082MJG TL082MJGB Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 9851501QPA TL082M Addendum-Page 3

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL082MJGB.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 9851501QPA TL082M TL084ACDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC TL084ACN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL084ACN TL084ACN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL084ACN TL084ACNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084A TL084ACNSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084A TL084BCDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI 0 to 70 TL084BCDR1G4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCDR1G4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC TL084BCDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI 0 to 70 TL084BCN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL084BCN TL084BCN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL084BCN TL084BCNE4 Active Production PDIP (N) | 14 25 | TUBE - Call TI Call TI 0 to 70 TL084CDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C TL084CDRG4 Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 TL084C TL084CN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL084CN TL084CN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL084CN TL084CNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084 TL084CNSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 TL084 TL084CPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM 0 to 70 T084 TL084CPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T084 TL084CPWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T084 TL084HIDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084HID TL084HIDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084HID TL084HIDYYR Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T084HDYY Addendum-Page 4

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL084HIDYYR.A Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T084HDYY TL084HIDYYRG4 Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T084HDYY TL084HIDYYRG4.A Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T084HDYY TL084HIPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 TL084PW TL084HIPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084PW TL084IDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I TL084IDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I TL084IDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 125 TL084IDR1G4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084I TL084IDR1G4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084I TL084IDRE4 Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 85 TL084IDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R - Call TI Call TI -40 to 85 TL084IN Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL084IN TL084IN.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 TL084IN TL084ING4 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 125 TL084IN TL084ING4.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 125 TL084IN TL084MFK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL084MFK TL084MFK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL084MFK TL084MFKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962- 9851503Q2A TL084 MFKB TL084MFKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962- 9851503Q2A TL084 MFKB TL084MJ Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL084MJ TL084MJ.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 TL084MJ TL084MJB Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB Addendum-Page 5

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL084MJB.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-9851503QC A TL084MJB TL084QDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q TL084QDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q TL084QDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q TL084QDRG4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL082, TL082M, TL084, TL084M : Addendum-Page 6

www.ti.com 31-Oct-2025

• Catalog : TL082, TL084
• Automotive : TL082-Q1, TL082-Q1
• Military : TL082M , TL084M NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications Addendum-Page 7

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TL082HIDDFR SOT-23- THIN TL084HIDYYR SOT-23- THIN TL084HIDYYRG4 SOT-23- THIN Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL081ACDR SOIC D 8 2500 340.5 338.1 20.6 TL081BCDR SOIC D 8 2500 353.0 353.0 32.0 TL081CDR SOIC D 8 2500 340.5 338.1 20.6 TL081CPSR SO PS 8 2000 353.0 353.0 32.0 TL081HIDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TL081HIDCKR SC70 DCK 5 3000 190.0 190.0 30.0 TL081HIDR SOIC D 8 3000 353.0 353.0 32.0 TL081IDR SOIC D 8 2500 353.0 353.0 32.0 TL082ACDR SOIC D 8 2500 353.0 353.0 32.0 TL082ACDR SOIC D 8 2500 340.5 338.1 20.6 TL082ACPSR SO PS 8 2000 353.0 353.0 32.0 TL082BCDR SOIC D 8 2500 353.0 353.0 32.0 TL082BCDRG4 SOIC D 8 2500 353.0 353.0 32.0 TL082CDR SOIC D 8 2500 353.0 353.0 32.0 TL082CDR SOIC D 8 2500 353.0 353.0 32.0 TL082CDR SOIC D 8 2500 353.0 353.0 32.0 TL082CPSR SO PS 8 2000 353.0 353.0 32.0 TL082CPWR TSSOP PW 8 2000 353.0 353.0 32.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL082HIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TL082HIDR SOIC D 8 3000 353.0 353.0 32.0 TL082HIPWR TSSOP PW 8 3000 353.0 353.0 32.0 TL082IDR SOIC D 8 2500 353.0 353.0 32.0 TL082IDR SOIC D 8 2500 353.0 353.0 32.0 TL082IPWR TSSOP PW 8 2000 353.0 353.0 32.0 TL084ACDR SOIC D 14 2500 353.0 353.0 32.0 TL084ACNSR SOP NS 14 2000 353.0 353.0 32.0 TL084BCDR SOIC D 14 2500 353.0 353.0 32.0 TL084BCDR SOIC D 14 2500 353.0 353.0 32.0 TL084BCDR1G4 SOIC D 14 2500 353.0 353.0 32.0 TL084CDR SOIC D 14 2500 353.0 353.0 32.0 TL084CNSR SOP NS 14 2000 353.0 353.0 32.0 TL084CPWR TSSOP PW 14 2000 356.0 356.0 35.0 TL084CPWRG4 TSSOP PW 14 2000 356.0 356.0 35.0 TL084CPWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 TL084HIDR SOIC D 14 2500 353.0 353.0 32.0 TL084HIDYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 TL084HIDYYRG4 SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 TL084HIPWR TSSOP PW 14 2000 356.0 356.0 35.0 TL084HIPWR TSSOP PW 14 2000 356.0 356.0 35.0 TL084IDR SOIC D 14 2500 353.0 353.0 32.0 TL084IDR SOIC D 14 2500 353.0 353.0 32.0 TL084IDR1G4 SOIC D 14 2500 353.0 353.0 32.0 TL084QDR SOIC D 14 2500 353.0 353.0 32.0 TL084QDRG4 SOIC D 14 2500 353.0 353.0 32.0 Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 5962-9851501Q2A FK LCCC 20 55 506.98 12.06 2030 NA 5962-9851503Q2A FK LCCC 20 55 506.98 12.06 2030 NA TL081ACP P PDIP 8 50 506 13.97 11230 4.32 TL081ACP.A P PDIP 8 50 506 13.97 11230 4.32 TL081BCP P PDIP 8 50 506 13.97 11230 4.32 TL081BCP.A P PDIP 8 50 506 13.97 11230 4.32 TL081CP P PDIP 8 50 506 13.97 11230 4.32 TL081CP.A P PDIP 8 50 506 13.97 11230 4.32 TL081IP P PDIP 8 50 506 13.97 11230 4.32 TL081IP.A P PDIP 8 50 506 13.97 11230 4.32 TL082ACP P PDIP 8 50 506 13.97 11230 4.32 TL082ACP.A P PDIP 8 50 506 13.97 11230 4.32 TL082BCP P PDIP 8 50 506 13.97 11230 4.32 TL082BCP.A P PDIP 8 50 506 13.97 11230 4.32 TL082CP P PDIP 8 50 506 13.97 11230 4.32 TL082CP.A P PDIP 8 50 506 13.97 11230 4.32 TL082IP P PDIP 8 50 506 13.97 11230 4.32 TL082IP P PDIP 8 50 506 13.97 11230 4.32 TL082IP.A P PDIP 8 50 506 13.97 11230 4.32 TL082IP.A P PDIP 8 50 506 13.97 11230 4.32 TL082MFKB FK LCCC 20 55 506.98 12.06 2030 NA TL082MFKB.A FK LCCC 20 55 506.98 12.06 2030 NA TL084ACN N PDIP 14 25 506 13.97 11230 4.32 TL084ACN N PDIP 14 25 506 13.97 11230 4.32 TL084ACN.A N PDIP 14 25 506 13.97 11230 4.32 TL084ACN.A N PDIP 14 25 506 13.97 11230 4.32 TL084BCN N PDIP 14 25 506 13.97 11230 4.32 TL084BCN N PDIP 14 25 506 13.97 11230 4.32 TL084BCN.A N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL084BCN.A N PDIP 14 25 506 13.97 11230 4.32 TL084CN N PDIP 14 25 506 13.97 11230 4.32 TL084CN.A N PDIP 14 25 506 13.97 11230 4.32 TL084IN N PDIP 14 25 506 13.97 11230 4.32 TL084IN.A N PDIP 14 25 506 13.97 11230 4.32 TL084ING4 N PDIP 14 25 506 13.97 11230 4.32 TL084ING4.A N PDIP 14 25 506 13.97 11230 4.32 TL084MFK FK LCCC 20 55 506.98 12.06 2030 NA TL084MFK.A FK LCCC 20 55 506.98 12.06 2030 NA TL084MFKB FK LCCC 20 55 506.98 12.06 2030 NA TL084MFKB.A FK LCCC 20 55 506.98 12.06 2030 NA Pack Materials-Page 6

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.15 2.4 1.8 2X 0.65 1.3

1.1 MAX

0.1

0.0 TYP

5X 0.33 0.15 NOTE 5

0.1 C A B

0.46

0.26 TYP

0 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/G 11/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6)

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE 10.16 9.00 7.11 6.22 1.60 0.38 6X 2.54 8X 0.58 0.38 4X 1.65 1.14 0.51 MIN 3.30 MIN

5.08 MAX

7.87 7.37 0.36

0.20 TYP

4X (0.94) CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package can be hermetically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification. 5. Falls within MIL STD 1835 GDIP1-T8 SEATING PLANE

0.25 C A B

A B C

www.ti.com EXAMPLE BOARD LAYOUT (7.62) 6X (2.54) 8X ( 1) THRU 7X ( 1.6) (1.6) (R0.05) TYP CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 LAND PATTERN EXAMPLE NON SOLDER MASK DEFINED SCALE: 9X SOLDER MASK OPENING TYP METAL TYP SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 0.22 0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11 C SEATING PLANE 0.2 0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4) 14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

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