TL081

TL081 NSC | Alldatasheet

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Y Internally trimmed offset voltage 15 mV Y Low input bias current 50 pA Y Low input noise voltage 25 nV/ 0Hz Y Low input noise current 0.01 pA/ 0Hz Y Wide gain bandwidth 4 MHz Y High slew rate 13 V/ ms Y Low supply current 1.8 mA Y High input impedance 10 12X Y Low total harmonic distortion A V e 10, k0.02% RL e 10k, V O e 20 Vp-p, BW e 20 Hz b20 kHz Y Low 1/f noise corner 50 Hz Y Fast settling time to 0.01% 2 ms Typical Connection TL/H/8358–1 Connection Diagram Simplified Schematic TL/H/8358–2 Dual-In-Line Package TL/H/8358–4 Order Number TL081CP See NS Package Number N08E BI-FET II TM is a trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage g18V Power Dissipation (Notes 1 and 6) 670 mW Operating Temperature Range 0 §Ct o a70§C Tj(MAX) 115§C Differential Input Voltage g30V Input Voltage Range (Note 2) g15V Output Short Circuit Duration Continuous Storage Temperature Range b65§Ct o a150§C Lead Temp. (Soldering, 10 seconds) 260 §C ijA 120§C/W ESD rating to be determined. Symbol Parameter Conditions TL081C Units Min Typ Max VOS Input Offset Voltage R S e 10 k X,T A e 25§C 5 15 mV Over Temperature 20 mV DVOS/DT Average TC of Input Offset R S e 10 k X 10 mV/§CVoltage IOS Input Offset Current T j e 25§C, (Notes 3, 4) 25 100 pA Tj s 70§C4 n A IB Input Bias Current T j e 25§C, (Notes 3, 4) 50 200 pA Tj s 70§C8 n A RIN Input Resistance T j e 25§C1 0 12 X AVOL Large Signal Voltage Gain V S e g15V, T A e 25§C 25 100 V/mV VO e g10V, R L e 2k X Over Temperature 15 V/mV VO Output Voltage Swing V S e g15V, R L e 10 k X g12 g13.5 V VCM Input Common-Mode Voltage VS e g15V g11 a15 V Range b12 V CMRR Common-Mode Rejection Ratio R S s 10 k X 70 100 dB PSRR Supply Voltage Rejection Ratio (Note 5) 70 100 dB IS Supply Current 1.8 2.8 mA Symbol Parameter Conditions TL081C Units Min Typ Max SR Slew Rate V S e g15V, T A e 25§C1 3 V / ms GBW Gain Bandwidth Product V S e g15V, T A e 25§C 4 MHz en Equivalent Input Noise Voltage T A e 25§C, R S e 100X, 25 nV/ 0Hzf e 1000 Hz in Equivalent Input Noise Current T j e 25§C, f e 1000 Hz 0.01 pA/ 0Hz Note 1: For operating at elevated temperature, the device must be derated based on a thermal resistance of 120 §C/W junction to ambient for N package. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: These specifications apply for V S e g15V and 0 §C sTA s a70§C. V OS,I B and I OS are measured at V CM e 0. Note 4: The input bias currents are junction leakage currents which approximately double for every 10 §C increase in the junction temperature, T j. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, P D.T j e TA a ijA PD where ijA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 5: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice from VS e g5V to g15V. Note 6: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits.

Typical Performance Characteristics Input Bias Current Input Bias Current Supply Current TL/H/8358–5 Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Positive Current Limit Negative Current Limit Voltage Swing Output Voltage Swing Gain Bandwidth Bode Plot Slew Rate

Typical Performance Characteristics (Continued) Distortion vs Frequency Undistorted Output Voltage Swing Open Loop Frequency Response Common-Mode Rejection Ratio Power Supply Rejection Ratio Equivalent Input Noise Voltage Open Loop Voltage Gain (V/V) Output Impedance Inverter Settling Time TL/H/8358–6

TL/H/8358–7 Small Signal Non-Inverting TL/H/8358–13 Large Signal Inverting TL/H/8358–14 Large Signal Non-Inverting TL/H/8358–15 Current Limit (R L e 100X) TL/H/8358–16 Application Hints The TL081 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a de- stroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the

Application Hints (Continued) common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifier will operate with a common-mode input volt- age equal to the positive supply; however, the gain band- width and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. The TL081 is biased by a zener reference which allows nor- mal circuit operation on g4V power supplies. Supply volt- ages less than these may result in lower gain bandwidth and slew rate. The TL081 will driv ea2k X load resistance to g10V over the full temperature range of 0 §Ct o a70§C. If the amplifier is forced to drive heavier load currents, however, an in- crease in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power sup- ply for the integrated circuit never becomes reversed in po- larity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. Because these amplifiers are JFET rather than MOSFET input op amps they do not require special handling. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in or- der to ensure stability. For example, resistors from the out- put to an input should be placed with the body close to the input to minimize ‘‘pick-up’’ and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capaci- tance from the input of the device (usually the inverting in- put) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Detailed Schematic TL/H/8358–8

Supply Current Indicator/Limiter TL/H/8358–9 # VOUT switches high when R SIS l VD Hi-ZIN Inverting Amplifier TL/H/8358–10 Parasitic input capacitance C1 j (3 pF for TL081 plus any additional layout capacitance) interacts with feedback elements and creates un- desirable high frequency pole. To compensate, add C2 such that: R2C2 j R1C1. Ultra-Low (or High) Duty Cycle Pulse Generator TL/H/8358–11 # tOUTPUT HIGH & R1C fin 4.8 b 2VS 4.8 b VS # tOUTPUT LOW & R2C fin 2VS b 7.8 VS b 7.8 where V S e Va a lVbl *low leakage capacitor Long Time Integrator TL/H/8358–12 * Low leakage capacitor # 50k pot used for less sensitive V OS adjust

TL081 Wide Bandwidth JFET Input Operational Amplifier Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number TL081CP LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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