TL070_06 TI | Alldatasheet
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JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Low Power Consumption /C0068 Wide Common-Mode and Differential Voltage Ranges /C0068 Low Input-Bias and Offset Currents /C0068 Output Short-Circuit Protection /C0068 Low Total Harmonic Distortion. . . 0.003% Typ /C0068 Low Noise ...Vn = 18 nV/√Hz Typ at f = 1 kHz /C0068 High Input Impedance. . . JFET Input Stage /C0068 Common-Mode Input Voltage Range Includes VCC+ /C0068 Latch-Up-Free Operation /C0068 High Slew Rate. . . 13 V/µs Typ
description
The JFET-input TL070 operational amplifier is designed as the lower-noise version of the TL080 amplifier with low input-bias and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL070 ideally suited for high-fidelity and audio-preamplifier applications. This amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip. The TL070I device is characterized for operation from –40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA VIOmax AT 25°C SMALL OUTLINE (D) –40°C to 85°C 10 mV TL070ID logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. N1/COMP COMP IN+ IN– OFFSET N2 OUT Copyright 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. N1/COMP IN– IN+ VCC – COMP VCC+ OUT OFFSET N2 D PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC – 1080 Ω ÌÌÌ 1080 Ω N1/COMP IN– 64 Ω 128 Ω 64 Ω All component values shown are nominal. OUT COMPONENT COUNT † Transistors 13 Diodes 2 Resistors 10 epi-FET 1 JFET 2 † Includes all bias and trim circuitry
JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC –. 2. Differential voltages are at IN+ with respect to IN–. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 5. The package thermal impedance is calculated in accordance with JESD 51-7.
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Figure 5. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible.
JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Input bias current vs Free-air temperature 5 Maximum peak output voltage vs Frequency 6, 7, 8 Maximum peak output voltage vs Free-air temperature 9 Maximum peak output voltage vs Load resistance 10 Maximum peak output voltage vs Supply voltage 11 Large-signal differential voltage amplification vs Free-air temperature12 Differential voltage amplification vs Frequency with feed-forward compensation13 Large-signal differential voltage amplification and phase shift vs Frequency14 Normalized unity-gain bandwidth and phase shift vs Free-air temperature15 Common-mode rejection ratio vs Free-air temperature 16 Supply current vs Supply voltage 17 Supply current vs Free-air temperature 18 Total power dissipated vs Free-air temperature 19 Normalized slew rate vs Free-air temperature 20 Equivalent input noise voltage vs Frequency 21 Total harmonic distortion vs Frequency 22 Voltage-follower large-signal pulse response 23 Output voltage vs Elapsed time 24
JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS † Figure 9 TA – Free-Air Temperature – °C ±15 ±2.5 ±7.5 ±10 ±12.5 MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE ÌÌÌÌ ÌÌÌÌ R L = 2 kΩ – Maximum Peak Output Voltage – VVOM ÌÌÌÌÌ ÌÌÌÌÌ VCC ± = ±15 V See Figure 2 ÌÌÌÌÌ ÌÌÌÌÌ R L = 10 kΩ –75 –50 –25 0 25 50 75 100 125 Figure 10 R L – Load Resistance – kΩ ±15 ±2.5 ±7.5 ±10 ±12.5 MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE – Maximum Peak Output Voltage – VVOM ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ VCC ± = ±15 V TA = 25°C See Figure 2 0.1 0.2 0.4 0.7 1 2 4 7 10 Figure 11 |VCC ±| – Supply Voltage – V ±15 ±2.5 ±7.5 ±10 ±12.5 MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE – Maximum Peak Output Voltage – VVOM ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ R L = 10 kΩ TA = 25°C 0 2 4 6 8 10 12 14 16 Figure 12 TA – Free-Air Temperature – °C 1000 100 200 400 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION VS FREE-AIR TEMPERATURE – Large-Signal Differential Voltage Amplification – V/mVA VD ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ VCC ± = ±15 V VO = ±10 V R L = 2 kΩ –75 –50 –25 0 25 50 75 100 125 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. An 18-pF compensation capacitor is used.
JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS † Figure 17 |VCC ±| – Supply Voltage – V 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 SUPPLY CURRENT vs SUPPLY VOLTAGE – Supply Current – mAICC ± TA = 25°C No Signal No Load 02468 1 0 1 2 1 4 1 6 Figure 18 TA – Free-Air Temperature – °C 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 SUPPLY CURRENT vs FREE-AIR TEMPERATURE – Supply Current – mAICC ± VCC ± = ±15 V No Signal No Load –75 –50 –25 0 25 50 75 100 125 Figure 19 TA – Free-Air Temperature – °C 100 TOTAL POWER DISSIPATED vs FREE-AIR TEMPERATURE ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ VCC ± = ±15 V No Signal No Load – Total Power Dissipation – mWP D –75 –50 –25 0 25 50 75 100 125 Figure 20 0.85 Normalized Slew Rate TA – Free-Air Temperature – °C 1.15 0.90 0.95 1.05 1.10 NORMALIZED SLEW RATE vs FREE-AIR TEMPERATURE ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ VCC ± = ±15 V R L = 2 kΩ C L = 100 pF –75 –50 –25 0 25 50 75 100 125 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. An 18-pF compensation capacitor is used.
JFET-INPUT OPERATIONAL AMPLIFIER SLOS121B – NOVEMBER 1993 – REVISED MARCH 2001
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APPLICATION INFORMATION
75 µF 100 Ω 100 Ω Input Output 68 kΩ MIN 100 kΩ Treble MAX 0.003 µF 0.003 µF 3.3 kΩ 10 kΩ 0.03 µF MAX Bass 100 kΩ MIN 10 kΩ 10 kΩ 0.03 µF 47 µFGain 5 kΩ VCC – VCC+ 220 kΩ 0.00375 µF 0.01 µF 1 µF 27 kΩ 10 pF 47 kΩ 50 pF Balance TL070 VCC – VCC+ 10 pF TL070 Figure 25. IC Preamplifier
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TL070CD OBSOLETE SOIC D 8 TBD Call TI Call TI TL070CP OBSOLETE PDIP P 8 TBD Call TI Call TI TL070IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL070IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL070IP OBSOLETE PDIP P 8 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1
MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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