TL061CDT STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Features

■ Very low power consumption: 200 µA ■ Wide common-mode (up to VCC +) and differential voltage ranges ■ Low input bias and offset currents ■ Output short-circuit protection ■ High input impedance JFET input stage ■ Internal frequency compensation ■ Latch-up free operation ■ High slew rate: 3.5 V/µs

Description

The TL061 is a high-speed JFET input single operational amplifier, that incorporates well- matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The device features high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. N DIP8 (Plastic package) D SO-8 (Plastic micropackage) 1 - Offset null 1 2 - Inverting input 3 - Non-inverting input 4 - V CC 5 - Offset null 2 6 - Output 7 - V CC 8 - N.C. Pin connections (top view)

1 Schematic diagram

Figure 1. Schematic diagram Figure 2. Input offset voltage null circuit

2 Absolute maximum ratings and operating conditions

Table 1. Absolute maximum ratings

  1. All voltage values, except differential vo ltage, are with respect to the zero reference level (ground) of the supply voltages
  2. The magnitude of the input voltage must never exceed the magnit ude of the supply voltage or 15 volts, whichever is less.
  3. Differential voltages are the non-inverting input term inal with respect to the inverting input terminal.
  4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure

that the dissipation rating is not exceeded.

  1. Short-circuits can c ause excessive heating and destructive dissipation.
  2. Human body model: 100 pF discharged through a 1.5 k Ω resistor between two pins of the device, done for all couples of pin

combinations with other pins floating.

  1. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device

with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating.

  1. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to

Table 2. Operating conditions

3 Electrical characteristics

Table 3. V CC = ±15 V, Tamb = +25° C (unless otherwise specified)

6 V/mV

  1. The input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature

Table 3. V CC = ±15 V, Tamb = +25° C (unless otherwise specified) (continued) Table 4. V CC = ±15 V, Tamb = +25° C (unless otherwise specified)

  1. The input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature

Table 4. V CC = ±15 V, Tamb = +25° C (unless otherwise specified) (continued)

4 Parameter measurement information

Figure 18. Voltage follower Figure 19. Gain-of-10 inverting amplifier

5 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK ® is an ST trademark.

5.1 DIP8 package information

Figure 20. DIP8 package mechanical drawing Table 5. DIP8 package mechanical data

5.2 SO-8 package information

Figure 21. SO-8 package mechanical drawing Table 6. SO-8 package mechanical data

6 Ordering information

Table 7. Order codes

7 Revision history

Table 8. Document revision history 13-Nov-2001 1 Initial release. Added Table 2: Operating conditions. Chapter 5: Package information.