TL061ACDR

TL061_V01 TI | Alldatasheet

Document overview

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Technical content

IN− OUT OFFSET N1 Offset Null/Compensation TL061 Only OFFSET N2 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B SLOS078L –NOVEMBER 1978–REVISED MAY 2015 TL06xxLow-PowerJFET-InputOperationalAmplifiers

1 Features 2 Applications

1• Very Low Power Consumption • Tablets

• Typical Supply Current: 200 μA (Per Amplifier) • White goods
• Wide Common-Mode and Differential Voltage • Personal electronics Ranges • Computers
• Low Input Bias and Offset Currents

3 Description• Common-Mode Input Voltage Range

The JFET-input operational amplifiers of the TL06xIncludes VCC+ series are designed as low-power versions of the• Output Short-Circuit Protection TL08x series amplifiers. They feature high input• High Input Impedance: JFET-Input Stage impedance, wide bandwidth, high slew rate, and low

• Internal Frequency Compensation input offset and input bias currents. The TL06x series features the same terminal assignments as the TL07x• Latch-Up-Free Operation and TL08x series.• High Slew Rate: 3.5 V/μs Typical
• On Products Compliant to MIL-PRF-38535, Device Information(1) All Parameters Are Tested Unless Otherwise PART NUMBER PACKAGE BODY SIZE (NOM) Noted. On All Other Products, Production TL06xxD SOIC (14) 8.65 mm × 3.91 mm Processing Does Not Necessarily Include Testing TL06xxJ CDIP (14) 19.56 mm × 6.92 mm of All Parameters. TL06xxN PDIP (14) 19.30 mm × 6.35 mm TL06xxNS SO (14) 10.30 mm × 5.30 mm TL06xxPW TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Schematic Symbol An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B SLOS078L –NOVEMBER 1978–REVISED MAY 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (January 2014) to Revision L Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision J (September 2004) to Revision K Page

2 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

VCC− NC 3IN+ 1IN+ NC VCC+ NC 2IN+ 1IN− 1OUT NC 3OUT3IN− 4OUT 4IN− 2IN−2OUT NC 1 1 1OUT 1IN− 1IN+ VCC+ 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ VCC− 3IN+ 3IN− 3OUT 1OUT 1IN− 1IN+ VCC− VCC+ 2OUT 2IN− 2IN+ NC 2OUT NC 2IN− NC 3 2 1 20 19 9 10 1 1 12 13 NC 1IN− NC 1IN+ NC NC 1OUT NC 2IN+NC NC NC NC VCC− VCC+ OFFSET N1 IN− IN+ VCC− NC VCC+ OUT OFFSET N2 TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B www.ti.com SLOS078L –NOVEMBER 1978–REVISED MAY 2015

5 Pin Configuration and Functions

TL061x D, P, and PS Package TL062 FK Package8-Pin SOIC, PDIP, and SO 20-Pin LCCCTop View Top View TL062x D, JG, P, PS, and PW Package 8-Pin SOIC, CDIP, PDIP, SO, and TSSOP Top View 20-Pin LCCC Top View TL064x D, J, N, NS, PW, and W Package 14-Pin SOIC, CDIP, PDIP, SO, TSSOP and CFP Top View Pin Functions PIN TL061 TL062 TL064 TYPE DESCRIPTION NAME D, JG, P, D, J, N, NS,D, P, PS FK FKPS, PW PW, W 1IN– — 2 5 2 3 I Negative input 1IN+ — 3 7 3 4 I Positive input 1OUT — 1 2 1 2 O Output 2IN– — 6 15 6 9 I Negative input 2IN+ — 5 12 5 8 I Positive input 2OUT — 7 17 7 10 O Output 3IN– — — — 9 13 I Negative input 3IN+ — — — 10 14 I Positive input 3OUT — — — 8 12 O Output 4IN– — — — 13 19 I Negative input 4IN+ — — — 12 18 I Positive input 4OUT — — — 14 20 O Output IN– 2 — — — — I Negative input Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B SLOS078L –NOVEMBER 1978–REVISED MAY 2015 www.ti.com Pin Functions (continued) PIN TL061 TL062 TL064 TYPE DESCRIPTION NAME D, JG, P, D, J, N, NS,D, P, PS FK FKPS, PW PW, W IN+ 3 — — — — I Positive input NC 8 — — — Do not connect OFFSET N1 1 — — — — — Input offset adjustment OFFSET N2 5 — — — — — Input offset adjustment OUT 6 — — — — O Output VCC– 4 4 10 11 16 — Power supply VCC+ 7 8 20 4 6 — Power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC+ 18 Supply voltage(2) V VCC– –18 VID Differential input voltage(3) ±30 V VI Input voltage(2)(4) ±15 V Duration of output short circuit(5) Unlimited TJ Operating virtual junction temperature 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1.6 mm (1/16 inch) from J, JG, U, or W package 300 °Ccase for 60 seconds Lead temperature 1.6 mm (1/16 inch) from D, N, NS, P, PS, or PW package 260 °Ccase for 10 seconds Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−. (3) Differential voltages are at IN+, with respect to IN−. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.

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Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B www.ti.com SLOS078L –NOVEMBER 1978–REVISED MAY 2015

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- 2000C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC– Supply voltage –5 –15 V VCM Common-mode voltage VCC– + 4 VCC+ – 4 V TL06xM –55 125 TL06xQ –40 125 TA Ambient temperature °C TL06xI –40 85 TL06xC 0 70

6.4 Thermal Information - 8 Pins

THERMAL METRIC(1) D (SOIC) P (PDIP) PS (SO) PW (TSSOP) JG (CDIP) UNIT

8 PINS 8 PINS 8 PINS 8 PINS 8 PINS

RθJ Junction-to-ambient thermal 97 85 95 149 — °C/W A resistance(2)(3) RθJ Junction-to-case (top) thermal C(to — — — — 14.5 °C/Wresistance(4)(5) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.5 Thermal Information - 14 Pins

D (SOIC) N (PDIP) NS (SO) PS (SO) PW J (CDIP) W (CFP)THERMAL METRIC(1) UNIT(TSSOP)

14 PINS 14 PINS 14 PINS 8 PINS 14 PINS 14 PINS 14 PINS

RθJ Junction-to-ambient thermal 11386 80 76 95 — — °C/W A resistance(2)(3) RθJ Junction-to-case (top) thermal C(to — — — — — 15.05 14.65 °C/Wresistance(2)(3) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (3) The package thermal impedance is calculated in accordance with MIL-STD-883. Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B SLOS078L –NOVEMBER 1978–REVISED MAY 2015 www.ti.com

6.6 Thermal Information - 20 Pins

THERMAL METRIC(1) FK (LCCC) UNIT

20 PINS

RθJA Junction-to-ambient thermal resistance(2)(3) — °C/W RθJC(top) Junction-to-case (top) thermal resistance(4)(5) 5.61 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.7 Electrical Characteristics for TL06xC and TL06xxC

VCC± = ±15 V (unless otherwise noted) TL061AC, TL062AC,TL061C, TL062C, TL064C TL064ACPARAMETER TEST CONDITIONS(1) UNIT MIN TYP MAX MIN TYP MAX TA = 25°C 3 15 3 6 VIO Input offset voltage VO = 0, RS = 50 Ω mV TA = Full range 20 7.5 Temperature coefficientαVIO VO = 0, RS = 50 Ω, TA = Full range 10 10 μV/°Cof input offset voltage TA = 25°C 5 200 5 100 pA IIO Input offset current VO = 0 TA = Full range 5 3 nA TA = 25°C 30 400 30 200 pA IIB Input bias current(2) VO = 0 TA = Full range 10 7 nA –12 –12Common-mode inputVICR TA = 25°C ±11 to ±11 to Vvoltage range 15 15 RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5Maximum peak outputVOM Vvoltage swing RL ≥ 10 kΩ, TA = Full range ±10 ±10 TA = 25°C 3 6 4 6Large-signal differential VO = ±10 V,AVD V/mVvoltage amplification RL ≥ 2 kΩ TA = Full range 3 4 B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz ri Input resistance TA = 25°C Ω1012 1012 Common-mode VIC = VICRmin,CMRR 70 86 80 86 dBrejection ratio VO = 0, RS = 50 Ω, TA = 25°C Supply-voltage VCC = ±9 V to ±15 V,kSVR rejection ratio 70 95 80 95 dBVO = 0, RS = 50 Ω, TA = 25°C(ΔVCC±/ΔVIO) Total power dissipationPD VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW(each amplifier) Supply currentICC VO = 0, No load, TA = 25°C 200 250 200 250 µA(each amplifier) VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI. (2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

6 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B www.ti.com SLOS078L –NOVEMBER 1978–REVISED MAY 2015

6.8 Electrical Characteristics for TL06xxC and TL06xI

VCC± = ±15 V (unless otherwise noted) TL061BC, TL062BC, TL061I, TL062I, TL064ITL064BCPARAMETER TEST CONDITIONS(1) UNIT MIN TYP MAX MIN TYP MAX TA = 25°C 2 3 3 6 VIO Input offset voltage VO = 0, RS = 50 Ω mV TA = Full range 5 9 Temperature coefficientαVIO VO = 0, RS = 50 Ω, TA = Full range 10 10 μV/°Cof input offset voltage TA = 25°C 5 100 5 100 pA IIO Input offset current VO = 0 TA = Full range 3 10 nA TA = 25°C 30 200 30 200 pA IIB Input bias current(2) VO = 0 TA = Full range 7 20 nA –12 –12Common-mode inputVICR TA = 25°C ±11 to ±11 to Vvoltage range 15 15 RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5Maximum peak outputVOM Vvoltage swing RL ≥ 10 kΩ, TA = Full range ±10 ±10 TA = 25°C 4 6 4 6Large-signal differential VO = ±10 V,AVD V/mVvoltage amplification RL ≥ 2 kΩ TA = Full range 4 4 B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz ri Input resistance TA = 25°C Ω1012 1012 Common-mode VIC = VICRmin,CMRR 80 86 80 86 dBrejection ratio VO = 0, RS = 50 Ω, TA = 25°C Supply-voltage VCC = ±9 V to ±15 V,kSVR rejection ratio 80 95 80 95 dBVO = 0, RS = 50 Ω, TA = 25°C(ΔVCC±/ΔVIO) Total power dissipationPD VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW(each amplifier) Supply currentICC VO = 0, No load, TA = 25°C 200 250 200 250 µA(each amplifier) VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI. (2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

6.9 Electrical Characteristics for TL06xM and TL064M

VCC± = ±15 V (unless otherwise noted) TL061M, TL062M TL064M PARAMETER TEST CONDITIONS(1) UNIT MIN TYP MAX MIN TYP MAX TA = 25°C 3 6 3 9 VIO Input offset voltage VO = 0, RS = 50 Ω mVTA = –55°C to 9 15125°C Temperature coefficient VO = 0, RS = 50 Ω,αVIO 10 10 μV/°Cof input offset voltage TA = –55°C to 125°C TA = 25°C 5 100 5 100 pA IIO Input offset current VO = 0 TA = –55°C 20(2) 20(2) nA TA = 125°C 20 20 TA = 25°C 30 200 30 200 pA IIB Input bias current(3) VO = 0 TA = –55°C 50(2) 50(2) nA TA = 125°C 50 50 –12 –12Common-mode inputVICR TA = 25°C ±11 to ±11 to Vvoltage range 15 15 (1) All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified. (2) This parameter is not production tested. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B SLOS078L –NOVEMBER 1978–REVISED MAY 2015 www.ti.com VCC± = ±15 V (unless otherwise noted) TL061M, TL062M TL064M PARAMETER TEST CONDITIONS(1) UNIT MIN TYP MAX MIN TYP MAX RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5Maximum peak outputVOM Vvoltage swing RL ≥ 10 kΩ, TA = –55°C to 125°C ±10 ±10 TA = 25°C 4 6 4 6 Large-signal differential VO = ±10 V,AVD V/mVTA = –55°C tovoltage amplification RL ≥ 2 kΩ 4 4125°C B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C MHz ri Input resistance TA = 25°C Ω1012 1012 Common-mode VIC = VICRmin,CMRR 80 86 80 86 dBrejection ratio VO = 0, RS = 50 Ω, TA = 25°C Supply-voltage VCC = ±9 V to ±15 V,kSVR rejection ratio 80 95 80 95 dBVO = 0, RS = 50 Ω, TA = 25°C(ΔVCC±/ΔVIO) Total power dissipationPD VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW(each amplifier) Supply currentICC VO = 0, No load, TA = 25°C 200 250 200 250 µA(each amplifier) VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB

6.10 Operating Characteristics

VCC± = ±15 V, TA= 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI = 10 V, CL = 100 pF,SR Slew rate at unity gain(1) 1.5 3.5 V/μsRL = 10 kΩ, see Figure 16 tr Rise-time 0.2 μsVI = 20 V, CL = 100 pF, RL = 10 kΩ, see Figure 16Overshoot factor 10% Vn Equivalent input noise voltage RS = 20 Ω f = 1 kHz 42 nV/√Hz (1) Slew rate at –55°C to 125°C is 0.7 V/μs min.

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Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

6.11 Typical Characteristics

Table 1. Table of Graphs

Figure 1. Maximum Peak Output Voltage vs Supply Voltage Figure 2. Maximum Peak Output Voltage vs Free-Air Figure 4. Maximum Peak Output Voltage vs FrequencyFigure 3. Maximum Peak Output Voltage vs Load Figure 5. Differential Voltage Amplification vs Free-Air Figure 6. Large-Signal Differential Voltage Amplification and

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Figure 14. Output Voltage vs Elapsed TimeFigure 13. Voltage-Follower Large-Signal Pulse Response Figure 15. Equivalent Input Noise Voltage vs Frequency

12 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

7 Parameter Measurement Information

Figure 16. Unity-Gain Amplifier Figure 17. Gain-of-10 Inverting Amplifier Figure 18. Input Offset-Voltage Null Circuit

50 Ω 100 Ω VCC+ OUT V CC−OFFSET N1 TL061 Only OFFSET N2 IN− C1 = 10 pF on TL061, TL062, and TL064 Component values shown are nominal. TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B SLOS078L –NOVEMBER 1978–REVISED MAY 2015 www.ti.com

8 Detailed Description

8.1 Overview

The JFET-input operational amplifiers of the TL06x series are designed as low-power versions of the TL08x series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset and input bias currents. The TL06x series features the same terminal assignments as the TL07x and TL08x series. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in an integrated circuit. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C, and the M-suffix devices are characterized for operation over the full military temperature range of −55°C to 125°C.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Common-Mode Rejection Ratio

The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers are designed to have it as high as possible. The CMRR of this device is 86 dB.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. These devices have a 3.5-V/μs slew rate.

14 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061,TL061A,TL061B TL062,TL062A,TL062B,TL064,TL064A,TL064B www.ti.com SLOS078L –NOVEMBER 1978–REVISED MAY 2015

8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single supply operational amplifier or dual supply amplifier depending on the application. Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

section show principles used in all applications of these parts.

9.2 Typical Applications

9.2.1 Inverting Amplifier Application

Figure 19. Schematic for Inverting Amplifier Application

9.2.1.1 Design Requirements

accommodate this application.

9.2.1.2 Detailed Design Procedure

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9.2.1.3 Application Curve

Figure 20. Input and Output Voltages of the Inverting Amplifier

9.3 System Examples

9.3.1 General Applications

Figure 21. Instrumentation Amplifier Figure 22. 0.5-Hz Square-Wave Oscillator Figure 23. High-Q Notch Filter Figure 24. Audio-Distribution Amplifier

1.2 MΩ 100 kΩ

Figure 25. Low-Level Light Detector Preamplifier Figure 26. AC Amplifier Figure 27. Microphone Preamplifier With Tone Figure 28. Instrumentation Amplifier

18 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Figure 29. IC Preamplifier

10 Power Supply Recommendations

impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.

11 Layout

11.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Examples.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Examples

Figure 30. Operational Amplifier Schematic for Noninverting Configuration Figure 31. Operational Amplifier Board Layout for Noninverting Configuration

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser based versions of this data sheet, refer to the left hand navigation.

www.ti.com 26-Aug-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 81023022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023022A TL062MFKB 8102302PA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 8102302PA TL062M 81023032A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023032A TL064MFKB 8102303CA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 8102303CA TL064MJB 8102303DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8102303DA TL064MWB TL061ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 061AC TL061ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 061AC TL061ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 061AC TL061ACP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL061ACP TL061BCP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL061BCP TL061BCPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL061BCP TL061CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C TL061CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C TL061CP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL061CP TL061CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T061 TL061ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I

www.ti.com 26-Aug-2020 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL061IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I TL061IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I TL061IP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 TL061IP TL061IPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 TL061IP TL062ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062AC TL062ACP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL062ACP TL062ACPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062A TL062ACPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062A TL062BCD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062BC TL062BCDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062BC TL062BCDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 062BC TL062BCP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL062BCP TL062BCPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL062BCP

www.ti.com 26-Aug-2020 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL062CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C TL062CP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL062CP TL062CPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL062CP TL062CPS OBSOLETE SO PS 8 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T062 TL062ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I TL062IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I TL062IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I TL062IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I

www.ti.com 26-Aug-2020 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL062IP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 TL062IP TL062IPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 TL062IP TL062IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 Z062 TL062IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 Z062 TL062MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023022A TL062MFKB TL062MJG ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 TL062MJG TL062MJGB ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 8102302PA TL062M TL064ACD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC TL064ACDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC TL064ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC TL064ACN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL064ACN TL064BCD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC TL064BCDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC TL064BCDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC TL064BCN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL064BCN TL064BCNE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL064BCN TL064CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C TL064CDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C

www.ti.com 26-Aug-2020 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL064CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C TL064CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C TL064CN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type 0 to 70 TL064CN TL064CNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 TL064 TL064CPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T064 TL064CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T064 TL064CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T064 TL064CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 T064 TL064ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU | SN Level-1-260C-UNLIM -40 to 85 TL064I TL064IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IN ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 TL064IN TL064INE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -40 to 85 TL064IN TL064INS ACTIVE SO NS 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064INSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I TL064IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 Z064 TL064MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023032A

www.ti.com 26-Aug-2020 Addendum-Page 6 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL064MFKB TL064MJ ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 TL064MJ TL064MJB ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 8102303CA TL064MJB TL064MWB ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8102303DA TL064MWB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 26-Aug-2020 Addendum-Page 7 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL062, TL062M, TL064, TL064M :

• Catalog: TL062, TL064
• Military: TL062M , TL064M NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 28-Dec-2019 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL061ACDR SOIC D 8 2500 340.5 338.1 20.6 TL061CDR SOIC D 8 2500 340.5 338.1 20.6 TL061CDR SOIC D 8 2500 367.0 367.0 35.0 TL061IDR SOIC D 8 2500 340.5 338.1 20.6 TL061IDR SOIC D 8 2500 367.0 367.0 35.0 TL062ACDR SOIC D 8 2500 340.5 338.1 20.6 TL062BCDR SOIC D 8 2500 340.5 338.1 20.6 TL062CDR SOIC D 8 2500 340.5 338.1 20.6 TL062CDR SOIC D 8 2500 367.0 367.0 35.0 TL062CPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL062CPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0 TL062IDR SOIC D 8 2500 367.0 367.0 35.0 TL062IDR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 28-Dec-2019 Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL062IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL064ACDR SOIC D 14 2500 367.0 367.0 38.0 TL064BCDR SOIC D 14 2500 367.0 367.0 38.0 TL064CDR SOIC D 14 2500 367.0 367.0 38.0 TL064CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TL064IDR SOIC D 14 2500 367.0 367.0 38.0 TL064IDRG4 SOIC D 14 2500 367.0 367.0 38.0 TL064INSR SO NS 14 2000 367.0 367.0 38.0 TL064IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 28-Dec-2019 Pack Materials-Page 3

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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