TL051ACDE4

TL05X_08 STMICROELECTRONICS | Alldatasheet

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Direct Upgrades to TL07x and TL08x BiFET Operational Amplifiers /C0068 Faster Slew Rate (20 V/µs Typ) Without Increased Power Consumption /C0068 On-Chip Offset-Voltage Trimming for Improved DC Performance and Precision Grades Are Available (1.5 mV, TL051A) 1OUT 1IN– 1IN+ VCC+ 2IN+ 2IN– 2OUT 4OUT 4IN– 4IN+ V CC– 3IN+ 3IN– 3OUT OFFSET N1 IN– IN+ VCC– NC V CC+ OUT OFFSET N2 1OUT 1IN– 1IN+ VCC– VCC+ 2OUT 2IN– 2IN+ TL054 D, DB, N, OR NS PACKAGE (TOP VIEW) TL051 D OR P PACKAGE (TOP VIEW) TL052 D, P, OR PS PACKAGE (TOP VIEW) description/ordering information The TL05x series of JFET-input operational amplifiers offers improved dc and ac characteristics over the TL07x and TL08x families of BiFET operational amplifiers. On-chip Zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL051A) for greater accuracy in dc-coupled applications. Texas Instruments improved BiFET process and optimized designs also yield improved bandwidth and slew rate without increased power consumption. The TL05x devices are pin-compatible with the TL07x and TL08x and can be used to upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL05x family was designed to offer higher precision and better ac response than the TL08x, with the low noise floor of the TL07x. Designers requiring significantly faster ac response or ensured lower noise should consider the Excalibur TLE208x and TLE207x families of BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at mid-supply. Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single supplies. The TL05x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth requirements, and also the output loading. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ORDERING INFORMATION

AT 25°C PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (P) Tube of 50 TL051ACP TL051ACP PDIP (P) Tube of 50 TL052ACP TL052ACP 800 µV Tube of 75 TL051ACD 051AC SOIC (D) Tube of 75 TL052ACD 052AC Reel of 2500 TL052ACDR 052AC PDIP (P) Tube of 50 TL051CP TL051CP PDIP (P) Tube of 50 TL052CP TL052CP PDIP (N) Tube of 25 TL054ACN TL054ACN Tube of 75 TL051CD TL051C 0°Ct o7 0°C Reel of 2500 TL051CDR TL051C 0°C to 70°C 1.5 mV SOIC (D) Tube of 75 TL052CD TL052CSOIC (D) Reel of 2500 TL052CDR TL052C Tube of 50 TL054ACD TL054C Reel of 2500 TL054ACDR TL054C SOP (PS) Reel of 2000 TL052CPSR TL052 SSOP (DB) Reel of 2000 TL054CDBR TL054 PDIP (N) Tube of 25 TL054CN TL054CN 4m V SOIC (D) Tube of 50 TL054CD TL054C4 mV SOIC (D) Reel of 2500 TL054CDR TL054C SOP (NS) Reel of 2000 TL054CNSR TL054 PDIP (P) Tube of 50 TL052AIP TL052AI 800 µV SOIC (D) Tube of 75 TL052AID 052AISOIC (D) Reel of 2500 TL052AIDR 052AI PDIP (N) Tube of 25 TL054AIN TL054AIN PDIP (P) Tube of 50 TL051IP TL051IP PDIP (P) Tube of 50 TL052IP TL052IP 40°Ct o8 5°C 15m V Tube of 75 TL051ID TL051I –40°C to 85°C 1.5 mV Tube of 75 TL052ID TL052I SOIC (D) Reel of 2500 TL052IDR TL052I Tube of 50 TL054AID TL054AI Reel of 2500 TL054AIDR TL054AI PDIP (N) Tube of 25 TL054IN TL054IN 4 mV SOIC (D) Tube of 50 TL054ID TL054ISOIC (D) Reel of 2500 TL054IDR TL054I † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 symbol (each amplifier) –IN– IN+ OUT equivalent schematic (each amplifier) OFFSET N2 OFFSET N1 IN– IN+ VCC+ Q14 Q10 Q11 Q9Q5 JF1 JF2 Q13 Q16 JF3Q15 Q17 OU T VCC – R2 R3 Q12 R10 D2 See Note A NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x. ACTUAL DEVICE COMPONENT COUNT † COMPONENT TL051 TL052 TL054 Transistors 20 34 62 Resistors 10 19 37 Diodes 2 3 5 Capacitors 1 2 4 † These figures include all four amplifiers and all ESD, bias, and trim circuitry.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC –. 2. Differential voltages are at IN+ with respect to IN–. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions C SUFFIX I SUFFIX UNITMIN MAX MIN MAX UNIT VCC ± Supply voltage ±5 ±15 ±5 ±15 V VIC Common mode input voltage VCC ± = ±5 V –1 4 –1 4 VVIC Common -mode input voltage VCC ± = ±15 V –11 11 –11 11 V TA Operating free-air temperature 0 70 –40 85 °C

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL051C and TL051AC electrical characteristics at specified free-air temperature TL051C, TL051AC PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNIT MIN TYP MAX MIN TYP MAX TL051C 25°C 0.75 3.5 0.59 1.5 VIO Input offset voltage TL051C Full range 4.5 2.5 mVVIO Input offset voltage TL051AC 25°C 0.55 2.8 0.35 0.8 mV VO =0 TL051AC Full range 3.8 1.8 /C0097 Temperature coefficient VO = 0, VIC = 0, R S = 50 Ω TL051C 25°C to 70°C 8 8 µV/°C/C0097 V IO of input offset voltage‡ R S = 50 Ω TL051AC 25°C to 70°C 8 8 25 µV/°C Input offset-voltage long-term drift§ 25°C 0.04 0.04 µV/mo IIO Input offset current VO = 0, V IC = 0, 25°C 4 100 5 100 pA IIO Input offset current OI C See Figure 5 70°C 0.02 1 0.025 1 nA IIB Input bias current VO = 0, V IC = 0, 25°C 20 200 30 200 pA IIB Input bias current OI C See Figure 5 70°C 0.15 4 0.2 4 nA VICR Common-mode input 25°C to –2.3 to 5.6 –11 to –12.3 to 15.6 VVICR voltage range Full range to –11 to V R L =1 0kΩ 25°C 3 4.2 13 13.9 VOM Maximum positive peak R L = 10 kΩ Full range 3 13 VVOM+ output voltage swing R L =2k Ω 25°C 2.5 3.8 11.5 12.7 V R L = 2 kΩ Full range 2.5 11.5 R L =1 0kΩ VOM Maximum negative peak R L = 10 kΩ Full range –2.5 –12 VVOM – g output voltage swing R L =2k Ω R L = 2 kΩ Full range –2.3 –11 L i l diff ti l 25°C 25 59 50 105 AVD Large-signal differential voltage amplification¶ R L = 2 kΩ 0°C 30 65 60 129 V/mVvoltage am lification¶ 70°C 20 46 30 85 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF Common mode V V min 25°C 65 85 75 93 CMRR C ommon-mo de rejection ratio VIC = VICRm in, VO =0 R S =5 0Ω 0°C 65 84 75 92 dBrejection ratio VO = 0, R S = 50 Ω 70°C 65 84 75 91 Supply voltage rejection 25°C 75 99 75 99 kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VO = 0, R S = 50 Ω 0°C 75 98 75 98 dBratio (∆VCC ±/∆VIO) 70°C 75 97 75 97 25°C 2.6 3.2 2.7 3.2 ICC Supply current V O = 0, No load 0°C 2.7 3.2 2.8 3.2 mACC y O 70°C 2.6 3.2 2.7 3.2 † Full range is 0°C to 70°C. ‡ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ For VCC ± = ±5 V, VO = ±2.3 V, or for VCC ± = ±15 V, VO = ±10 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL051C and TL051AC operating characteristics at specified free-air temperature TL051C, TL051AC PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNIT MIN TYP MAX MIN TYP MAX P iti l t 25°C 16 13 20 SR+ Positive slew rate at unity gain‡ R L = 2 kΩ ,C L = 100 pF, Full range 16.4 11 22.6 V/µs Nt i l t L , L , See Figure 1 25°C 15 13 18 V/µs SR – N egative slew rate at unity gain‡ Full range 16 11 19.3 25°C 55 56 tr Rise time 0°C 54 55 70°C 63 63 nsVI(PP) = ±10 mV, R2 k Ω 25°C 55 57 ns tf Fall time R L = 2 kΩ , C L = 100pF 0°C 54 56C L = 100 F, See Figures 1 and 2 70°C 62 64g 25°C 24 19 Overshoot factor 0°C 24 19 % 70°C 24 19 V Equivalent input noise f = 10 Hz 25°C 75 75 nV/√HzVn q voltage§ R S = 20 Ω, f = 1 kHz 25°C 18 18 30 nV/√H z VN(PP) Peak-to-peak equivalent input noise voltage See Figure 3 f = 10 Hz to 10 kHz 25°C 4 4 µV In Equivalent input noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ R S = 1 kΩ , f = 1 kHz R L = 2 kΩ , 25°C 0.003 0.003 % V1 0 V R 2 k Ω 25°C 3 3.1 B1 Unity-gain bandwidth VI = 10 mV, R L = 2 kΩ , C L =2 5pF See Figure 4 0°C 3.2 3.3 MHzC L = 25 F, See Figure 4 70°C 2.7 2.8 Phase margin at unity V1 0 m V R 2 k Ω 25°C 59 62 φm Phase margin at unity gain VI = 10 mV, R L = 2 kΩ , C L = 25 pF, See Figure 4 0°C 58 62 deggain C L = 25 F, See Figure 4 70°C 59 62 † Full range is 0°C to 70°C. ‡ For VCC ± = ±5 V, VI(PP) = ±1 V; for VCC ± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC ± = ±5 V, VO(RMS) = 1 V; for VCC ± = ±15 V, VO(RMS) = 6 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL051I and TL051AI electrical characteristics at specified free-air temperature TL051I, TL051AI PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX TL051I 25°C 0.75 3.5 0.59 1.5 VIO Input offset voltage TL051I Full range 5.3 3.3 mVVIO Input offset voltage TL051AI 25°C 0.55 2.8 0.35 0.8 mV VO =0 TL051AI Full range 4.6 2.6 /C0097 Temperature coefficient of VO = 0, VIC = 0, R S = 50 Ω TL051I 25°C to 85°C 7 8 µV/°C/C0097 V IO input offset voltage‡ R S = 50 Ω TL051AI 25°C to 85°C 8 8 25 µV/°C Input offset-voltage long-term drift§ 25°C 0.04 0.04 µV/mo IIO Input offset current VO = 0, V IC = 0, 25°C 4 100 5 100 pA IIO Input offset current OI C See Figure 5 85°C 0.06 10 0.07 10 nA IIB Input bias current VO = 0, V IC = 0, 25°C 20 200 30 200 pA IIB Input bias current OI C See Figure 5 85°C 0.6 20 0.7 20 nA VICR Common-mode input 25°C to –2.3 to 5.6 –11 to –12.3 to 15.6 VVICR voltage range Full range to –11 to V R L =1 0kΩ 25°C 3 4.2 13 13.9 VOM Maximum positive peak R L = 10 kΩ Full range 3 13 VVOM + output voltage swing R L =2k Ω 25°C 2.5 3.8 11.5 12.7 V R L = 2 kΩ Full range 2.5 11.5 R L =1 0kΩ VOM Maximum negative peak R L = 10 kΩ Full range –2.5 –12 VVOM – g output voltage swing R L =2k Ω R L = 2 kΩ Full range –2.3 –11 L i l diff ti l 25°C 25 59 50 105 AVD Large-signal differential voltage amplification¶ R L = 2 kΩ –40°C 30 74 60 145 V/mVvoltage am lification¶ 85°C 20 43 30 76 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF Common mode VIC = VICRmin, 25°C 65 85 75 93 CMRR C ommon-mo de rejection ratio VIC VICRmin, VO = 0, –40°C 65 83 75 90 dBrejection ratio R S = 50 Ω 85°C 65 84 75 93 Supply voltage rejection V0 25°C 75 99 75 99 kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VO = 0, R S =5 0Ω –40°C 75 98 75 98 dBratio (∆VCC ±/∆VIO) R S = 50 Ω 85°C 75 99 75 99 25°C 2.6 3.2 2.7 3.2 ICC Supply current V O = 0, No load –40°C 2.4 3.2 2.6 3.2 mA 85°C 2.5 3.2 2.6 3.2 † Full range is –40°C to 85°C ‡ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ For VCC ± = ±5 V, VO = ±2.3 V, or for VCC ± = ±15 V, VO = ±10 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL051I and TL051AI operating characteristics at specified free-air temperature TL051I, TL051AI PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNIT MIN TYP MAX MIN TYP MAX P iti l t 25°C 16 13 20 SR+ Positive slew rate at unity gain‡ R L = 2 kΩ ,C L = 100 pF, Full range 11 V/µs Nt i l t L , L , See Figure 1 25°C 15 13 18 V/µs SR – N egative slew rate at unity gain‡ Full range 11 25°C 55 56 tr Rise time –40°C 52 53 85°C 64 65 nsVI(PP) = ±10 mV, R2 k Ω 25°C 55 57 ns tf Fall time R L = 2 kΩ , C L = 100pF –40°C 51 53C L = 100 F, See Figures 1 and 2 85°C 64 65g 25°C 24 19 Overshoot factor –40°C 24 19 % 85°C 24 19 V Equivalent input noise f = 10 Hz 25°C 75 75 nV/√HzVn q voltage§ R S = 20 Ω, f = 1 kHz 25°C 18 18 30 nV/√H z VN(PP) Peak-to-peak equivalent input noise voltage See Figure 3 f = 10 Hz to 10 kHz 25°C 4 4 µV In Equivalent input noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ R S = 1 kΩ , f = 1 kHz R L = 2 kΩ , 25°C 0.003 0.003 % V1 0 V R 2 k Ω 25°C 3 3.1 B1 Unity-gain bandwidth VI = 10 mV, R L = 2 kΩ , C L =2 5pF See Figure 4 –40°C 3.5 3.6 MHzC L = 25 F, See Figure 4 85°C 2.6 2.7 Phase margin at unity V1 0 m V R 2 k Ω 25°C 59 62 φm Phase margin at unity gain VI = 10 mV, R L = 2 kΩ , C L = 25 pF, See Figure 4 –40°C 58 61 deggain C L = 25 F, See Figure 4 85°C 59 62 † Full range is –40°C to 85°C. ‡ For VCC ± = ±5 V, VI(PP) = ±1 V; for VCC ± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC ± = ±5 V, VO(RMS) = 1 V; for VCC ± = ±15 V, VO(RMS) = 6 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL052C and TL052AC electrical characteristics at specified free-air temperature TL052C, TL052AC PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX TL052C 25°C 0.73 3.5 0.65 1.5 VIO Input offset voltage TL052C Full range 4.5 2.5 mVVIO Input offset voltage V0 TL052AC 25°C 0.51 2.8 0.4 0.8 mV VO = 0, VIC =0 TL052AC Full range 3.8 1.8VIC = 0, R S = 50 Ω TL052C 25°C to 8 8 /C0097 Temperature coefficient R S 50 Ω TL052C 70°C 8 8 µV/°C/C0097 V IO of input offset voltage‡ TL052AC 25°C to 8 6 25 µV/°C TL052AC 70°C 8 6 25 Input offset-voltage long-term drift§ VO = 0, R S = 50 Ω VIC = 0, 25°C 0.04 0.04 µV/mo IIO Input offset current VO = 0, VIC =0 25°C 4 100 5 100 pA IIO Input offset current O , See Figure 5 VIC = 0, 70°C 0.02 1 0.025 1 nA IIB Input bias current VO = 0, VIC =0 25°C 20 200 30 200 pA IIB Input bias current O , See Figure 5 VIC = 0, 70°C 0.15 4 0.2 4 nA VICR Common-mode input 25°C to –2.3 to 5.6 –11 to –12.3 to 15.6 VVICR voltage range Full range to –11 to V R L =1 0kΩ 25°C 3 4.2 13 13.9 VOM Maximum positive peak R L = 10 kΩ Full range 3 13 VVOM+ output voltage swing R L =2k Ω 25°C 2.5 3.8 11.5 12.7 V R L = 2 kΩ Full range 2.5 11.5 R L =1 0kΩ VOM Maximum ne gative peak R L = 10 kΩ Full range –2.5 –12 VVOM – g output voltage swing R L =2k Ω V R L = 2 kΩ Full range –2.3 –11 L i l diff ti l 25°C 25 59 50 105 AVD Large-signal differential voltage amplification¶ R L = 2 kΩ 0°C 30 65 60 129 V/mVvoltage am lification¶ 70°C 20 46 30 85 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF Common mode V V min 25°C 65 85 75 93 CMRR C ommon-mo de rejection ratio VIC = VICRm in, VO = 0, R S = 50 Ω 0°C 65 84 75 92 dBrejection ratio VO = 0, 70°C 65 84 75 91 † Full range is 0°C to 70°C. ‡ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ For VCC ± =±5 V, VO = ±2.3 V; at VCC ± = ±15 V, VO = ±10 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL052C and TL052AC electrical characteristics at specified free-air temperature (continued) TL052C, TL052AC PARAMETER TEST CONDITIONS TA VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX S l lt j ti 25°C 75 99 75 99 kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VO = 0, R S = 50 Ω 0°C 75 98 75 98 dBratio (∆VCC ±/∆VIO) 70°C 75 97 75 97 Sl t 25°C 4.6 5.6 4.8 5.6 ICC Supply current (two amplifiers) VO = 0, No load 0°C 4.7 6.4 4.8 6.4 mA(two am lifiers) 70°C 4.4 6.4 4.6 6.4 VO1 /VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL052C and TL052AC operating characteristics at specified free-air temperature TL052C, TL052AC PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX SR+ Slew rate at unity gain 25°C 17.8 9 20.7 SR + Slew rate at unity gain R L = 2 kΩ, C L = 100 pF,Full range 8 V/µs SR Ne gative slew rate See Figure 1 25°C 15.4 9 17.8 V/µs SR – g at unity gain‡ Full range 8 25°C 55 56 tr Rise time 0°C 54 55 70°C 63 63 nsVI(PP) = ±10 mV, R2 k Ω 25°C 55 57 ns tf Fall time R L = 2 kΩ, C L = 100pF 0°C 54 56C L = 100 F, See Figures 1 and 2 70°C 62 64g 25°C 24 19 Overshoot factor 0°C 24 19 % 70°C 24 19 V Equivalent input noise f = 10 Hz 25°C 71 71 nV/√HzVn q voltage§ R S = 20 Ω , f = 1 kHz 25°C 19 19 30 nV/√H z VN(PP) Peak-to-peak equivalent input noise current See Figure 3f = 10 Hz to 10 kHz 25°C 4 4 µV In Equivalent input noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ R S = 1 kΩ , f = 1 kHz R L = 2 kΩ , 25°C 0.003 0.003 % V1 0 V R2 k Ω 25°C 3 3 B1 Unity-gain bandwidth VI = 10 mV, C L =2 5pF R L = 2 kΩ , See Figure 4 0°C 3.2 3.2 MHzC L = 25 F, See Figure 4 70°C 2.6 2.7 Phase margin at unity V1 0 m V R2 k Ω 25°C 60 63 φm Phase margin at unity gain VI = 10 mV, C L = 25 pF, R L = 2 kΩ , See Figure 4 0°C 59 63 deggain C L = 25 F, See Figure 4 70°C 60 63 † Full range is 0°C to 70°C. ‡ For VCC ± =±5 V, VI(PP) = ±1 V; for VCC ± = ±15 V, VI(PP) =±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC ± = ±5 V, VO(RMS) = 1 V; for VCC ± =±15 V, VO(RMS) = 6 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL052I and TL052AI electrical characteristics at specified free-air temperature TL052I, TL052AI PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX TL052I 25°C 0.73 3.5 0.65 1.5 VIO Input offset voltage TL052I Full range 5.3 3.3 mVVIO Input offset voltage V0 TL052AI 25°C 0.51 2.8 0.4 0.8 mV VO = 0, VIC = 0, TL052AI Full range 4.6 2.6 /C0097 Ttf f i i t ‡ VIC = 0, R S = 50 Ω TL052I 25°C to 85°C 7 6 µV/°C/C0097 V IO Temperature coefficient‡ TL052AI 25°C to 85°C 6 6 25 µV/°C Input offset-voltage long-term drift§ VO = 0, R S = 50 Ω VIC = 0, 25°C 0.04 0.04 µV/mo IIO Input offset current VO = 0, VIC = 0, 25°C 4 100 5 100 pA IIO Input offset current O , See Figure 5 IC , 85°C 0.06 10 0.07 10 nA IIB Input bias current VO = 0, VIC = 0, 25°C 20 200 30 200 pA IIB Input bias current O , See Figure 5 IC , 85°C 0.6 20 0.7 20 nA VICR Common-mode input 25°C to –2.3 to 5.6 –11 to –12.3 to 15.6 VVICR voltage range Full range to –11 to V R L =1 0kΩ 25°C 3 4.2 13 13.9 VOM Maximum positive peak R L = 10 kΩ Full range 3 13 VVOM+ output voltage swing R L =2k Ω 25°C 2.5 3.8 11.5 12.7 V R L = 2 kΩ Full range 2.5 11.5 R L =1 0kΩ VOM Maximum ne gative peak R L = 10 kΩ Full range –2.5 –12 VVOM – g output voltage swing R L =2k Ω V R L = 2 kΩ Full range –2.3 –11 L i l diff ti l 25°C 25 59 50 105 AVD Large-signal differential voltage amplification¶ R L = 2 kΩ –40°C 30 74 60 145 V/mVvoltage am lification¶ 85°C 20 43 30 76 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF Common mode V V min 25°C 65 85 75 93 CMRR C ommon-mo de rejection ratio VIC = VICRm in, VO = 0, R S = 50 Ω –40°C 65 83 75 90 dBrejection ratio VO = 0, 85°C 65 84 75 93 † Full range is –40°C to 85°C. ‡ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ At VCC ± = ±5 V, VO = ±2.3 V; at VCC ± = ±15 V, VO = ±10 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL052I and TL052AI electrical characteristics at specified free-air temperature (continued) TL052I, TL052AI PARAMETER TEST CONDITIONS TA VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX S l lt j ti 25°C 75 99 75 99 kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VO = 0, R S = 50 Ω –40°C 75 98 75 98 dBratio (∆VCC ±/∆VIO) 85°C 75 99 75 99 Sl t 25°C 4.6 5.6 4.8 5.6 ICC Supply current (two amplifiers) VO = 0, No load –40°C 4.5 6.4 4.7 6.4 mA(two am lifiers) 85°C 4.4 6.4 4.6 6.4 VO1 /VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL052I and TL052AI operating characteristics at specified free-air temperature TL052I, TL052AI PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX SR+ S l tti t i ‡ 25°C 17.8 9 20.7 SR + Slew rate at unity gain‡ R L = 2 kΩ, C L = 100 pF, Full range 8 V/µs SR Ne gative slew rate at L , L , See Figure 1 25°C 15.4 9 17.8 V/µs SR – g unity gain‡ Full range 8 25°C 55 56 tr Rise time –40°C 52 53 85°C 64 65 ns VI(PP)= ±10 mV, 25°C 55 57 ns tf Fall time VI(PP) = ±10 mV , R L = 2 kΩ, C L = 100 pF, –40°C 51 53 See Figures 1 and 2 85°C 64 65 25°C 24% 19% Overshoot factor –40°C 24% 19% % 85°C 24% 19 V Equivalent input noise f = 10 Hz 25°C 71 71 nV/√HzVn q voltage§ R S = 20 Ω , f = 1 kHz 25°C 19 19 30 nV/√H z VN(PP) Peak-to-peak equivalent input noise current See Figure 3f = 10 Hz to 10 kHz 25°C 4 4 µV In Equivalent input noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ R S = 1 kΩ , f = 1 kHz R L = 2 kΩ , 25°C 0.003 0.003 % V1 0 V R2 k Ω 25°C 3 3 B1 Unity-gain bandwidth VI = 10 mV, C L =2 5pF R L = 2 kΩ , See Figure 4 –40°C 3.5 3.6 MHzC L = 25 F, See Figure 4 85°C 2.5 2.6 Phase margin at unity V1 0 m V R2 k Ω 25°C 60 63 φm Phase margin at unity gain VI = 10 mV, C L = 25 pF, R L = 2 kΩ , See Figure 4 –40°C 58 61 deggain C L = 25 F, See Figure 4 85°C 60 63 † Full range is –40°C to 85°C. ‡ For VCC ± =±5 V, VI(PP) = ±1 V; for VCC ± = ±15 V, VI(PP) =±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC ± = ±5 V, VO(RMS) = 1 V; for VCC ± =±15 V, VO(RMS) = 6 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL054C and TL054AC electrical characteristics at specified free-air temperature TL054C, TL054AC PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNIT MIN TYP MAX MIN TYP MAX TL054C 25°C 0.64 5.5 0.56 4 VIO Input offset voltage TL054C Full range 7.7 6.2 mVVIO Input offset voltage TL054AC 25°C 0.57 3.5 0.5 1.5 mV VO =0 TL054AC Full range 5.7 3.7 /C0097 Temperature coefficient VO = 0, VIC = 0, R S = 50 Ω TL054C 25°C to 70°C 25 23 µV/°C/C0097 V IO of input offset voltage R S 50 Ω TL054AC 25°C to 70°C 24 23 µV/°C Input offset-voltage long-term drift‡ 25°C 0.04 0.04 µV/mo IIO Input offset current VO = 0, V IC = 0, 25°C 4 100 5 100 pA IIO Input offset current OI C See Figure 5 70°C 0.02 1 0.025 1 nA IIB Input bias current VO = 0, V IC = 0, 25°C 20 200 30 200 pA IIB Input bias current OI C See Figure 5 70°C 0.15 4 0.2 4 nA VICR Common-mode input 25°C to –2.3 to 5.6 –11 to –12.3 to 15.6 VVICR voltage range Full range to –11 to V R L =1 0kΩ 25°C 3 4.2 13 13.9 VOM Maximum positive peak R L = 10 kΩ Full range 3 13 VVOM+ output voltage swing R L =2k Ω 25°C 2.5 3.8 11.5 12.7 V R L = 2 kΩ Full range 2.5 11.5 R L =1 0kΩ VOM Maximum negative peak R L = 10 kΩ Full range –2.5 –12 VVOM – g output voltage swing R L =2k Ω R L = 2 kΩ Full range –2.3 –11 L i l diff ti l 25°C 25 72 50 133 AVD Large-signal differential voltage amplification§ R L = 2 kΩ 0°C 30 88 60 173 V/mVvoltage am lification§ 70°C 20 57 30 85 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF Common mode V V min 25°C 65 84 75 92 CMRR C ommon-mo de rejection ratio VIC = VICRm in, VO =0 R S =5 0Ω 0°C 65 84 75 92 dBrejection ratio VO = 0, R S = 50 Ω 70°C 65 84 75 93 Supply voltage rejectionV ±5Vt o±15 V 25°C 75 99 75 99 kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VCC ± = ±5 V to ±15 V, VO =0 R S =5 0Ω 0°C 75 99 75 99 dBratio (∆VCC ±/∆VIO) VO = 0, R S = 50 Ω 70°C 75 99 75 99 Supply current 25°C 8.1 11.2 8.4 11.2 ICC Supply current (four amplifiers) VO = 0, No load 0°C 8.2 12.8 8.5 12.8 mA(four am lifiers) 70°C 7.9 11.2 8.2 11.2 VO1 /VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB † Full range is 0°C to 70°C. ‡ Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. § For VCC ± = ±5 V, VO = ±2.3 V, at VCC ± = ±15 V, VO = ±10 V.B

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL054C and TL054AC operating characteristics at specified free-air temperature TL054C, TL054C PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNIT MIN TYP MAX MIN TYP MAX SR+ Positive slew rate 25°C 15.4 10 17.8 SR + at unity gain 0°C 15.7 8 17.9 R L = 2 kΩ ,C L = 100 pF, 70°C 14.4 8 17.5 V/µs SR Ne gative slew rate at L L See Figure 1 and Note 7 25°C 13.9 10 15.9 V/µs SR – g unity gain‡ 0°C 14.3 8 16.1 70°C 13.3 8 15.5 25°C 55 56 tr Rise time 0°C 54 55 70°C 63 63 nsVI(PP) = ±10 mV, R2 k Ω 25°C 55 57 ns tf Fall time R L = 2 kΩ , C L = 100pF 0°C 54 56C L = 100 F, See Figures 1 and 2 70°C 62 64See Figures 1 and 2 25°C 24% 19% Overshoot factor 0°C 24% 19% % 70°C 24% 19 V Equivalent input noise f = 10 Hz 25°C 75 75 nV/√HzVn q voltage§ R S = 20 Ω, f = 1 kHz 25°C 21 21 45 nV/√Hz VN(PP) Peak-to-peak equivalent input noise voltage See Figure 3f = 10 Hz to 10 kHz 25°C 4 4 µV In Equivalent input noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ R S = 1 kΩ , f = 1 kHz R L = 2 kΩ , 25°C 0.003 0.003 % V1 0 m V R 2 k Ω 25°C 2.7 2.7 B1 Unity-gain bandwidth VI = 10 mV, R L = 2 kΩ , C L =2 5pF See Figure 4 0°C 3 3 MHzC L = 25 F, See Figure 4 70°C 2.4 2.4 Phase margin at VI=1 0m V R L =2k Ω 25°C 61 64 φm Phase margin at unity gain VI = 10 mV , R L = 2 kΩ , C L = 25 pF See Figure 4 0°C 60 64 degunity gain C L = 25 F, See Figure 4 70°C 61 63 † Full range is 0°C to 70°C. ‡ For VCC ± = ±5 V, VI(PP) = ±1 V; for VCC ± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC ± = ±5 V, VO(RMS ) = 1 V; for VCC ± = ±15 V, VO(RMS) = 6 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL054I and TL054AI electrical characteristics at specified free-air temperature TL054I, TL054AI PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX TL054I 25°C 0.64 5.5 0.56 4 VIO Input offset voltage TL054I Full range 8.8 7.3 mVVIO In ut offset voltage TL054AI 25°C 0.57 3.5 0.5 1.5 mV VO =0 TL054AI Full range 6.8 4.8 /C0097 Temperature coefficient of VO = 0, VIC = 0, R S = 50 Ω TL054I 25°C to 85°C 25 24 µV/°C/C0097 V IO input offset voltage R S 50 Ω TL054AI 25°C to 85°C 25 23 µV/°C Input offset voltage long-term drift‡ 25°C 0.04 0.04 µV/mo IIO Input offset current VO = 0, V IC = 0, 25°C 4 100 5 100 pA IIO Input offset current OI C See Figure 5 85°C 0.06 10 0.07 10 nA IIB Input bias current VO = 0, V IC = 0, 25°C 20 200 30 200 pA IIB Input bias current OI C See Figure 5 85°C 0.6 20 0.7 20 nA VICR Common-mode input 25°C to –2.3 to 5.6 –11 to –12.3 to 15.6 VVICR voltage range Full range to –11 to V R L =1 0kΩ 25°C 3 4.2 13 13.9 VOM Maximum positive peak R L = 10 kΩ Full range 3 13 VVOM+ output voltage swing R L =2k Ω 25°C 2.5 3.8 11.5 12.7 V R L = 2 kΩ Full range 2.5 11.5 R L =1 0kΩ VOM Maximum negative peak R L = 10 kΩ Full range –2.5 –12 VVOM – g output voltage swing R L =2k Ω R L = 2 kΩ Full range –2.3 –11 L i l diff ti l 25°C 25 72 50 133 AVD Large-signal differential voltage amplification§ R L = 2 kΩ –40°C 30 101 60 212 V/mVvoltage am lification§ 85°C 20 50 30 70 ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 10 12 pF Common mode V V min 25°C 65 84 75 92 CMRR C ommon-mo de rejection ratio VIC = VICRm in, VO =0 R S =5 0Ω –40°C 65 83 75 92 dBrejection ratio VO = 0, R S = 50 Ω 85°C 65 84 75 93 Supply voltage rejectionV ±5Vt o±15 V 25°C 75 99 75 99 kSVR Supply-voltage rejection ratio (∆VCC ±/∆VIO) VCC ± = ±5 V to ±15 V, VO =0 R S =5 0Ω –40°C 75 98 75 99 dBratio (∆VCC ±/∆VIO) VO = 0, R S = 50 Ω 85°C 75 99 75 99 Supply current 25°C 8.1 11.2 8.4 11.2 ICC Supply current (four amplifiers) VO = 0, No load –40°C 7.9 12.8 8.2 12.8 mA(four am lifiers) 85°C 7.6 11.2 7.9 11.2 VO1 /VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB † Full range is –40°C to 85°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. § For VCC ± = ±5 V, VO = ±2.3 V, at VCC ± = ±15 V, VO = ±10 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL054I and TL054AI operating characteristics at specified free-air temperature TL054I, TL054AI PARAMETER TEST CONDITIONS TA † VCC ± = ±5 V VCC ± = ±15 V UNITA MIN TYP MAX MIN TYP MAX SR+ Positive slew rate 25°C 15.4 10 17.8 SR + at unity gain –40°C 16.4 8 18 R L = 2 kΩ ,C L = 100 pF, 85°C 14 8 17.3 V/µs SR Ne gative slew rate at L L See Figure 1 25°C 13.9 10 15.9 V/µs SR – g unity gain‡ –40°C 14.7 8 16.1 85°C 13 8 15.3 25°C 55 56 tr Rise time –40°C 52 53 85°C 64 65 ns VI(PP) = ±10 mV, RL = 2 kΩ , 25°C 55 57 ns tf Fall time VI(PP) ±10 mV, R L 2 kΩ , C L = 100 pF, –40°C 51 53 See Figures 1 and 2 85°C 64 65 25°C 24 19 Overshoot factor –40°C 24 19 % 85°C 24 19 V Equivalent input noise f = 10 Hz 25°C 75 75 nV/√HzVn q voltage§ R S = 20 Ω, f = 1 kHz 25°C 21 21 45 nV/√Hz VN(PP) Peak-to-peak equivalent input noise voltage See Figure 3f = 10 Hz to 10 kHz 25°C 4 4 µV In Equivalent input noise current f = 1 kHz 25°C 0.01 0.01 pA/√Hz THD Total harmonic distortion¶ R S = 1 kΩ , f = 1 kHz R L = 2 kΩ , 25°C 0.003% 0.003% % V1 0 m V R 2 k Ω 25°C 2.7 2.7 B1 Unity-gain bandwidth VI = 10 mV, R L = 2 kΩ , C L =2 5pF See Figure 4 –40°C 3.3 3.3 MHzC L = 25 F, See Figure 4 85°C 2.3 2.4 Phase margin at VI=1 0m V R L =2k Ω 25°C 61 64 φm Phase margin at unity gain VI = 10 mV , R L = 2 kΩ , C L = 25 pF See Figure 4 –40°C 59 62 degunity gain C L = 25 F, See Figure 4 85°C 61 64 † Full range is –40°C to 85°C. ‡ For VCC ± = ±5 V, VI(PP) = ±1 V; for VCC ± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC ± = ±5 V, VO(RMS) = 1 V; for VCC ± = ±15 V, VO(RMS) = 6 V.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIO Input offset voltage Distribution 6–11 /C0097 V IO Temperature coefficient of input offset voltageDistribution 12, 13, 14 IIB Input bias current vs Common-mode input voltage vs Free-air temperature IIO Input offset current vs Free-air temperature 16 VIC Common-mode input voltage range limits vs Supply voltage vs Free-air temperature VO Output voltage vs Differential input voltage 19, 20 VOM Maximum peak output voltage vs Supply voltage vs Output current vs Free-air temperature 25, 26 27, 28 VO(PP) Maximum peak-to-peak output voltage vs Frequency 22, 23, 24 AVD Large-signal differential voltage amplification vs Load resistance vs Frequency vs Free-air temperature 31, 32, 33 CMRR Common-mode rejection ratio vs Frequency vs Free-air temperature 34, 35 zo Output impedance vs Frequency 37 kSVR Supply-voltage rejection ratio vs Free-air temperature 38 IOS Short-circuit output current vs Supply voltage vs Time vs Free-air temperature ICC Supply current vs Supply voltage vs Free-air temperature 42, 43, 44 45, 46, 47 SR Slew rate vs Load resistance vs Free-air temperature 48–53 54–59 Overshoot factor vs Load capacitance 60 Vn Equivalent input noise voltage vs Frequency 61, 62 THD Total harmonic distortion vs Frequency 63 B1 Unity-gain bandwidth vs Supply voltage vs Free-air temperature 64, 65, 66 67, 68, 69 φm Phase margin vs Supply voltage vs Load capacitance vs Free-air temperature 70, 71, 72 73, 74, 75 76, 77, 78 Phase shift vs Frequency 30 Voltage-follower small-signal pulse responsevs Time 79 Voltage-follower large-signal pulse responsevs Time 80

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 6 DISTRIBUTION OF TL051 INPUT OFFSET VOLTAGE –1.5 Percentage of Units – % VIO – Input Offset Voltage – mV

433 Units Tested From 1 Wafer Lot

VCC ± = ±15 V TA = 25°C P Package –1.1 –0.6 0.6 1.1 Figure 7 DISTRIBUTION OF TL051A INPUT OFFSET VOLTAGE 9006003000–300–600 VIO – Input Offset Voltage – µV Percentage of Units – % –900 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ

393 Units Tested From 1 Wafer Lot

VCC ± = ±15 V TA = 25°C P Package Figure 8 –1.5 Percentage of A mp lifiers – % VIO – Input Offset Voltage – mV DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE

476 Amplifiers Tested From 1 Wafer Lot

VCC ± = ±15 V TA = 25°C P Package –1.2 –0.6 0.6 1.2 Figure 9 –900 –600 –300 0 300 600 900 VIO – Input Offset Voltage – µV Percentage of Amplifiers – % TA = 25°C DISTRIBUTION OF TL052A INPUT OFFSET VOLTAGE

403 Amplifiers Tested From 1 Wafer Lot

VCC ± = ±15 V P Package

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Percentage of Amplifiers – % VIO – Input Offset Voltage – mV –20 1 3–3 –12 4 VCC ± = ±15 V TA = 25°C N Package

1140 Amplifiers Tested From 3 Wafer Lots

VIO – Input Offset Voltage – mV Percentage of Amplifiers – % –1.8

1048 Amplifiers Tested From 3 Wafer Lots

VCC ± = ±15 V TA = 25°C N Package Figure 12 DISTRIBUTION OF TL051 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT –25 Percentage of Units – % – Temperature Coefficient – µV/°C –20 –15 –10 –5 0 5 1 01 52 0 2 5 ÎÎÎÎÎÎÎÎÎÎ

120 Units Tested From 2 Wafer Lots

VCC ± = ±15 V TA = 25°C to 125°C P Package /C0097 V IO Percentage of Amplifiers – % – Temperature Coefficient – µV/°C 20100–10–20–30 DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ

172 Amplifiers Tested From 2 Wafer Lots

VCC ± = ±15 V TA = 25°C to 125°C P Package ÎÎÎÎÎÎÎÎÎÎ Outlier: One Unit at –34.6 µV/°C Figure 13 /C0097 V IO

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 14 DISTRIBUTION OF TL054 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT –60 – Temperature Coefficient – µV/°C –40 –20 0 20 40 60 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ

324 Amplifiers Tested From 3 Wafer Lots

VCC ± = ±15 V TA = 25°C to 125°C N Package Percentage of Amplifiers – % /C0097 V IO Figure 15 –15 –10 – Input Bias Current – nA VIC – Common-Mode Input Voltage – V –10 –505 1 0 1 5 TA = 25°C VCC ± = ±15 V INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE I IB Figure 16 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT † vs FREE-AIR TEMPERATURE IIO IIB TA – Free-Air Temperature – °C – Input Bias and Offset Currents – nA 0.001 0.01 0.1 100 45 65 85 105 125 VCC ± = ±15 V VO = 0 VIC = 0 I IBand I IO Figure 17 –16 – Common-Mode Input Voltage – V |VCC ±| – Supply Voltage – V –12 2 4 6 8 10 12 14 16 TA = 25°C COMMON-MODE INPUT VOLTAGE RANGE LIMITS vs SUPPLY VOLTAGE VIC ÎÎÎÎÎ Negative Limit ÎÎÎÎÎ Positive Limit † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–75 –20 TA – Free-Air Temperature – °C –15 –10 –50 –25 0 25 50 75 100 125 COMMON-MODE INPUT VOLTAGE RANGE LIMITS † vs FREE-AIR TEMPERATURE – Common-Mode Input Voltage – VVIC ÎÎÎÎÎ ÎÎÎÎÎ VCC ± = ±15 V ÎÎÎÎÎ ÎÎÎÎÎ Positive Limit ÎÎÎÎÎ ÎÎÎÎÎ Negative Limit Figure 19 –200 – Output Voltage – V –100 0 100 200 ÎÎÎÎ ÎÎÎÎ TA = 25°C OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE VID – Differential Input Voltage – µV VO ÎÎÎÎ ÎÎÎÎ R L = 600 Ω ÎÎÎÎ ÎÎÎÎ R L = 1 kΩ ÎÎÎÎÎ R L = 10 kΩ ÎÎÎÎÎ ÎÎÎÎÎ R L = 2 kΩ ÎÎÎÎÎ VCC ± = ±5 V Figure 20 –400 –15 VID – Differential Input Voltage – µV –10 –200 0 200 400 OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE – Output Voltage – VVO ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÎÎÎÎ R L = 600 Ω ÎÎÎÎ ÎÎÎÎ R L = 1 kΩ ÎÎÎÎ R L = 2 kΩ ÎÎÎÎ R L = 10 kΩ ÎÎÎÎÎ ÎÎÎÎÎ VCC ± = ±15 V ÎÎÎÎ TA = 25°C Figure 21 – Maximum Peak Output Voltage – V |VCC ±| – Supply Voltage – V 2 4 6 8 10 12 14 16 TA = 25°C VOM+ R L = 10 kΩ R L = 2 kΩ VOM – R L = 2 kΩ R L = 10 kΩ MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE –12 –16 VOM † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 22 10 k f – Frequency – Hz 100 k 1 M 10 M – Maximum Peak-to-Peak Output Voltage – V R L = 2 kΩ TA = 125°C VCC ± = ±5 V TA = –55°C VCC ± = ±15 V MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE † vs FREQUENCY VO(PP) Figure 23 – Maximum Peak-to-Peak Output Voltage – V 10 k f – Frequency – Hz 100 k 1 M 10 M MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY VO(PP) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ TA = 25°C R L = 2 kΩ ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±5 V ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±15 V Figure 24 10 k 100 k f – Frequency – Hz

1 M 10 M

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY – Maximum Peak-to-Peak Output Voltage – VVO(PP) ÁÁÁÁ ÁÁÁÁ R L = 10 kΩ TA = 25°C ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±15 V ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±5 V Figure 25 – Maximum Peak Output Voltage – V |IO | – Output Current – mA 41 2 1 6 2 08 MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT |VOM | ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ VOM – ÁÁÁ ÁÁÁ VOM+ VCC ± = ±5 V R L = 10 kΩ TA = 25°C 2 6 10 14 18 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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|IO | – Output Current – mA MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT – Maximum Peak Output Voltage – V|VOM | ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±15 V R L = 10 kΩ TA = 25°C ÁÁÁ ÁÁÁ VOM – ÁÁÁÁ ÁÁÁÁ VOM+ 51 52 53 54 5 Figure 27 –75 TA – Free-Air Temperature – °C –50 –25 0 25 50 75 100 125 R L = 2 kΩ R L = 10 kΩ R L = 10 kΩ R L = 2 kΩ VOM+ VCC ± = ±5 V MAXIMUM PEAK OUTPUT VOLTAGE † vs FREE-AIR TEMPERATURE – Maximum Peak Output Voltage – VV OM ÁÁÁ ÁÁÁ VOM – Figure 28 –75 –16 –50 –25 0 25 50 75 100 125 –12 TA – Free-Air Temperature – °C R L = 10 kΩ R L = 10 kΩ R L = 2 kΩ R L = 2 kΩ VCC ± = ±15 V MAXIMUM PEAK OUTPUT VOLTAGE † vs FREE-AIR TEMPERATURE – Maximum Peak Output Voltage – VV OM ÁÁÁ ÁÁÁ VOM+ ÁÁÁ ÁÁÁ VOM – Figure 29 – Differential Voltage Amplification – V/mV 0.4 R L – Load Resistance – kΩ 100 150 200 250 1 4 10 40 100 VO = ±1 V TA = 25°C VCC ± = ±15 V LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE VCC ± = ±5 V A VD † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS f – Frequency – Hz

10 M100 1 k 10 k 100 k 1 M

0.1 101 104 102 103 VCC ± = ±15 V R L = 2 kΩ C L = 25 pF TA = 25°C AVD Phase Shift 30° 60° 90° 120° 150° 180° LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 106 105 – Differential Voltage Amplification – V/mVA VD mφ – Phase Shift Figure 30 –75 TA – Free-Air Temperature – °C 125 1000 –50 –25 0 25 50 75 100 100 400 R L = 2 kΩ R L = 10 kΩ VCC ± = ±5 V VO = ±2.3 V – Differential Voltage Amplification – V/mVA VD Figure 31 TL051 AND TL052 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION † vs FREE-AIR TEMPERATURE Figure 32 –75 TA – Free-Air Temperature – °C 125 1000 –50 –25 0 25 50 75 100 100 400 R L = 2 kΩ R L = 10 kΩ VCC ± = ±5 V VO = ±2.3 V – Differential Voltage Amplification – V/mVA VD TL054 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION † vs FREE-AIR TEMPERATURE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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–75 125 1000 –50 –25 0 25 50 75 100 100

400 R L = 10 kΩ

R L = 2 kΩ TA – Free-Air Temperature – °C LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION † vs FREE-AIR TEMPERATURE ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±15 V VO = 10 V – Differential Voltage Amplification – V/mVA VD Figure 34 CMRR – Common-Mode Rejection Ratio – dB f – Frequency – Hz 10 M 100 100 1 k 10 k 100 k 1 M VCC ± = ±5 V TA = 25°C COMMON-MODE REJECTION RATIO vs FREQUENCY Figure 35 100

1 M100 k10 k1 k100 10 M

f – Frequency – Hz VCC ± = ±15 V TA = 25°C COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR – Common-Mode Rejection Ratio – dB Figure 36 –75 TA – Free-Air Temperature – °C 100 –50 –25 0 25 50 75 100 VIC = VICRMin VCC ± = ±5 V VCC ± = ±15 V COMMON-MODE REJECTION RATIO † vs FREE-AIR TEMPERATURE CMRR – Common-Mode Rejection Ratio – dB 125 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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VO = 0 TA – Free-Air Temperature – °C –20 –40 –60 1007550250–25–50 125–75 VCC ± = ±15 V VCC ± = ±5 V VCC ± = ±5 V VCC ± = ±15 V SHORT-CIRCUIT OUTPUT CURRENT † vs FREE-AIR TEMPERATURE IOS – Short-Circuit Output Current – mA ÁÁ ÁÁ IOS ÎÎÎÎÎ ÎÎÎÎÎ VID = 100 m V ÎÎÎÎÎÎ VID = –100 m V Figure 42 |VCC ±| – Supply Voltage – V 2 4 6 8 10 12 14 0.5 1.5 2.5 TA = 25°C TA = –55°C TA = 125°C VO = 0 No Load ICC – Supply Current – mA ÁÁ ÁÁ ÁÁ ICC TL051 SUPPLY CURRENT † vs SUPPLY VOLTAGE 2 4 6 8 10 12 14 TA = 25°C TA = –55°C TA = 125°C VO = 0 No Load ICC – Supply Current – mA ÁÁ ÁÁ ÁÁ ICC |VCC ±| – Supply Voltage – V Figure 43 TL052 SUPPLY CURRENT † vs SUPPLY VOLTAGE Figure 44 |VCC ±| – Supply Voltage – V 24 6 8 10 12 14 TA = 25°C ÎÎÎÎÎ ÎÎÎÎÎ TA = –55°C TA = 125°C VO = 0 No Load ICC – Supply Current – mA ÁÁ ÁÁ ICC TL054 SUPPLY CURRENT † vs SUPPLY VOLTAGE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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10410.4 R L – Load Resistance – kΩ SR – SR+ C L = 100 pF TA = 25°C See Figure 1 VCC ± = ±5 V SR – Slew Rate – V/µ s Figure 49 TL052 SLEW RATE vs LOAD RESISTANCE 100 Figure 50 SR – Slew Rate – V/ 100401041 R L – Load Resistance – kΩ 0.4 ÎÎ SR+ SR – C L = 100 pF TA = 25°C See Figure 1 VCC ± = ±5 V µ s TL054 SLEW RATE vs LOAD RESISTANCE Figure 51 0.4 R L – Load Resistance – kΩ 1 4 10 40 100 SR+ SR – SR – Slew Rate – V/µ s C L = 100 pF TA = 25°C See Figure 1 VCC ± = ±15 V TL051 SLEW RATE vs LOAD RESISTANCE 1 4 10 40 1000.4 R L – Load Resistance – kΩ SR+ SR – C L = 100 pF TA = 25°C See Figure 1 VCC ± = ±15 V SR – Slew Rate – V/µ s Figure 52 TL052 SLEW RATE vs LOAD RESISTANCE

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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–75 TA – Free-Air Temperature – °C 125 –50 –25 0 25 50 75 100 VCC ± = ±15 V R L = 2 kΩ C L = 100 pF See Figure 1 SR – SR+ SR – Slew Rate – V/µ s TL051 SLEW RATE † vs FREE-AIR TEMPERATURE SR – SR+ –75 TA – Free-Air Temperature – °C 125–50 –25 0 25 50 75 100 VCC ± = ±15 V R L = 2 kΩ C L = 100 pF See Figure 1 SR – Slew Rate – V/µ s Figure 58 TL052 SLEW RATE † vs FREE-AIR TEMPERATURE Figure 59 SR – SR+ –75 TA – Free-Air Temperature – °C 125–50 –25 0 25 50 75 100 VCC ± = ±15 V R L = 2 kΩ C L = 100 pF See Figure 1 SR – Slew Rate – V/µ s TL054 SLEW RATE † vs FREE-AIR TEMPERATURE Figure 60 ÎÎÎÎÎ ÎÎÎÎÎ See Figure 1 ÎÎÎÎÎ TA = 25°C ÎÎÎÎÎ R L = 2 kΩ ÎÎÎÎÎ ÎÎÎÎÎ VI(PP) = ±10 mV Overshoot Factor – % C L – Load Capacitance – pF 300 50 100 150 200 250 OVERSHOOT FACTOR vs LOAD CAPACITANCE ÎÎÎÎÎ VCC ± = ±15 V ÎÎÎÎ ÎÎÎÎ VCC ± = ±5 V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ VI = 10 mV R L = 2 kΩ C L = 25 pF See Figure 4 TA = 25°C 2.7 – Unity-Gain Bandwidth – MHz |VCC ±| – Supply Voltage – V 3.2 4 6 8 10 12 14 2.8 2.9 3.1 B 1 TL052 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE Figure 66 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 2.4 – Unity-Gain Bandwidth – MHz |VCC ±| – Supply Voltage – V 2.9 0 2 6 8 10 14 2.5 2.6 2.7 2.8 B 1 ÎÎÎÎ ÎÎÎÎ VI = 10 mV ÎÎÎÎÎ ÎÎÎÎÎ R L = 2 kΩ ÎÎÎÎÎÎ C L = 25 pF ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ See Figure 4 ÎÎÎÎÎ ÎÎÎÎÎ TA = 25°C 41 2 TL054 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE Figure 67 –75 TA – Free-Air Temperature – °C 125 –50 –25 0 25 50 75 100 See Figure 4 VI = 10 mV R L = 2 kΩ C L = 25 pF VCC ± = ±15 V VCC ± = ±5 V – Unity-Gain Bandwidth – MHzB 1 TL051 UNITY-GAIN BANDWIDTH † vs FREE-AIR TEMPERATURE Figure 68 See Figure 4 VCC ± = ±5 V to ±15 V R L = 2 kΩ C L = 25 pF TA = 25°C VI = 10 mV –75 TA – Free-Air Temperature – °C 125 –50 –25 0 25 50 75 100 – Unity-Gain Bandwidth – MHzB 1 TL052 UNITY-GAIN BANDWIDTH † vs FREE-AIR TEMPERATURE † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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40° C L – Load Capacitance – pF 100 70° 10 20 30 40 50 60 70 80 90 45° 50° 55° 60° 65° VI = 10 mV R L = 2 kΩ TA = 25°C See Figure 4 VCC ± = ±15 V See Note A VCC ± = ±5 V mφ – Phase Margin TL051 PHASE MARGIN † vs LOAD CAPACITANCE Figure 74 C L – Load Capacitance – pF 70° 10 20 30 40 50 60 70 80 90 45° 50° 55° 60° 65° VI = 10 mV R L = 2 kΩ TA = 25°C See Figure 4 ÎÎÎÎÎ VCC ± = ±15 V See Note A ÎÎÎÎÎ ÎÎÎÎÎ VCC ± = ±5 V mφ – Phase Margin TL052 PHASE MARGIN † vs LOAD CAPACITANCE 100 C L – Load Capacitance – pF 100 70° 10 20 30 40 50 60 70 80 90 45° 50° 55° 60° 65° VI = 10 mV R L = 2 kΩ TA = 25°C See Figure 4 ÎÎÎÎÎ ÎÎÎÎÎ VCC ± = ±15 V See Note A ÎÎÎÎÎ VCC ± = ±5 V mφ – Phase Margin TL054 PHASE MARGIN † vs LOAD CAPACITANCE Figure 75 † Values of phase margin below a load capacitance of 25 pF were estimated.

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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–16 – Output Voltage – mV t – Time – µs 1.2 –12 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE VO ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±15 V R L = 2 kΩ C L = 100 pF TA = 25°C See Figure 1 Figure 79 t – Time – µs 0 1 2 3 4 5 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE – Output Voltage – VVO ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC ± = ±15 V R L = 2 kΩ C L = 100 pF TA = 25°C See Figure 1 Figure 80

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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APPLICATION INFORMATION

The TL05x and TL05xA are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Because of the extremely high input impedance and resulting low-bias current requirements, the TL05x and TL05xA are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets easily can exceed bias current requirements and cause degradation in system performance. It is good practice to include guard rings around inputs (see Figure 83). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input. Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation. VO VO VO VI VI (a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER VI Figure 83. Use of Guard Rings circuit impedance greater than 50 kΩ .

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 The phase meter in Figure 84 produces an output voltage of 10 mV per degree of phase delay between the two input signals VA and VB. The reference signal VA must be the same frequency as VB. The TLC3702 comparators (U1) convert these two input sine waves into ±5-V square waves. Then, R1 and R4 provide level shifting prior to the SN74HC109 dual J-K flip flops. Flip-flop U2B is connected as a toggle flip-flop and generates a square wave at one-half the frequency of VB. Flip-flop U2A also produces a square wave at one-half the input frequency. The pulse duration of U2A varies from zero to one-half the period, where zero corresponds to zero phase delay between VA and VB and one-half the period corresponds to VB lagging VA by 360 degrees. The output pulse from U2A causes the TLC4066 (U3) switch to charge the TL05x (U4) integrator capacitors C1 and C2. As the phase delay approaches 360 degrees, the output of U4A approximates a square wave, and U2A has an output of almost 2.5 V. U4B acts as a noninverting amplifier with a gain of 1.44 in order to scale the 0- to 2.5-V integrator output to a 0- to 3.6-V output range. R8 and R10 provide output gain and zero-level calibration. This circuit operates over a 100-Hz to 10-kHz frequency range. +5 V 100 kΩ 100 kΩ U1A VA S U2A R NC U2B VB U1B 10 kΩ 10 kΩ +5 V S R NC100 kΩ 100 kΩ R5 C1 10 kΩ 0.016 µF 0.016 µF U4A U4B V O 20 kΩ Gain 50 kΩ +5 V R10 10 kΩ Zero –5 V NOTE A: U1 = TLC3702; VCC ± = ±5 V U2 = SN74HC109 U3 = TLC4066 U4, U5 = TL05x; VCC ± = ±5 V Figure 84. Phase Meter

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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precision constant-current source over temperature A precision current source (see Figure 85) benefits from the high input impedance and stability of Texas Instruments enhanced-JFET process. A low-current shunt regulator maintains 2.5 V between the inverting input and the output of the TL05x. The negative feedback then forces 2.5 V across the current-setting resistor R; therefore, the current to the load simply is 2.5 V divided by R. Possible choices for the shunt regulator include the LT1004, LT1009, and LM385. If the regulator’s cathode connects to the operational amplifier output, this circuit sources load current. Similarly, if the cathode connects to the inverting input, the circuit sinks current from the load. To minimize output current change with temperature, R should be a metal film resistor with a low temperature coefficient. Also, this circuit must be operated with split-voltage supplies. 150 pF +15 V –15 V R 100 kΩ IO Load V = 0 to 10 V (a) SOURCE CURRENT LOAD (b) SINK CURRENT LOAD V = 0 to –10 V Load II R –15 V +15 V 150 pF 100 kΩ NOTE A: U1 = 1/2 TL05x U2 = LM385, LT1004, or LT1009 voltage reference I =2.5 V R , R = Low-temperature-coefficient metal-film resistor Figure 85. Precision Constant-Current Source

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 43POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 instrumentation amplifier with adjustable gain/null The instrumentation amplifier in Figure 86 benefits greatly from the high input impedance and stable input offset voltage of the TL05xA. Amplifiers U1A, U1B, and U2A form the actual instrumentation amplifier, while U2B provides offset null. Potentiometer R1 provides gain adjustment. With R1 = 2 kΩ , the circuit gain equals 100, while with R1 = 200 kΩ , the circuit gain equals two. The following equation shows the instrumentation amplifier gain as a function of R1: A V /C0043 1 /C0041 /C0466R2 /C0041 R3 R1 /C0467 Readjusting the offset null is necessary when the circuit gain is changed. If U2B is needed for another application, R7 can be terminated at ground. The low input offset voltage of the TL05xA minimizes the dc error of the circuit. For best matching, all resistors should be one-percent tolerance. The matching between R4, R5, R6, and R7 controls the CMRR of this application. The following equation shows the output voltages when the input voltage equals zero. This dc error can be nulled by adjusting the offset null potentiometer; however, any change in offset voltage over time or temperature also creates an error. To calculate the error from changes in offset, consider the three offset components in the equation as delta offsets, rather than initial offsets. The improved stability of Texas Instruments enhanced JFETs minimizes the error resulting from change in input offset voltage with time. Assuming V I equals zero, VO can be shown as a function of the offset voltage: –V IO1/C0426R3 R1 /C0466 R7 R5 /C0041 R7 /C0467 /C04661 /C0041 R6 R4 /C0467 /C0041 R6 R4 /C04661 /C0041 R2 R1 /C0467/C0427 /C0041 V IO3/C04661 /C0041 R6 R4 /C0467 V O /C0043 V IO2/C0426/C04661 /C0041 R3 R1 /C0467 /C0466 R7 R5 /C0041 R7 /C0467 /C04661 /C0041 R6 R4 /C0467 /C0041 R2 R1 /C0466R6 R4 /C0467/C0427 NOTE A: U1 and U2 = TL05xA; VCC ± = ±15 V. 100 kΩ U2A VI– U1A 10 kΩ 10 kΩ 200 kΩ 10 MΩ 100 kΩ 10 turn AV = 2 to 100 2 kΩ R1 U1B VI+ R5 R7 U2B 0.1 µF Offset Null VCC – 82 kΩ 82 kΩ VCC+R3 VO 10 kΩ 10 kΩ 10 MΩ 1 kΩ Figure 86. Instrumentation Amplifier

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

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high input impedance log amplifier The low input offset voltage and high input impedance of the TL05xA creates a precision log amplifier (see Figure 87). IC1 is a 2.5-V, low-current precision, shunt regulator. Transistors Q1 and Q2 must be a closely matched npn pair. For best performance over temperature, R4 should be a metal-film resistor with a low temperature coefficient. In this circuit, U1A serves as a high-impedance unity-gain buffer. Amplifier U1B converts the input voltage to a current through R1 and Q1. Amplifier U1C, IC1, and R4 form a 1-µA temperature-stable current source that sets the base-emitter voltage of Q2. U1D amplifies the difference between the base-emitter voltage of Q1 and Q2 (see Figure 88). The output voltage is given by the following equation: V O /C0043 – /C04261 /C0041 R6 R5 /C0427 kT q /C0551/C0561 /C0562 In V I /C0466R1 /C0032 1 /C0032 10–6/C0467/C0551/C0563 /C0564 where k /C0043 1.38 /C0032 10–23,q /C0043 1.602/C0032 10–19, and T is Kelvin temperature + _ U1A U1B U1C U1D VI 10 kΩ Q1 Q2 2N2484

15 V 10 kΩ

2.5 MΩ 150 pF IC1270 kΩ –15V 10 kΩ 10 kΩ VO (see equation above) NOTE A: U1A through U1D = TL05xA. IC1 = LM385, LT1004, or LT1009 voltage reference Figure 87. Log Amplifier Figure 88. Output Voltage vs Input Voltage for Log Amplifier

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003 45POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 By combining a current source that does not vary over temperature with an instrumentation amplifier, a precise analog thermometer can be built (see Figure 89). Amplifier U1A and IC1 establish a constant current through the temperature-sensing diode D1. For this section of the circuit to operate correctly, the TL05x must use split supplies, and R3 must be a metal-film resistor with a low temperature coefficient. The temperature-sensitive voltage from the diode is compared to a temperature-stable voltage reference set by IC2. R4 should be adjusted to provide the correct output voltage when the diode is at a known temperature. Although this potentiometer resistance varies with temperature, the divider ratio of the potentiometer remains constant. Amplifiers U1B, U2A, and U2B form the instrumentation amplifier that converts the difference between the diode and reference voltage to a voltage proportional to the temperature. With switch S1 closed, the amplifier gain equals 5 and the output voltage is proportional to temperature in degrees Celsius. With S1 open, the amplifier gain is 9 and the output is proportional to temperature in degrees Fahrenheit. Every time S1 is changed, R4 must be recalibrated. By setting S1 correctly, the output voltage equals 10 mV per degree (C or F). IC1 150 pF 100 kΩ U1A R3 10 kΩ (see Note B) (see Note A) +15 V R2 100 kΩ IC2 50 kΩ U1B 10 kΩ 5 kΩ 5 kΩ (see Note C) 10 kΩ U2A R10 10 kΩ R11 R9 R12 10 kΩ 10 kΩ +15 V –15 V 10 kΩ VO (see Note D) U2B NOTES: A. Temperature-sensing diode ≈ (–2 mV/°C) B. Metal-film resistor (low temperature coefficient) C. Switch open for °F and closed for °C D. V O α temperature; 10 mV/°C or 10 mV/°F E. U1, U2 = TL05x. IC1, IC2 = LM385, LT1004, or LT1009 voltage reference Figure 89. Analog Thermometer

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voltage-ratio-to-dB converter The application in Figure 90 measures the amplitude ratio of two signals, then converts the ratio to decibels (see Figure 91). The output voltage provides a resolution of 100 mV/dB. The two inputs can be either dc or sinusoidal ac signals. When using ac signals, both signals should be the same frequency or output glitches will occur. For measuring two input signals of different frequencies, extra filtering should be added after the rectifiers. The circuit contains three low-offset TL05xA devices. Two of these devices provide the rectification and logarithmic conversion of the inputs. The third TL05xA forms an instrumentation amplifier. The stage performing the logarithmic conversion also requires two well-matched npn transistors. The input signal first passes through a high-impedance unity-gain buffer U1A (U2A). Then U1B (U2B) rectifies the input signal at a gain of 0.5, and U1C (U2C) provides a noninverting gain of 2, so that the system gain is still one. U1D (U2D), R6 (R13), and Q1 (Q2) perform the logarithmic conversion of the rectified input signal. The instrumentation amplifier formed by U3A, U3B, U3D scales the difference of the two logarithmic voltages by a gain of 33.6. As a result, the output voltage equals 100 mV/dB. The 1-kΩ potentiometer on the input of U3C calibrates the zero-dB reference level. The following equations are used to derive the relationship between the input voltage ratio, expressed in decibels, and the output voltage. Xd B /C0043 20 log /C0426 V A V B /C0427 /C0043 20/C0551/C0561 /C0562 In /C0466V A/C0467 – /C0466V B/C0467 In (10) /C0551/C0563 /C0564 Xd B /C0043 8.686 /C0426In /C0466V A/C0467 – In /C0466V B/C0467/C0427 V BE(Q1) /C0043 kT q In /C0426 V A R /C0032 IS /C0427 V BE(Q2) /C0043 kT q In /C0426 V B R /C0032 IS /C0427 /C0068 V BE /C0043 V BE(Q1) –V BE(Q2) /C0043 kT q /C0426In /C0466V A/C0467 – In /C0466V B/C0467/C0427 Xd B /C0043 8.686 kT/C0324 q /C0426V BE(Q1) –V BE(Q2)/C0427 /C0043 336 /C0426V BE(Q1) –V BE(Q2)/C0427 at 25°C where k /C0043 1.38/C0032 10–23,q /C0043 1.602/C0032 10–19, and T is Kelvin temperature This gives a resolution of 1 V/dB. Therefore, the gain of the instrumentation amplifier is set at 33.6 to obtain 100 mV/dB.

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48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Macromodel information provided was derived using MicrosimParts , the model-generation software used with Microsim PSpice . The Boyle macromodel (see Note 6 and subcircuit Figure 92) are generated using the TL05x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068 Maximum positive output voltage swing /C0068 Maximum negative output voltage swing /C0068 Slew rate /C0068 Quiescent power dissipation /C0068 Input bias current /C0068 Open-loop voltage amplification /C0068 Unity-gain frequency /C0068 Common-mode rejection ratio /C0068 Phase margin /C0068 DC output resistance /C0068 AC output resistance /C0068 Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). OUT – + .SUBCKT TL05x 1 2 3 4 5 C1 11 12 3.988E –12 C2 6 7 15.00E –12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX D P 43D X FB 7 99 POLY (5) VB VC VE VLP + VLN 0 2.875E6 –3E6 3E6 3E6 –3E6 GA 6 0 11 12 292.2E –6 GCM 0 6 10 99 6.542E –9 ISS 3 10 DC 300.0E –6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3 RD1 4 11 3.422E3 RD2 4 12 3.422E3 R01 8 5 125 R02 7 99 125 RP 3 4 11.11E3 RSS 10 99 666.7E6 VB 9 0 DC 0 VC 3 53 DC 3 VE 54 4 DC 3.7 VLIM 7 8 DC 0 VLP 91 0 DC 28 VLN 0 92 DC 28 .MODEL DX D (IS=800.0E–18) .MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6 + VTO=–.1) .ENDS VCC+ RP IN– IN+ VCC – VAD RD1 J1 J2 RSS ISS RD2 VE DE DP VC DC EGND VB FB GCM GA VLIM RO1 RO2 HLIM DLP DLN VLNVLP Figure 92. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. semiconductor product to which the model relates.

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Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TL051ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL051ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL051AID OBSOLETE SOIC D 8 TBD Call TI Call TI TL051AIP OBSOLETE PDIP P 8 TBD Call TI Call TI TL051CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL051CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL051CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL051ID OBSOLETE SOIC D 8 TBD Call TI Call TI TL051IDR OBSOLETE SOIC D 8 TBD Call TI Call TI TL051IP OBSOLETE PDIP P 8 TBD Call TI Call TI TL052ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ACDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TL052AIDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052AIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052AMFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL052AMJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TL052CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CPSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052IDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL052IP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 2

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) (RoHS) TL052IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL052MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL052MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL052MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TL054ACD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ACDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ACDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ACDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ACN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054ACNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054AIDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054AIDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054AIDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054AMFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL054AMJB OBSOLETE CDIP J 14 TBD Call TI Call TI TL054CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 3

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TL054CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054CNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054CNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054IDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL054IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL054MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL054MJ OBSOLETE CDIP J 14 TBD Call TI Call TI TL054MJB OBSOLETE CDIP J 14 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 4

compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 5

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL051CDR SOIC D 8 2500 340.5 338.1 20.6 TL052ACDR SOIC D 8 2500 340.5 338.1 20.6 TL052AIDR SOIC D 8 2500 340.5 338.1 20.6 TL052CDR SOIC D 8 2500 340.5 338.1 20.6 TL052CPSR SO PS 8 2000 346.0 346.0 33.0 TL052IDR SOIC D 8 2500 340.5 338.1 20.6 TL054ACDR SOIC D 14 2500 333.2 345.9 28.6 TL054AIDR SOIC D 14 2500 333.2 345.9 28.6 TL054CDBR SSOP DB 14 2000 346.0 346.0 33.0 TL054CDR SOIC D 14 2500 333.2 345.9 28.6 TL054CNSR SO NS 14 2000 346.0 346.0 33.0 TL054IDR SOIC D 14 2500 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

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