TL031CDRG4

Texas Instruments

ENHANCED-JFET LOW-POWER LOW-OFFSET

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TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Direct Upgrades for the TL06x Low-Power BiFETs /C0068Low Power Consumption... 6.5 mW/Channel Typ /C0068On-Chip Offset-Voltage Trimming for Improved DC Performance (1.5 mV, TL031A) /C0068Higher Slew Rate and Bandwidth Without Increased Power Consumption /C0068Available in TSSOP for Small Form-Factor Designs

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The TL03x series of JFET-input operational amplifiers offer improved dc and ac characteristics over the TL06x family of low-power BiFET operational amplifiers. On-chip zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL031A) for greater accuracy in dc-coupled applications. The Texas Instruments improved BiFET process and optimized designs also yield improved bandwidths and slew rates without increased power consumption. The TL03x devices are pin-compatible with the TL06x and can be used to upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors without sacrificing the output drive associated with bipolar amplifiers. This higher input impedance makes the TL3x amplifiers better suited for interfacing with high-impedance sensors or very low-level ac signals. These devices also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL03x family has been optimized for micropower operation, while improving on the performance of the TL06x series. Designers requiring significantly faster ac response should consider the Excalibur ™ TLE206x family of low-power BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input-voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at midsupply. The TI TLE2426 integrated virtual-ground generator is useful when operating BiFET amplifiers from single supplies. The TL03x devices are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, the TI LinCMOS families of operational amplifiers (TLC prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to slew rate, bandwidth requirements, and output loading. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40 °C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to 125°C. Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Excalibur is a trademark of Texas Instruments.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IN− IN+ VCC− NC V CC+ OUT OFFSET N2 3212 0 1 9 91 0 1 1 1 2 1 3 NC VCC+ NC OUT NC NC IN− NC IN+ NC NC OFFSET N1 NC NC NC NC OFFSET N2 NC NC V CC− TL031x, TL031Ax D, JG, OR P PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VCC − VCC+ 2OUT 2IN− 2IN+ 3212 0 1 9 91 0 1 1 1 2 1 3 NC 2OUT NC 2IN− NC NC 1IN− NC 1IN+ NC NC 1OUT NC NC NC NC 2IN+ NC CC−V CC+V TL031M, TL031AM FK PACKAGE (TOP VIEW) TL032M, TL032AM FK PACKAGE (TOP VIEW) TL032x, TL032Ax D, JG, OR P PACKAGE (TOP VIEW) 3212 0 1 9 91 0 1 1 1 2 1 3 4IN+ NC V CC− NC 3IN+ 1IN+ NC V CC+ NC 2IN+ 1IN− 1OUT NC 3IN− 2IN− NC 3OUT 4OUT 4IN− 2OUT 1OUT 1IN− 1IN+ VCC+ 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ VCC− 3IN+ 3IN− 3OUT TL034x, TL034Ax D, J, N, OR PW PACKAGE (TOP VIEW) TL034M, TL034AM FK PACKAGE (TOP VIEW) NC − No internal connection

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOMAX AT 25°C SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (J) CERAMIC DIP (JG) PLASTIC DIP (N) PLASTIC DIP (P) TSSOP (PW) 0.8 mV TL031ACD TL032ACD — — — — TL031ACP TL032ACP 0°C to 70°C 1.5 mV TL031CD TL032CD TL034ACD — — — TL034ACN TL031CP TL032CP — 4 mV TL034CD — — — TL034CN — TL034CPW 0.8 mV TL031AID TL032AID — — — — TL031AIP TL032AIP −40°C to 85°C 1.5 mV TL031ID TL032ID TL034AID — — — TL034AIN TL031IP TL032IP — 4 mV TL034ID — — — TL034IN — — 0.8 mV TL031AMD TL032AMD TL031AMFK TL032AMFK — TL031AMJG TL032AMJG — TL031AMP TL032AMP −55°C to 125°C 1.5 mV TL031MD TL032MD TL034AMD TL031MFK TL032MFK TL034AMFK TL034AMJ TL031MJG TL032MJG TL034AMN TL031MP TL032MP 4 mV TL034MD TL034MFK TL034MJ — TL034MN — — The D and PW packages are available taped and reeled and are indicated by adding an R suffix to device type (e.g., TL034CDR or TL034CPWR).

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

symbol (each amplifier) OUT IN− IN+ equivalent schematic (each amplifier) OFFSET N2 OFFSET N1 IN− IN+ VCC+ Q14 Q8 Q10 R7 Q11 Q12 R5R1 JF1 JF2 Q13 Q16 JF3 JF4 Q15 Q17 OUT VCC− NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL031, TL031A. See Note A

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V CC+ and VCC−. 2. Differential voltages are at IN+ with respect to IN−. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. 5. The package thermal impedance is calculated in accordance with JESD 51-7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW recommended operating conditions C SUFFIX I SUFFIX M SUFFIX UNITMIN MAX MIN MAX MIN MAX UNIT VCC± Supply voltage ±5 ±15 ±5 ±15 ±5 ±15 V V Common mode input voltage VVIC Common-mode input voltage VCC± = ±15 V −11.5 14 −11.5 14 −11.5 14 V TA Operating free-air temperature 0 70 −40 85 −55 125 °C

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031C and TL031AC electrical characteristics at specified free-air temperature TL031C, TL031AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL031C 25°C 0.54 3.5 0.5 1.5 V Input offset voltage VO = 0, V 0 TL031C Full range† 4.5 2.5 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL031AC 25°C 0.41 2.8 0.34 0.8 mV RS = 50 Ω TL031AC Full range† 3.8 1.8 TL031C 25°C to 71 59 /C0097 Temperature coefficient of VO = 0, V 0 TL031C 25 C to 70°C 7.1 5.9 V/°C/C0097VIO Temperature coefficient of input offset voltage VIC =0, RS = 50 Ω TL031AC 25°C to 71 59 25 μV/°Cinput offset voltage RS = 50 Ω TL031AC 25 C to 70°C 7.1 5.9 25 Input offset voltage long-term drift‡ VO = 0, VIC =0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pAIIO Input offset current VO = 0, VIC = 0 See Figure 5 70°C 9 200 12 200 pA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pAIIB Input bias current VO = 0, VIC = 0 See Figure 5 70°C 50 400 80 400 pA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ 0°C 3 4.2 13 14 VVOM+ output voltage swing RL 10 kΩ 70°C 3 4.3 13 14 V Mi t i k VOM− Maximum negative peak output voltage swing RL = 10 kΩ 0°C −3 −4.1 −12.5 −13.9 VVOM− output voltage swing RL 10 kΩ V 25°C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ 0°C 3 11.1 4 13.5 V/mVAVD voltage amplification§ RL 10 kΩ 70°C 4 13.3 5 15.2 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω 0°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω 70°C 70 87 75 94 dB Supply-voltage 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, RS = 50 Ω 0°C 75 96 75 96 dBSVR rejection ratio (ΔVCC±/ΔVIO) O , S 70°C 75 96 75 96 † Full range is 0°C to 70°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL031C and TL031AC electrical characteristics at specified free-air temperature (continued) TL031C, TL031AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT 25°C 1.9 2.5 6.5 8.4 PD Total power dissipation V O = 0, No load 0°C 1.8 2.5 6.3 8.4 mWPD Total power dissipation VO 0, No load 70°C 1.9 2.5 6.3 8.4 mW 25°C 192 250 217 280 ICC Supply current V O = 0, No load 0°C 184 250 211 280 μACC pp y O , 70°C 189 250 210 280 μ TL031C and TL031AC operating characteristics at specified free-air temperature TL031C, TL031AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 0°C 1.8 1 2.6 V/μsSR+ unity gain† See Figure 1 70°C 2.2 1.5 3.2 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 0°C 3.7 1.5 5 V/μsSR unity gain† See Figure 1 70°C 4 1.5 5 V/μs VI(PP) = ±10 mV, 25°C 138 132 tr Rise time VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 150 142 ns VI(PP) = ±10 mV, 25°C 138 132 tf Fall time VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 70°C 150 142 ns VI(PP) = ±10 mV, 25°C 11% 5% Overshoot factor VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF 0°C 10% 4%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 12% 6% TL031C f = 10 Hz 25°C 61 61 V Equivalent input TL031C RS = 20 Ω f = 1 kHz 25°C 41 41 nV/√HVn Equivalent input noise voltage TL031AC RS = 20 Ω See Figure 3 f = 10 Hz 25°C 61 61 nV/√Hzg TL031AC f = 1 kHz 25°C 41 41 60 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 70°C 1 1 MHz VI = 10 mV 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV RL = 10 kΩ, CL = 25 pF 0°C 61° 65°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 70°C 60° 64° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031I and TL031AI electrical characteristics at specified free-air temperature TL031I, TL031AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL031I 25°C 0.54 3.5 0.5 1.5 V Input offset voltage VO = 0, V 0 TL031I Full range† 5.3 3.3 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL031AI 25°C 0.41 2.8 0.34 0.8 mV RS = 50 Ω TL031AI Full range† 4.6 2.6 TL031I 25°C to 65 62 /C0097 Temperature coefficient f VO = 0, V 0 TL031I 25 C to 85°C 6.5 6.2 V/°C/C0097VIO of input offset voltage VIC = 0, RS = 50 Ω TL031AI 25°C to 65 62 25 μV/°C input offset voltage RS = 50 Ω TL031AI 25 C to 85°C 6.5 6.2 25 Input offset voltage VO = 0, V 0 25°C 00 4 00 4 V/moInput offset voltage long-term drift‡ VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pA IIO Input offset current VO = 0, VIC = 0 See Figure 5 85°C 0.02 0.45 0.02 0.45 nA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pA IIB Input bias current VO = 0, VIC = 0 See Figure 5 85°C 0.2 0.9 0.2 0.9 nA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ −40°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ 85°C 3 4.4 13 14 V Mi t i k VOM− Maximum negative peak output voltage swing RL = 10 kΩ −40°C −3 −4.1 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ V 25°C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ −40°C 3 8.4 4 11.6 V/mVAVD voltage amplification§ RL 10 kΩ 85°C 4 13.5 5 15.3 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω −40°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω 85°C 70 87 75 94 dB Supply-voltage 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, RS = 50 Ω −40°C 75 96 75 96 dBSVR rejection ratio (ΔVCC±/ΔVIO) O , S 85°C 75 96 75 96 † Full range is −40°C to 85°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL031I and TL031AI electrical characteristics at specified free-air temperature (continued) TL031I, TL031AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT 25°C 1.9 2.5 6.5 8.4 PD Total power dissipation V O = 0, No load −40°C 1.4 2.5 5.4 8.4 mWPD Total power dissipation VO 0, No load 85°C 1.9 2.5 6.2 8.4 mW 25°C 192 250 217 280 ICC Supply current V O = 0, No load −40°C 144 250 181 280 μACC pp y O , 85°C 189 250 207 280 μ TL031I and TL031AI operating characteristics at specified free-air temperature TL031I, TL031AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −40°C 1.6 1 2.1 V/μsSR+ unity gain† See Figure 1 85°C 2.3 1.5 3.3 V/μs N t i l tti t R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −40°C 3.3 1.5 4.8 V/μsSR gain† See Figure 1 85°C 4.1 1.5 4.9 V/μs VI(PP) = ±10 mV, 25°C 138 132 tr Rise time VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 154 146 ns VI(PP) = ±10 mV, 25°C 138 132 tf Fall time VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 85°C 154 146 ns VI(PP) = ±10 mV, 25°C 11% 5% Overshoot factor VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF −40°C 12% 5%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 13% 7% TL031I f = 10 Hz 25°C 61 61 V Equivalent it TL031I RS = 20 Ω f = 1 kHz 25°C 41 41 nV/√HVn input noise voltage TL031AI RS = 20 Ω See Figure 3 f = 10 Hz 25°C 61 61 nV/√Hz noise voltage TL031AI f = 1 kHz 25°C 41 41 60 I Equivalent input noise f 1 kHz 25°C 0 003 0 003 pA/√HIn Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 85°C 0.9 1 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF −40°C 60° 65°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 85°C 60° 64° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL031M and TL031AM electrical characteristics at specified free-air temperature TL031M, TL031AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL031M 25°C 0.54 3.5 0.5 1.5 V Input offset voltage VO = 0, V 0 TL031M Full range† 6.5 4.5 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL031AM 25°C 0.41 2.8 0.34 0.8 mV RS = 50 Ω TL031AM Full range† 5.8 3.8 /C0097 Temperature coefficient of VO = 0, V 0 TL031M 25°C to 125°C 5.1 4.3 V/°C/C0097VIO Temperature coefficient of input offset voltage VIC = 0, RS = 50 Ω TL031AM 25°C to 125°C 5.1 4.3 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pA IIO Input offset current VO = 0, VIC = 0 See Figure 5 125°C 0.2 10 0.2 10 nA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pA IIB Input bias current VO = 0, VIC = 0 See Figure 5 125°C 7 20 8 20 nA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ −55°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ 125°C 3 4.4 13 14 V Mi t i k VOM− Maximum negative peak output voltage swing RL = 10 kΩ −55°C −3 −4 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ V 25°C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ −55°C 3 7.1 4 10.4 V/mVAVD voltage amplification§ RL 10 kΩ 125°C 3 12.9 4 15 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω −55°C 70 87 70 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω 125°C 70 87 70 94 dB Supply-voltage 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, RS = 50 Ω −55°C 75 96 75 95 dBkSVR rejection ratio (ΔVCC±/ΔVIO) VO 0, RS 50 Ω 125°C 75 96 75 96 dB 25°C 1.9 2.5 6.5 8.4 PD Total power dissipation V O = 0, No load −55°C 1.1 2.5 4.7 8.4 mWD pp O , 125°C 1.8 2.5 5.8 8.4 † Full range is −55°C to 125°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL031M and TL031AM electrical characteristics at specified free-air temperature (continued) TL031M, TL031AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT 25°C 192 250 217 280 ICC Supply current V O = 0, No load −55°C 114 250 156 280 μACC pp y O , 125°C 178 250 197 280 μ TL031M and TL031AM operating characteristics at specified free-air temperature TL031M, TL031AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −55°C 1.4 1 1.9 V/μsSR+ unity gain† See Figure 1 125°C 2.4 1 3.5 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −55°C 3.2 1 4.6 V/μsSR unity gain† See Figure 1 125°C 4.1 1 4.7 V/μs VI(PP) = ±10 mV, 25°C 138 132 tr Rise time VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 125°C 166 158 ns VI(PP) = ±10 mV, 25°C 138 132 tf Fall time VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 125°C 166 158 ns VI(PP) = ±10 mV, 25°C 11% 5% Overshoot factor VI(PP) = ±10 mV, RL = 10 kΩ, CL = 100 pF −55°C 16% 6%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 125°C 14% 8% TL031M f = 10 Hz 25°C 61 61 V Equivalent input TL031M RS = 20 Ω f = 1 kHz 25°C 41 41 nV/√HVn Equivalent input noise voltage TL031AM RS = 20 Ω See Figure 3 f = 10 Hz 25°C 61 61 nV/√Hz TL031AM f = 1 kHz 25°C 41 41 I Equivalent input noise f 1 kHz 25°C 0 003 0 003 pA/√HIn Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV, 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV, RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 125°C 0.9 0.9 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF −55°C 57° 64°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 125°C 59° 62° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032C and TL032AC electrical characteristics at specified free-air temperature TL032C, TL032AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL032C 25°C 0.69 3.5 0.57 1.5 V Input offset voltage VO = 0, V 0 TL032C Full range† 4.5 2.5 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL032AC 25°C 0.53 2.8 0.39 0.8 mV RS = 50 Ω TL032AC Full range† 3.8 1.8 /C0097V Temperature ffi i t f i t VO = 0, V 0 TL032C 25°C to 70°C 11.5 10.8 V/°C/C0097VIO coefficient of input offset voltage VIC = 0, RS = 50 Ω TL032AC 25°C to 70°C 11.5 10.8 25 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pAIIO Input offset current VO = 0, See Figure 5 VIC = 0 70°C 9 200 12 200 pA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pAIIB Input bias current VO = 0, See Figure 5 VIC = 0 70°C 50 400 80 400 pA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V Maximum positive 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage RL = 10 kΩ 0°C 3 4.2 13 14 VVOM+ peak output voltage swing RL 10 kΩ 70°C 3 4.3 13 14 V Maximum negative 25°C −3 −4.2 −12.5 −13.9 VOM− Maximum negative peak output voltage RL = 10 kΩ 0°C −3 −4.1 −12.5 −13.9 VVOM− peak output voltage swing RL 10 kΩ V Large-signal 25°C 4 12 5 14.3 AVD Large-signal differential voltage RL = 10 kΩ 0°C 3 11.1 4 13.5 V/mVAVD differential voltage amplification§ RL 10 kΩ 70°C 4 13.3 5 15.2 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 14 pF Cd V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω 0°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω 70°C 70 87 75 94 dB Supply-voltage V ±5Vt ±15 V 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, VO =0 R S =5 0 Ω 0°C 75 96 75 96 dBSVR rejection ratio (ΔVCC±/ΔVIO) VO = 0, RS = 50 Ω 70°C 75 96 75 96 † Full range is 0°C to 70°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL032C and TL032AC electrical characteristics at specified free-air temperature (continued) TL032C, TL032AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT Ttl d i i t i 25°C 3.8 5 13 17 PD Total power dissipation (two amplifiers) VO = 0, No load 0°C 3.7 5 12.7 17 mWPD (two amplifiers) VO 0, No load 70°C 3.8 5 12.6 17 mW I Supply current V 0 No load 0°C 368 500 422 560 AICC Supply current (two amplifiers) VO = 0, No load 70°C 378 500 420 560 μA VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB TL032C and TL032AC operating characteristics at specified free-air temperature TL032C, TL032AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITA MIN TYP MAX MIN TYP MAX R 10 kΩ C 100 F 25°C 1.2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 0°C 1.8 1 2.6 V/μsSR+ gain† See Figure 1 70°C 2.2 1.5 3.2 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 0°C 3.7 1.5 5 V/μsSR gain† See Figure 1 70°C 4 1.5 5 V/μs VI(PP) = ±10 V, 25°C 138 132 tr Rise time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 150 142 ns VI(PP) = ±10 V, 25°C 138 132 tf Fall time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstf Fall time RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 150 142 ns Overshoot factor VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF 0°C 10% 4%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 12% 6% TL032C f = 10 Hz 25°C 49 49 V Equivalent input TL032C RS = 20 Ω f = 1 kHz 25°C 41 41 nV/√HzVn Equivalent input noise voltage TL032AC RS = 20 Ω See Figure 3 f = 10 Hz 25°C 49 49 nV/√Hzg TL032AC f = 1 kHz 25°C 41 41 60 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV, 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV, RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 70°C 1 1 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF 0°C 61° 65°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 70°C 60° 64° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032I and TL032AI electrical characteristics at specified free-air temperature TL032I, TL032AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL032I 25°C 0.69 3.5 0.57 1.5 V Input offset voltage VO = 0, V 0 TL032I Full range† 5.3 3.3 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL032AI 25°C 0.53 2.8 0.39 0.8 mV RS = 50 Ω TL032AI Full range† 4.6 2.6 /C0097V Temperature ffi i t f i t VO = 0, V 0 TL032I 25°C to 85°C 11.4 10.8 V/°C/C0097VIO coefficient of input offset voltage VIC = 0, RS = 50 Ω TL032AI 25°C to 85°C 11.4 10.8 25 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pA IIO Input offset current VO = 0, See Figure 5 VIC = 0 85°C 0.02 0.45 0.02 0.45 nA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pA IIB Input bias current VO = 0, See Figure 5 VIC = 0 85°C 0.2 0.9 0.3 0.9 nA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V Maximum positive 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage RL = 10 kΩ −40°C 3 4.2 13 14 VVOM+ peak output voltage swing RL 10 kΩ 85°C 3 4.4 13 14 V Maximum negative 25°C −3 −4.2 −12.5 −13.9 VOM− Maximum negative peak output voltage RL = 10 kΩ −40°C −3 −4.1 −12.5 −13.8 VVOM− peak output voltage swing RL 10 kΩ V A Large-signal differential R 10 kΩ −40°C 3 8.4 4 11.6 V/mVAVD Large-signal differential voltage amplification§ RL = 10 kΩ 85°C 4 13.5 5 15.3 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω −40°C 70 87 75 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω 85°C 70 87 75 94 dB Supply-voltage V ±5Vt ±15 V 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, VO =0 R S =5 0 Ω −40°C 75 96 75 96 dBSVR rejection ratio (ΔVCC±/ΔVIO) VO = 0, RS = 50 Ω 85°C 75 96 75 96 † Full range is −40°C to 85°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL032I and TL032AI electrical characteristics at specified free-air temperature (continued) TL032I, TL032AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT Total power 25°C 3.8 5 13 17 PD Total power dissipation VO = 0, No load −40°C 2.9 5 10.9 17 mWPD dissipation (two amplifiers) VO 0, No load 85°C 3.7 5 12.4 17 mW Sl t 25°C 384 500 434 560 ICC Supply current (two amplifiers) VO = 0, No load −40°C 288 500 362 560 μAICC (two amplifiers) VO 0, No load 85°C 372 500 414 560 μA VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB TL032I and TL032AI operating characteristics at specified free-air temperature TL032I, TL032AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF −40°C 1.6 1 2.1 V/μsSR+ gain† RL 10 kΩ, CL 100 pF 85°C 2.3 1.5 3.3 V/μs 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF −40°C 3.3 1.5 4.8 V/μsSR gain† RL 10 kΩ, CL 100 pF 85°C 4.1 1.5 4.9 V/μs VI(PP) = ±10 V, 25°C 138 132 tr Rise time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 154 146 ns VI(PP) = ±10 V, 25°C 138 132 tf Fall time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 85°C 154 146 ns Overshoot factor VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −40°C 12% 5%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 13% 7% TL032I f = 10 Hz 25°C 49 49 V Equivalent input TL032I RS = 20 Ω f = 1 kHz 25°C 41 41 nV/√HzVn Equivalent input noise voltage TL032AI RS = 20 Ω See Figure 3 f = 10 Hz 25°C 49 49 nV/√Hzg TL032AI f = 1 kHz 25°C 41 41 60 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV, 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV, RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 85°C 0.9 1 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF −40°C 61° 65°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 85°C 60° 64° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL032M and TL032AM electrical characteristics at specified free-air temperature TL032M, TL032AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL032M 25°C 0.69 3.5 0.57 1.5 V Input offset voltage VO = 0, V 0 TL032M Full range† 6.5 4.5 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL032AM 25°C 0.53 2.8 0.39 0.8 mV RS = 50 Ω TL032AM Full range† 5.8 3.8 /C0097 Temperature coefficient VO = 0, V 0 TL032M 25°C to 125°C 9.7 9.7 V/°C/C0097VIO Temperature coefficient of input offset voltage VIC = 0, RS = 50 Ω TL032AM 25°C to 125°C 9.7 9.7 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pA IIO Input offset current VO = 0, See Figure 5 VIC = 0 125°C 0.2 10 0.2 10 nA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pA IIB Input bias current VO = 0, See Figure 5 VIC = 0 125°C 7 20 8 20 nA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ −55°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ 125°C 3 4.4 13 14 V Mi t i k VOM− Maximum negative peak output voltage swing RL = 10 kΩ −55°C −3 −4 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ V 25°C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ −55°C 3 7.1 4 10.4 V/mVAVD voltage amplification§ RL 10 kΩ 125°C 3 12.9 4 15 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd j t i V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω −55°C 70 87 70 94 dBCMRR ratio VO = 0, RS = 50 Ω 125°C 70 87 70 94 dB Supply-voltage V ±5Vt ±15 V 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VCC± = ±5 V to ±15 V, VO =0 R S =5 0 Ω −55°C 75 95 75 95 dBSVR rejection ratio (ΔVCC±/ΔVIO) VO = 0, RS = 50 Ω 125°C 75 96 75 96 † Full range is −55°C to 125°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = 2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL032M and TL032AM electrical characteristics at specified free-air temperature (continued) TL032M, TL032AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT Total power dissipation 25°C 3.8 5 13 17 PD Total power dissipation (two amplifiers) VO = 0, No load −55°C 2.3 5 9.4 17 mWPD (two amplifiers) VO = 0, VO 0, No load 125°C 3.6 5 11.8 17 mW Sl t 25°C 384 500 434 560 ICC Supply current (two amplifiers) VO = 0, No load −55°C 228 500 312 560 μAICC (two amplifiers) VO 0, No load 125°C 356 500 394 560 μA VO1/VO2 Crosstalk attenuation AVD = 100 dB 25°C 120 120 dB TL032M and TL032AM operating characteristics at specified free-air temperature TL032M, TL032AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See and Figure 1 −55°C 1.4 1 1.9 V/μsSR+ gain† See and Figure 1 125°C 2.4 1 3.5 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See and Figure 1 −55°C 3.2 1 4.6 V/μsSR gain† See and Figure 1 125°C 4.1 1 4.7 V/μs VI(PP) = ±10 V, 25°C 138 132 tr Rise time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 125°C 166 58 ns VI(PP) = ±10 V, 25°C 138 132 tf Fall time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 125°C 166 158 ns Overshoot factor VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −55°C 16% 6%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 125°C 14% 8% TL032M f = 10 Hz 25°C 49 49 V Equivalent input noise TL032M RS = 20 Ω f = 1 kHz 25°C 41 41 nV/√HzVn input noise voltage TL032AM RS = 20 Ω See Figure 3 f = 10 Hz 25°C 49 49 nV/√Hz voltage TL032AM f = 1 kHz 25°C 41 41 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV, 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV, RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 125°C 0.9 0.9 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF −55°C 57° 64°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 125°C 59° 62° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034C and TL034AC electrical characteristics at specified free-air temperature TL034C, TL034AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL034C 25°C 0.91 6 0.79 4 V Input offset voltage VO = 0, V 0 TL034C Full range† 8.2 6.2 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL034AC 25°C 0.7 3.5 0.58 1.5 mV RS = 50 Ω TL034AC Full range† 5.7 3.7 /C0097 Temperature coefficient VO = 0, V 0 TL034C 25°C to 70°C 11.6 12 V/°C/C0097VIO Temperature coefficient of input offset voltage VIC = 0, RS = 50 Ω TL034AC 25°C to 70°C 11.6 12 25 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pAIIO Input offset current VO = 0, VIC = 0 See Figure 5 70°C 9 200 12 200 pA I Input bias current VO = 0, V IC = 0 25°C 2 200 2 200 pAIIB Input bias current VO = 0, VIC = 0 See Figure 5 70°C 50 400 80 400 pA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ 0°C 3 4.2 13 14 VVOM+ output voltage swing RL 10 kΩ 70°C 3 4.3 13 14 V Mi t i k VOM− Maximum negative peak output voltage swing RL = 10 kΩ 0°C −3 −4.1 −12.5 −13.9 VVOM− output voltage swing RL 10 kΩ V 25°C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ 0°C 3 11.1 4 13.5 V/mVAVD voltage amplification§ RL 10 kΩ 70°C 4 13.3 5 15.2 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 14 pF Cd VIC = VICRmin, 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, 0°C 70 87 75 94 dBCMRR rejection ratio VO 0, RS = 50 Ω 70°C 70 87 75 94 dB Supply-voltage 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, R S = 50 Ω 0°C 75 96 75 96 dBSVR rejection ratio (ΔVCC±/ΔVIO) O , S 70°C 75 96 75 96 † Full range is 0°C to 70°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL034C and TL034AC electrical characteristics at specified free-air temperature (continued) TL034C, TL034AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT Ttl d i i t i 25°C 7.7 10 26 34 PD Total power dissipation (two amplifiers) VO = 0, No load 0°C 7.4 10 25.3 34 mWPD (two amplifiers) VO 0, No load 70°C 7.6 10 25.2 34 mW Sl t ( f 25°C 0.77 1 0.87 1.12 ICC Supply current (four amplifiers) VO = 0, No load 0°C 0.74 1 0.85 1.12 mAICC amplifiers) VO 0, No load 70°C 0.76 1 0.84 1.12 mA VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL034C and TL034AC operating characteristics at specified free-air temperature TL034C, TL034AC PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 0°C 1.8 1 2.6 V/μsSR+ gain† See Figure 1 70°C 2.2 1.5 3.2 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 0°C 3.7 1.5 5 V/μsSR gain† See Figure 1 70°C 4 1.5 5 V/μs VI(PP) = ±10 V, 25°C 138 132 tr Rise time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 150 142 ns VI(PP) = ±10 V, 25°C 138 132 tf Fall time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF 0°C 134 127 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 70°C 150 142 ns Overshoot factor VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF 0°C 10% 4%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 70°C 12% 6% TL034C f = 10 Hz 25°C 83 83 V Equivalent input TL034C RS = 20 Ω f = 1 kHz 25°C 43 43 nV/√HzVn Equivalent input noise voltage TL034AC RS = 20 Ω See Figure 3 f = 10 Hz 25°C 83 83 nV/√Hzg TL034AC f = 1 kHz 25°C 43 43 60 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV RL = 10 kΩ, CL = 25 pF 0°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 70°C 1 1 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF 0°C 61° 65°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 70°C 60° 64° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034I and TL034AI electrical characteristics at specified free-air temperature TL034I, TL034AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL034I 25°C 0.91 3.6 0.79 4 V Input offset voltage VO = 0, V 0 TL034I Full range† 9.3 7.3 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL034AI 25°C 0.7 3.5 0.58 1.5 mV RS = 50 Ω TL034AI Full range† 6.8 4.8 /C0097 Temperature coefficient VO = 0, VIC TL034I 25°C to 85°C 11.5 11.6 V/°C/C0097VIO Temperature coefficient of input offset voltage = 0, RS = 50 Ω TL034AI 25°C to 85°C 11.5 11.6 25 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pA IIO Input offset current VO = 0, VIC = 0 See Figure 5 85°C 0.02 0.45 0.02 0.45 nA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pA IIB Input bias current VO = 0, VIC = 0 See Figure 5 85°C 0.2 0.9 0.3 0.9 nA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ −40°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ 85°C 3 4.4 13 14 V Maximum negative 25°C −3 −4.2 −12.5 −13.9 VOM− Maximum negative peak RL = 10 kΩ −40°C −3 −4.1 −12.5 −13.8 VVOM− peak output voltage swing RL 10 kΩ V A Large-signal differential R 10 kΩ −40°C 4 12 5 14.3 V/mVAVD Large-signal differential voltage amplification§ RL = 10 kΩ 85°C 3 8.4 4 11.6 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd VIC = VICRmin, 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, −40°C 70 87 75 94 dBCMRR rejection ratio VO 0, RS = 50 Ω 85°C 70 87 75 94 dB Supply-voltage 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, RS = 50 Ω −40°C 75 96 75 96 dBSVR rejection ratio (ΔVCC±/ ΔVIO) O , S 85°C 75 96 75 96 † Full range is −40°C to 85°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL034I and TL034AI electrical characteristics at specified free-air temperature (continued) TL034I, TL034AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT Ttl d i i t i 25°C 7.7 10 26 34 PD Total power dissipation (four amplifiers) VO = 0, No load −40°C 5.8 10 21.7 34 mWPD (four amplifiers) VO 0, No load 85°C 7.4 10 24.8 34 mW Sl t 25°C 0.77 1 0.87 1.12 ICC Supply current (four amplifiers) VO = 0, No load −40°C 0.58 1 0.72 1.12 mAICC (four amplifiers) VO 0, No load 85°C 0.74 1 0.83 1.12 mA VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL034I and TL034AI operating characteristics TL034I, TL034AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −40°C 1.6 1 2.1 V/μsSR+ gain† See Figure 1 85°C 2.3 1.5 3.3 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −40°C 3.3 1.5 4.8 V/μsSR gain† See Figure 1 85°C 4.1 1.5 4.9 V/μs VI(PP) = ±10 V, 25°C 138 132 tr Rise time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 154 146 ns VI(PP) = ±10 V, 25°C 138 132 tf Fall time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −40°C 132 123 nstf Fall time RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 154 146 ns Overshoot factor VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −40°C 12% 5%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 85°C 13% 7% TL034I f = 10 Hz 25°C 83 83 V Equivalent input TL034I RS = 20 Ω f = 1 kHz 25°C 43 43 nV/√HzVn Equivalent input noise voltage TL034AI RS = 20 Ω See Figure 3 f = 10 Hz 25°C 83 83 nV/√Hzg TL034AI f = 1 kHz 25°C 43 43 60 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV, 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV, RL = 10 kΩ, CL = 25 pF −40°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 85°C 0.9 1 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF −40°C 61° 65°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 85°C 60° 64° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL034M and TL034AM electrical characteristics at specified free-air temperature TL034M, TL034AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL034M 25°C 0.91 3.6 0.78 4 V Input offset voltage VO = 0, V 0 TL034M Full range† 11 9 mVVIO Input offset voltage VIC = 0, RS = 50 Ω TL034AM 25°C 0.7 3.5 0.58 1.5 mV RS = 50 Ω TL034AM Full range† 8.5 6.5 /C0097 Temperature coefficient of VO = 0, V 0 TL034M 25°C to 125°C 10.6 10.9 V/°C/C0097VIO Temperature coefficient of input offset voltage VIC = 0, RS = 50 Ω TL034AM 25°C to 125°C 10.6 10.9 μV/°C Input offset voltage long-term drift‡ VO = 0, VIC = 0, RS = 50 Ω 25°C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25°C 1 100 1 100 pA IIO Input offset current VO = 0, VIC = 0 See Figure 5 125°C 0.2 10 0.2 10 nA I Input bias current VO = 0, VIC = 0 25°C 2 200 2 200 pA IIB Input bias current VO = 0, VIC = 0 See Figure 5 125°C 7 20 8 20 nA V Common-mode input 25°C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 VVICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25°C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ −55°C 3 4.1 13 14 VVOM+ output voltage swing RL 10 kΩ 125°C 3 4.4 13 14 V Mi t i k VOM− Maximum negative peak output voltage swing RL = 10 kΩ −55°C −3 −4 −12.5 −13.8 VVOM− output voltage swing RL 10 kΩ V 25°C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ −55°C 3 7.1 4 10.4 V/mVAVD voltage amplification§ RL 10 kΩ 125°C 3 12.9 4 15 V/mV ri Input resistance 25°C 1012 1012 Ω ci Input capacitance 25°C 5 4 pF Cd V V i 25°C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 R S =5 0 Ω −55°C 70 87 70 94 dBCMRR rejection ratio VO = 0, RS = 50 Ω 125°C 70 87 70 94 dB Supply-voltage 25°C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, RS = 50 Ω −55°C 75 95 75 95 dBSVR rejection ratio (ΔVCC±/ΔVIO) O , S 125°C 75 96 75 96 † Full range is −55°C to 125°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150 °C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL034M and TL034AM electrical characteristics at specified free-air temperature (continued) TL034M, TL034AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT Ttl d i i t i 25°C 7.7 10 26 34 PD Total power dissipation (two amplifiers) VO = 0, No load −55°C 4.6 12 18.7 45 mWPD (two amplifiers) VO 0, No load 125°C 7.1 12 23.6 45 mW Sl t 25°C 0.77 1 0.87 1.12 ICC Supply current (two amplifiers) VO = 0, No load −55°C 0.46 1.2 0.62 1.5 mAICC (two amplifiers) VO 0, No load 125°C 0.71 1.2 0.79 1.5 mA VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB TL034M and TL034AM operating characteristics at specified free-air temperature TL034M, TL034AM PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNITPARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT R 10 kΩ C 100 F 25°C 2 1.5 2.9 SR+ Positive slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −55°C 1.4 1 1.9 V/μsSR+ gain† See Figure 1 125°C 2.4 1 3.5 V/μs R 10 kΩ C 100 F 25°C 3.9 1.5 5.1 SR− Negative slew rate at unity gain† RL = 10 kΩ, CL = 100 pF See Figure 1 −55°C 3.2 1 4.6 V/μsSR gain† See Figure 1 125°C 4.1 1 4.7 V/μs VI(PP) = ±10 V, 25°C 138 132 tr Rise time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstr Rise time RL 10 kΩ, CL 100 pF See Figures 1 and 2 125°C 166 58 ns VI(PP) = ±10 V, 25°C 138 132 tf Fall time VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −55°C 142 123 nstf Fall time RL 10 kΩ, CL 100 pF See Figure 1 125°C 166 158 ns Overshoot factor VI(PP) = ±10 V, RL = 10 kΩ, CL = 100 pF −55°C 16% 6%Overshoot factor RL 10 kΩ, CL 100 pF See Figures 1 and 2 125°C 14% 8% TL034M f = 10 Hz 25°C 83 83 V Equivalent input TL034M RS = 20 Ω f = 1 kHz 25°C 43 43 nV/√HzVn Equivalent input noise voltage TL034AM RS = 20 Ω See Figure 3 f = 10 Hz 25°C 83 83 nV/√Hz TL034AM f = 1 kHz 25°C 43 43 In Equivalent input noise current f = 1 kHz 25°C 0.003 0.003 pA/√Hz VI = 10 mV, 25°C 1 1.1 B1 Unity-gain bandwidth VI = 10 mV, RL = 10 kΩ, CL = 25 pF −55°C 1 1.1 MHzB1 Unity gain bandwidth RL 10 kΩ, CL 25 pF See Figure 4 125°C 0.9 0.9 MHz VI = 10 mV, 25°C 61° 65° φm Phase margin at unity gain VI = 10 mV, RL = 10 kΩ, CL = 25 pF −55°C 57° 64°φm gy g RL 10 kΩ, CL 25 pF See Figure 4 125°C 59° 62° † For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 1. Slew-Rate and Overshoot Test Circuit NOTE A: CL includes fixture capacitance. Figure 2. Rise Time and Overshoot Waveform Figure 3. Noise-Voltage Test Circuit Figure 4. Unity-Gain Bandwidth and NOTE A: CL includes fixture capacitance. Figure 5. Input-Bias and Offset-Current Test Circuit

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION typical values Typical values presented in this data sheet represent the median (50% point) of device parametric performance. input bias and offset current At the picoampere bias current level typical of the TL03x and TL03xA, accurate measurement of the bias current becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied but with no device in the socket. The device is then inserted into the socket and a second test that measures both the socket leakage and the device input bias current is performed. The two measurements are then subtracted algebraically to determine the bias current of the device. noise With the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage density is performed at f = 1 kHz, unless otherwise noted.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Distribution of TL03x input offset voltage 6−11 Distribution of TL03x input offset-voltage temperature coefficient 12−14 Input bias current vs Common-mode input voltage 15 Input bias current and input offset current vs Free-air temperature 16 Common-mode input voltage vs Supply voltage 17 Common-mode input voltage vs Free-air temperature 18 Output voltage vs Differential input voltage 19, 20 Maximum peak output voltage vs Supply voltage 21 Maximum peak-to-peak output voltage vs Frequency 22 Maximum peak output voltage vs Output current 23, 24 Maximum peak output voltage vs Free-air temperature 25, 26 Large-signal differential voltage amplification vs Load resistance 27 Large-signal differential voltage amplification and Phase shift vs Frequency 28 Large-signal differential voltage amplification vs Free-air temperature 29 Output impedance vs Frequency 30 Common-mode rejection ratio vs Frequency 31, 32 Common-mode rejection ratio vs Free-air temperature 33 Supply-voltage rejection ratio vs Free-air temperature 34 Short-circuit output current vs Supply voltage 35 Short-circuit output current vs Time 36 Short-circuit output current vs Free-air temperature 37 Equivalent input noise voltage vs Frequency (TL031 and TL031A) 38 Equivalent input noise voltage vs Frequency (TL032 and TL032A) 39 Equivalent input noise voltage vs Frequency (TL034 and TL034A) 40 Supply current vs Supply voltage (TL031 and TL031A) 41 Supply current vs Supply voltage (TL032 and TL032A) 42 Supply current vs Supply voltage (TL034 and TL034A) 43 Supply current vs Free-air temperature (TL031 and TL031A) 44 Supply current vs Free-air temperature (TL032 and TL032A) 45 Supply current vs Free-air temperature (TL034 and TL034A) 46 Slew rate vs Load resistance 47, 48 Slew rate vs Free-air temperature 49, 50 Overshoot factor vs Load capacitance 51 Total harmonic distortion vs Frequency 52 Unity-gain bandwidth vs Supply voltage 53 Unity-gain bandwidth vs Free-air temperature 54 Phase margin vs Supply voltage 55 Phase margin vs Load capacitance 56 Phase margin vs Free-air temperature 57 Voltage-follower small-signal pulse response 58 Voltage-follower large-signal pulse response 59, 60

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 6 Percentage of Units − % VIO − Input Offset Voltage − mV DISTRIBUTION OF TL031 INPUT OFFSET VOLTAGE ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ

1681 Units Tested From 1 Wafer Lot

ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±15 V ÎÎÎÎ ÎÎÎÎ TA = 25°C P Package Figure 7 0−900 Percentage of Units − % VIO − Input Offset Voltage − μV −600 0 300 600 900

1433 Units Tested From 1 Wafer Lot

VCC± = ±15 V ÎÎÎÎÎ ÎÎÎÎÎ P Package DISTRIBUTION OF TL031A INPUT OFFSET VOLTAGE TA = 25°C −300 Figure 8 −1.2 Percentage of Amplification − % VIO − Input Offset Voltage − mV −0.6 0 0.6 1.2 DISTRIBUTION OF TL032 INPUT OFFSET VOLTAGE ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ

1681 Amplifiers Tested From 1 Wafer Lot

ÎÎÎÎ ÎÎÎÎ TA = 25°C P Package VCC± = ±15 V Figure 9 −900 Percentage of Amplifiers − % VIO − Input Offset Voltage − μV 900 −600 −300 0 300 600 DISTRIBUTION OF TL032A INPUT OFFSET VOLTAGE

1321 Amplifiers Tested From 1 Wafer Lot

VCC± = ±15 V TA = 25°C P Package

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−1.2 VIO − Input Offset Voltage − mV −0.6 0 0.6 1.2 DISTRIBUTION OF TL034 INPUT OFFSET VOLTAGE TA = 25°C ÎÎÎÎ D Package ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±15 V ÎÎÎÎÎÎÎÎÎÎÎÎ Percentage of Amplifiers − % Figure 11 −1.8 Percentage of Amplifiers − % VIO − Input Offset Voltage − mV DISTRIBUTION OF TL034A INPUT OFFSET VOLTAGE ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ

1716 Amplifiers Tested From 3 Wafer Lots

ÎÎÎÎÎ N Package ÎÎÎÎÎÎ ÎÎÎÎÎÎ VCC± = ±15 V TA = 25°C Figure 12 0−30 Percentage of Units − % − Input Offset-Voltage Temperature Coefficient − μV/°C −20 −10 0 10 20 30 DISTRIBUTION OF TL031 INPUT OFFSET-VOLTAGE TEMPERATURE COEFFICIENT

76 Units Tested From 1 Wafer Lot

VCC± = ±15 V TA = 25°C to 125°C P Package /C0097VIO Figure 13 −40 Percentage of Amplifiers − % − Temperature Coefficient − μV/°C −30 −20 −10 0 10 20 30 DISTRIBUTION OF TL032 INPUT OFFSET-VOLTAGE TEMPERATURE COEFFICIENT P Package VCC± = ±15 V ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ

160 Amplifiers Tested From 2 Wafer Lots

ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ TA = 25°C to 125°C /C0097VIO

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 14 −40 Percentage of Amplifiers − % − Temperature Coefficient − μV/°C −30 −20 −10 0 10 20 30 DISTRIBUTION OF TL034 INPUT OFFSET-VOLTAGE TEMPERATURE COEFFICIENT D Package VCC± = ±15 V ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ TA = 25°C to 125°C /C0097VIO Figure 15 −10 −15 IIB − Input Bias Current − nA VIC − Common-Mode Input Voltage − V −10 −5 0 5 10 15 TA = 25°C VCC± = ±15 V INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE IBI Figure 16 0.001 TA − Free-Air Temperature − °C 0.01 0.1 45 65 85 105 125 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT† vs FREE-AIR TEMPERATURE ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC± = ±15 V VO = 0 VIC = 0 ÎÎ ÎÎ IIO ÎÎÎ ÎÎÎ IIB IIB and IIO − Input Bias and Input Offset Current − nAIBI IIO Figure 17 −16 VIC − Common-Mode Input Voltage − V |VCC±| − Supply Voltage − V −12 2 4 6 8 10 12 14 16 T A = 25°C ÎÎÎÎÎ ÎÎÎÎÎ Positive Limit ÎÎÎÎÎ ÎÎÎÎÎ Negative Limit COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE ÁÁ ÁÁ ÁÁ VIC † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1251007550250−25−50 −10 −15 T A − Free-Air Temperature −°C −75 −20 VCC± = ±15 V ÎÎÎÎÎ Positive Limit ÎÎÎÎÎ ÎÎÎÎÎ Negative Limit COMMON-MODE INPUT VOLTAGE† vs FREE-AIR TEMPERATURE VIC − Common-Mode Input Voltage − V ÁÁÁ ÁÁÁ VIC Figure 19 −1.5 0.5 1.5 − 4 − 3 − 2 − 1 012345 OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE −0.5 ÎÎÎÎÎ ÎÎÎÎÎ RL = 1 kΩ ÎÎÎÎ RL = 2 kΩ ÎÎÎÎ RL = 5 kΩ ÎÎÎÎÎ ÎÎÎÎÎ RL = 10 kΩ ÎÎÎÎÎ ÎÎÎÎÎ RL = 20 kΩ VCC± = ±5 V TA = 25°C ÎÎÎ RL = 1 kΩ ÎÎÎ ÎÎÎ RL = 2 kΩ ÎÎÎÎ ÎÎÎÎ RL = 5 kΩ ÎÎÎÎ ÎÎÎÎ RL = 20 kΩ ÎÎÎÎ RL = 10 kΩ − Output Voltage − VVO VID − Differential Input Voltage − V Figure 20 −1.5 −15 −0.5 0.5 −10 −5 0 5 10 1.5 OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE ÈÈÈÈ ÈÈÈÈ RL = 5 kΩ ÈÈÈÈ ÈÈÈÈ RL = 10 kΩ ÈÈÈÈ RL = 20 kΩ ÈÈÈÈ ÈÈÈÈ RL = 50 kΩ TA = 25°C VCC± = ±15 V VID − Differential Input Voltage − V − Output Voltage − VVO RL = 5 kΩ RL = 10 kΩ RL = 20 kΩ RL = 50 kΩ Figure 21 −16 0 VOM − Maximum Peak Output Voltage − V |VCC±| − Supply Voltage − V −12 2 4 6 8 1 01 21 41 6 TA = 25°C RL = 10 kΩ ÎÎÎ ÎÎÎ VOM− VOM+ MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE ÁÁ ÁÁ VOM † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−16 TA − Free-Air Temperature −°C −75 −50 −25 0 25 50 75 100 125 −12 VOM+ MAXIMUM PEAK OUTPUT VOLTAGE† vs FREE-AIR TEMPERATURE ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±15 V RL = 10 kΩ VOM − Maximum Peak Output Voltage − V ÁÁ ÁÁ ÁÁ VOM ÎÎÎ ÎÎÎ VOM− Figure 27 RL − Load Resistance − Ω 10 k 100 k 1 M VCC± = ±15 V VCC± = ±5 V TA = 25°C VO = ±1 V LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE − Large-Signal DifferentialAVD Voltage Amplification − V/mV 0.1 f − Frequency − Hz 100 k 10 k 1 k 100 100 1 k 10 k 100 k 1 M 10 M 30° 60° 90° 120° 150° 180° Phase Shift ÎÎÎ ÎÎÎ AVD VCC± = ±15 V RL = 10 kΩ CL = 25 pF TA = 25°C LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY ÎÎÎÎ ÎÎÎÎ Phase Shift − Large-Signal DifferentialAVD Voltage Amplification Figure 28 † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−75 CMRR − Common-Mode Rejection Ratio − dB TA − Free-Air Temperature − °C 125 −50 −25 0 25 50 75 100 VCC± = ±15 V VCC± = ±5 V COMMON-MODE REJECTION RATIO† vs FREE-AIR TEMPERATURE ÎÎÎÎÎ ÎÎÎÎÎ VIC = VICRmin Figure 34 −75 − Supply Voltage Rejection Ratio − dB TA − Free-Air Temperature − °C 125 100 −50 −25 0 25 50 75 100 VCC± = ±5 V to ±15 V SUPPLY-VOLTAGE REJECTION RATIO† vs FREE-AIR TEMPERATURE SVRk Figure 35 −30 IOS − Short-Circuit Output Current − mA |VCC±| − Supply Voltage − V 24 6 8 10 12 14 −20 −10 VO = 0 TA = 25°C VID = 100 mV VID = −100 mV SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE ÁÁ ÁÁ OSI Figure 36 −20 t − Time − s 51 0 15 20 25 −10 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ VCC± = ±15 V TA = 25°C VID = −100 mV VID = 100 mV SHORT-CIRCUIT OUTPUT CURRENT vs TIME IOS − Short-Circuit Output Current − mA ÁÁ ÁÁ OSI † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

|VCC±| − Supply Voltage − V 250 2 4 6 8 10 12 14 100 150 200 TA = 25°C TA = 125°C TA = −55°C ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ VO = 0 No Load ICC − Supply Current − A ÁÁ ÁÁ CCI Aμ TL031 and TL031A SUPPLY CURRENT† vs SUPPLY VOLTAGE Figure 42 ICC − Supply Current −A |VCC±| − Supply Voltage − V 500 24 6 8 10 12 14 100 200 300 400 TA = 25°C TA = 125°C TA = −55°C ÁÁ ÁÁ ÁÁ CCI Aμ ÁÁÁ ÁÁÁ VO = 0 No Load TL032 and TL032A SUPPLY CURRENT† vs SUPPLY VOLTAGE Figure 43 ICC − Supply Current −A |VCC±| − Supply Voltage − V 1000 2 4 6 8 10 12 14 200 400 600 800 TA = 25°C TA = 125°C TA = −55°C ÁÁ ÁÁ ÁÁ CCI Aμ ÎÎÎ ÎÎÎ ÎÎÎ VO = 0 No Load TL034 and TL034A SUPPLY CURRENT† vs SUPPLY VOLTAGE Figure 44 −75 TA − Free-Air Temperature − °C 125 250 −50 −25 0 25 50 75 100 100 150 200 VCC± = ±15 V VCC± = ±5 V ÁÁÁ ÁÁÁ ÁÁÁ VO = 0 No Load ICC − Supply Current − A ÁÁ ÁÁ CCI Aμ TL031 and TL031A SUPPLY CURRENT† vs FREE-AIR TEMPERATURE † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−75 TA − Free-Air Temperature − °C 125 −50 −25 0 25 50 75 100 SR− SR+ SLEW RATE† vs FREE-AIR TEMPERATURE SR − Slew Rate − V/s sμ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±5 V RL = 10 kΩ CL = 100 pF See Figure 1 Figure 50 −75 TA − Free-Air Temperature − °C 125 −50 −25 0 25 50 75 100 SR− SR+ SLEW RATE† vs FREE-AIR TEMPERATURE SR − Slew Rate − V/s sμ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ VCC± = ±15 V RL = 10 kΩ CL = 100 pF See Figure 1 Figure 51 Overshoot Factor − % CL − Load Capacitance − pF 250 50 100 150 200 VI(PP) = ±10 mV RL = 10 kΩ TA = 25°C See Figure 1 ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±5 V OVERSHOOT FACTOR vs LOAD CAPACITANCE ÎÎÎÎÎÎ VCC± = ±15 V Figure 52 100 0.1 THD − Total Harmonic Distortion − % f − Frequency − Hz 100 k 0.5 0.2 0.3 0.4 1 k 10 k VCC± = ±15 V AVD = 1 VO(rms) = 6 V TA = 25°C TOTAL HARMONIC DISTORTION vs FREQUENCY † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−75 55° TA − Free-Air Temperature −°C 125 67° −50 −25 0 25 50 75 100 57° 59° 61° 63° 65° VCC± = ±5 V PHASE MARGIN† vs FREE-AIR TEMPERATURE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VI = 10 mV RL = 10 kΩ CL = 25 pF See Figure 4 − Phase Marginmφ ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±15 V Figure 58 −16 VO − Output Voltage − mV t − Time − μs 1.4 −12 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE ÁÁ ÁÁ VO ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC± = ±15 V RL = 10 kΩ CL = 100 pF See Figure 1 TA = 25°C Figure 59 VO − Output Voltage − V t − Time − μs 01 2 3 45 6 7 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE ÁÁ ÁÁ VO VCC± = ±5 V RL = 10 kΩ CL = 100 pF TA = 25°C See Figure 1 Figure 60 t − Time − μs 1614121086421 8 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ See Figure 1 TA = 25°C CL = 100 pF RL = 10 kΩ VCC± = ±15 V VO − Output Voltage − V ÁÁ ÁÁ VO † Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The TL03x and TL03xA are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Due to of the extremely high input impedance and resulting low bias-current requirements, the TL03x and TL03xA are well suited for low-level signal processing; however, leakage currents on printed circuit boards and sockets easily can exceed bias-current requirements and cause degradation in system performance. It is a good practice to include guard rings around inputs (see Figure 61). These guard rings should be driven from a low-impedance source at the same voltage level as the common-mode input. Unused amplifiers should be connected as grounded unity-gain followers to avoid oscillation. (c) UNITY-GAIN AMPLIFIER(b) INVERTING AMPLIFIER(a) NONINVERTING AMPLIFIER VO VI VI VO VO VI Figure 61. Use of Guard Rings

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance. The TL03x and TL03xA drive higher capacitive loads; however, as the load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation. The value of the load capacitance at which oscillation occurs varies with production lots. If an application appears to be sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate the problem (see Figure 63). Capacitive loads of 1000 pF and larger can be driven if enough resistance is added in series with the output (see Figure 62). (a) CL = 100 pF, R = 0 (b) C L = 300 pF, R = 0 (c) C L = 350 pF, R = 0 (d) CL = 1000 pF, R = 0 (e) C L = 1000 pF, R = 50 Ω (f) CL = 1000 pF, R = 2 kΩ Figure 62. Effect of Capacitive Loads NOTE A: CL includes fixture capacitance. Figure 63. Test Circuit for Output Characteristics

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The low-power precision TL03x allows accurate measurement of low currents. The high input impedance and low offset voltage of the TL03xA greatly simplify the design of a transimpedance amplifier. At room temperature, this design achieves 10-bit accuracy with an error of less than 1/2 LSB. Assuming that R2 is much less than R1 and ignoring error terms, the output voltage can be expressed as: VO /C0043–I IN /C0032RF/C0466R1 /C0041R2 R2 /C0467 Using the resistor values shown in the schematic for a 1-nA input current, the output voltage equals −0.1 V. If the VO limit for the TL03xA is measured at ±12 V, the maximum input current for these resistor values is ±120 nA. Similarly, one LSB on a 10-bit scale corresponds to 12 mV of output voltage, or 120 pA of input current. The following equation shows the effect of input offset voltage and input bias current on the output voltage: VO /C0043– /C0426VIO /C0041RF/C0466IIO /C0041IIB/C0467/C0427/C0466R1 /C0041R2 R2 /C0467 If the application requires input protection for the transimpedance amplifier, do not use standard PN diodes. Instead, use low-leakage Siliconix SN4117 JFETs (or equivalent) connected as diodes across the TL03xA inputs (see Figure 65). As with all precision applications, special care must be taken to eliminate external sources of leakage and interference. Other precautions include using high-quality insulation, cleaning insulating surfaces to remove fluxes and other residue, and enclosing the application within a protective box. 15 V −15 V TL03xA RF 10 MΩ 90 kΩ VO 10 kΩR2 SN4117 Input Current Figure 65. Transimpedance Amplifier

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 45POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-mA to 20-mA current loops Often, information from an analog sensor must be sent over a distance to the receiving circuitry. For many applications, the most feasible method involves converting voltage information to a current before transmission. The following circuits give two variations of low-power current loops. The circuit in Figure 66 requires three wires from the transmitting to receiving circuitry, while the second variation in Figure 67 requires only two wires, but includes an extra integrated circuit. Both circuits benefit from the high input impedance of the TL03xA because many inexpensive sensors do not have low output impedance. Assuming that the voltage at the noninverting input of the TL03xA is zero, the following equation determines the output current: IO /C0043VI/C0466R3 R1 /C0032RS /C0467/C00415V/C0466R3 R2 /C0032RS /C0467/C00430.16 /C0032VI /C00414mA The circuits presently provide 4-mA to 20-mA output current for an input voltage of 0 to 100 mV. By modifying R1, R2, and R3, the input voltage range or the output current range can be adjusted. Including the offset voltage of the operational amplifier in the above equation clearly illustrates why the low offset TL03xA was chosen: IO /C0043VI/C0466R3 R1 /C0032RS /C0467/C00415V/C0466R3 R2 /C0032RS /C0467/C0042VI/C0466R3 R1 /C0032RS /C0041R3 R2 /C0032RS /C0041R1 RS /C0467 /C00430.16 /C0032VI /C00414mA – 0.17 /C0032VI For example, an offset voltage of 1 mV decreases the output current by 0.17 mA. Due to the low power consumption of the TL03xA, both circuits have at least 2 mA available to drive the actual sensor from the 5-V reference node.

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3.3 kΩ 2N3904 TL03xA

1 MΩR2

5 kΩ R3 80 k Ω R4 5 k Ω VI Signal Common 1N4148 RS 100 Ω RL 50 Ω IO

5 V Ref

VCC+ = 10 V VEE = −5 V 100 kΩ TL431 100 kΩ Figure 66. Three-Wire 4-mA to 20-mA Current Loop Figure 67. Two-Wire 4-mA to 20-mA Current Loop

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 low-level light-detector preamplifier Applications that need to detect small currents require high input-impedance operational amplifiers; otherwise, the bias currents of the operational amplifier camouflage the current being monitored. Phototransistors provide a current that is proportional to the light reaching the transistor. The TL03x allows even the small currents resulting from low-level light to be detected. In Figure 68, if there is no light, the phototransistor is off and the output is high. As light is detected, the operational amplifier output begins pulling low. Adjusting R4 both compensates for offset voltage of the amplifier and adjusts the point of light detection by the amplifier. TL03x 10 kΩ 100 pF TIL601 R2 5 k Ω 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 15 V VO −15 V Figure 68. Low-Level Light-Detector Preamplifier

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001

48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

audio-distribution amplifier This audio-distribution amplifier (see Figure 69) feeds the input signal to three separate output channels. U1A amplifies the input signal with a gain of 10, while U1B, U1C, and U1D serve as buffers to the output channels. The gain response of this circuit is very flat from 20 Hz to 20 kHz. The TL03x allows quick response to the input signal while maintaining low power consumption. VCC+ 1 MΩ 1 μF U1B 10 kΩ 100 kΩ 100 μF U1C U1D U1A 100 kΩ 100 kΩ VI VCC+ VOA VOB VOC NOTE A: U1A through U1D = TL03x; V CC+ = 5 V Figure 69. Audio-Distribution Amplifier Circuit

TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 49POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 instrumentation amplifier with linear gain adjust The low offset voltage and low power consumption of the TL03x provide an accurate but inexpensive instrumentation amplifier (see Figure 70). This particular configuration offers the advantage that the gain can be linearly set by one resistor: V O = R6 × (VB − VA) Adjusting R6 varies the gain. The value of R6 always should be greater than, or equal to, the value of R5 to ensure stability. The disadvantage of this instrumentation amplifier topology is the high degree of CMRR degradation resulting from mismatches between R1, R2, R3, and R4. For this reason, these four resistors should be 0.1%-tolerance resistors. U1C U1A 1 MΩ VA VCC+ VO VB U1B 10 kΩ 0.1% 10 kΩ 0.1% 100 kΩ 100 kΩ 10 kΩ 0.1% 10 kΩ 0.1% U1D VCC− NOTE A: U1A through U1D = TL03x; V CC± = ±15 V Figure 70. Instrumentation Amplifier With Linear Gain-Adjust Circuit

www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-9086102Q2A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 TL031ACD OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 TL031ACP OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 TL031AID OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 TL031AIP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 TL031CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C TL031CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C TL031CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C TL031CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL031C TL031CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL031CP TL031CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL031CP TL031CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70 TL031ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL031I TL031IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL031I TL031IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL031IP TL032ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 032AC TL032ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 032AC TL032ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 032AC TL032ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL032ACP

www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL032AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI TL032AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI TL032AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI TL032AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 032AI TL032AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL032AIP TL032CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C TL032CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C TL032CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C TL032CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C TL032CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL032C TL032CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL032CP TL032CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL032CP TL032CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T032 TL032CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70 TL032ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I TL032IDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I TL032IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I TL032IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I

www.ti.com 10-Jun-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL032IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL032I TL032IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL032IP TL032IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL032IP TL032MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 TL032MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125 TL034ACD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034AC TL034ACDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034AC TL034ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034AC TL034ACN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL034ACN TL034AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034AI TL034AIDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034AI TL034AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034AI TL034AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL034AIN TL034CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034C TL034CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034C TL034CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL034CN TL034CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL034CN TL034CNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL034 TL034CPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T034

www.ti.com 10-Jun-2014 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL034CPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70 TL034CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T034 TL034ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I TL034IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I TL034IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I TL034IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL034I TL034IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL034IN TL034INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL034IN TL034MD OBSOLETE SOIC D 14 TBD Call TI Call TI -55 to 125 TL034MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 TL034MJB OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125 TL034MN OBSOLETE PDIP N 14 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 10-Jun-2014 Addendum-Page 5 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL031CDR SOIC D 8 2500 340.5 338.1 20.6 TL032ACDR SOIC D 8 2500 340.5 338.1 20.6 TL032AIDR SOIC D 8 2500 340.5 338.1 20.6 TL032CDR SOIC D 8 2500 340.5 338.1 20.6 TL032CPSR SO PS 8 2000 367.0 367.0 38.0 TL032IDR SOIC D 8 2500 340.5 338.1 20.6 TL034AIDR SOIC D 14 2500 367.0 367.0 38.0 TL034CDR SOIC D 14 2500 367.0 367.0 38.0 TL034CNSR SO NS 14 2000 367.0 367.0 38.0 TL034CPWR TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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Product Information

TL031CDRG4 specifications and overview.

Summary

ENHANCED-JFET LOW-POWER LOW-OFFSET

Description

ENHANCED-JFET LOW-POWER LOW-OFFSET

Source title TL031CDRG4 Datasheet(PDF) - Texas Instruments

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