TL026CD.A

TL026 TI | Alldatasheet

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DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Output Common-Mode Sensitivity to AGC Voltages /C0068Input and Output Impedances Independent of AGC Voltage /C0068Peak Gain. . . 38 dB Typ /C0068Wide AGC Range . . . 50 dB Typ /C00683-dB Bandwidth. . . 50 MHz /C0068Other Characteristics Similar to NE592 and uA733

description

This device is a monolithic two-stage high- frequency amplifier with differential inputs and outputs. Internal feedback provides wide bandwidth, low phase distortion, and excellent gain stability. Variable gain based on signal summation provides large AGC control over a wide bandwidth with low harmonic distortion. Emitter-follower outputs enable the device to drive capacitive loads. All stages are current-source biased to obtain high common-mode and supply-voltage rejection ratios. The gain may be electronically attenuated by applying a control voltage to the AGC pin. No external compensation components are required. This device is particularly useful in TV and radio IF and RF AGC circuits, as well as magnetic-tape and disk-file systems where AGC is needed. Other applications include video and pulse amplifiers where a large AGC range, wide bandwidth, low phase shift, and excellent gain stability are required. The TL026C is characterized for operation from 0°C to 70°C. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to the midpoint of VCC+ and VCC– except differential input and output voltages. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING D 725 mW 5.8 mW/°C 464 mW P 1000 mW 8.0 mW/°C 640 mW Copyright  1990, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. IN– REF OUT V CC + OUT– IN+ AGC VCC OUT+ D OR P PACKAGE (TOP VIEW) symbol AGC IN + IN – REF OUT OUT+ OUT–

DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990

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recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC + 3 6 8 V Supply voltage, VCC – – 3 – 6 – 8 V Operating free-air temperature range, TA 0 70 °C electrical characteristics at 25°C operating free-air temperature, VCC+ = ±6 V, VAGC = 0, REF OUT pin open (unless otherwise specified) PARAMETER FIGURE TEST CONDITIONS MIN TYP MAX UNIT AVD Large-signal differential voltage amplification 1 VO(PP) = 3 V, R L = 2 kW 65 85 105 V/V DAVD Change in voltage amplification 1 VIPP = 28.5 mV, RL = 2 kW, VAGC – Vref = ±180 mV – 50 dB Vref Voltage at REF OUT Iref = – 1 mA to 100 mA 1.3 1.5 V BW Bandwidth (–3 dB) 2 VO(PP) = 1 V, VAGC – Vref = ±180 mV 50 MHz IIO Input offset current 0.4 5 mA IIB Input bias current 10 30 mA VICR Common-mode input voltage range 3 ±1 V VOC Common-mode output voltage 1 R L = ∞ 3.25 3.75 4.25 V DVOC Change in common-mode output voltage 1 VAGC = 0 to 2 V,R L = ∞ 300 mV VOO Output offset voltage 1 VID = 0, R L = ∞ 0.75 V VO(PP) Maximum peak-to-peak output voltage swing 1 R L = 2 kW 3 4 V ri Input resistance at AGC, IN+, or IN – 10 30 kW ro Output resistance 20 W CMRR Common mode rejection ratio 3 VIC = ±1 V, f = 100 kHz 60 86 dBCMRR Common -mode rejection ratio 3 VIC = ±1 V, f = 5 mHz 60 dB kSVR Supply voltage rejection ratio (DVCC / DVIO) 4 DVCC + = ± 0.5 V, DVCC – = ± 0.5 V 50 70 dB Vn Broadband equivalent noise voltage 4 BW = 1 kHz to 10 MHz 12 mV tpd Propagation delay time 2 DVO = 1 V 6 10 ns tr Rise time 2 DVO = 1 V 4.5 12 ns Isink(max) Maximum output sink current VID = 1 V, VO = 3 V 3 4 mA ICC Supply current No load, No signal 22 27 mA

50 W 50 W

Figure 1. Test Circuit Figure 2. Test Circuit Figure 3. Test Circuit Figure 4. Test Circuit

DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– 200 – 100 0 100 200 A DIFFERENTIAL VOLTAGE AMPLIFICATION vs DIFFERENTIAL GAIN-CONTROL VOLTAGE VD VAGC – Vref – Differential Gain-Control Voltage – mV 100 VCC + = 6 V VCC – = – 6 V TA = 0°C TA = 70°C TA = 25°C — Differential Voltage Amplification — V/ V

DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Figure 5 shows the differential voltage amplification versus the differential gain-control voltage (VAGC – Vref). VAGC is the absolute voltage applied to the AGC input and Vref is the dc voltage at the REF OUT output. As VAGC increases with respect to Vref, the TL026C gain changes from maximum to minimum. As shown in Figure 5 for example, VAGC would have to vary from approximately 180 mV less than Vref to approximately 180 mV greater than Vref to change the gain from maximum to minimum. The total signal change in VAGC is defined by the following equation. DVAGC = Vref + 180 mV – (Vref – 180 mV) DVAGC = 360 mV (1) However, because VAGC varies as the ac AGC signal varies and also differentially around Vref, then VAGC should have an ac signal component and a dc component. To preserve the dc and thermal tracking of the device, this dc voltage must be generated from V ref. To apply proper bias to the AGC input, the external circuit used to generate VAGC must combine these two voltages. Figures 6 and 7 show two circuits that will perform this operation and are easy to implement. The circuits use a standard dual operational amplifier for AGC feedback. By providing rectification and the required feedback gain, these circuits are also complete AGC systems. circuit operation Amplifier A1 amplifies and inverts the rectified and filtered AGC signal voltage VC producing output voltage V1. Amplifier A2 is a differential amplifier that inverts V1 again and adds the scaled Vref voltage. This conditioning makes VAGC the sum of the signal plus the scaled Vref. As the signal voltage increases, VAGC increases and the gain of the TL026C is reduced. This maintains a constant output level. feedback circuit equations Following the AGC input signal (Figures 6 and 7) from the OUT output through the feedback amplifiers to the AGC input produces the following equations: (2) 1. AC ouput to diode D1, assuming sinusoidal signals V O = VOP (sin (wt)) where: VOP = peak voltage of VO (3) 2. Diode D1 and capacitor C1 output VC = VOP – VF where: VF = forward voltage drop of D1 V C = voltage across capacitor C1 (4) 3. A1 output V1 /C0043/C0042R2 R1 V C (5) 4. A2 output (R3 = R4) V AGC /C0043R2 R1 V C /C00412 R6 R5 /C0041R6 V ref

DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990

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Amplifier A2 inverts V1 producing a positive AGC signal voltage. Therefore, the input voltage to the TL026C AGC pin consists of an AGC signal equal to: (6)R2 R1 V C and a dc voltage derived from Vref, defined as the quiescent value of VAGC . V AGC (q)/C00432 R6 R5 /C0041R6 V ref (7) For the initial resistor calculations, Vref is assumed to be typically 1.4 V making quiescent VAGC approximately 1.22 V (VAGC (q) = Vref – 180 mV). This voltage allows the TL026C to operate at maximum gain under no-signal and low-signal conditions. In addition, with Vref used as both internal and external reference, its variation from device to device automatically adjusts the overall bias and makes AGC operation essentially independent of the absolute value of V ref. The resistor divider needs to be calculated only once and is valid for the full tolerance of Vref. output voltage limits (see Figures 6 and 7) The output voltage level desired must fall within the following limits: 1. Because the data sheet minimum output swing is 3 V peak-to-peak using a 2-kW load resistor, the user-selected design limit for the peak output swing should not exceed 1.5 V. 2. The voltage drop of the rectifying diode determines the lower voltage limit. When a silicon diode is used, this voltage is approximately 0.7 V. The output voltage VO must have sufficient amplitude to exceed the rectifying diode drop. Aschottky diode can be used to reduce the VO level required. gain calculations for a peak output voltage of 1 V A peak output voltage of 1 V was chosen for gain calculations because it is approximately midway between the limits of conditions 1 and 2 in the preceding paragraph. Using equation 3 (V C = VOP – Vd), VC is calculated as follows: VC = 1 V – 0.7 V VC = 0.3 V Therefore, the gain of A1 must produce a voltage V1 that is equal to or greater than the total change in VAGC for maximum TL026C gain change. With a total change in V AGC of 360 mV and using equation 4, the calculation is as follows: /C0042V1 V C /C0043 /C0068V AGC V C /C0043R2 R1 /C00430.36 0.3 /C00431.2 If R1 is 10 kW , R2 is 1.2 time R1 or 12 kW . Since the output voltage for this circuit must be between 0.85 V and 1.3 V, the component values in Figures 6 and 7 provide a nominal 1-V peak output limit. This limit is the best choice to allow for temperature variations of the diode and minimum output voltage specification.

DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 The circuit values in Figures 6 and 7 will produce the best results in this general application. Because of rectification and device input constraints, the circuit in Figure 6 will not provide attenuation and has about 32 dB of control range. The circuit shown in Figure 7 will have approximately 25% variation in the peak output voltage limit due to the variation in gain of the TL592 device to device. In addition, if a lower output voltage is desired, the output of the TL026C can be used for approximately 40 mV of controlled signal. considerations for the use of the TL026C To obtain the most reliable results, RF breadboarding techniques must be used. A groundplane board should be used and power supplies should be bypassed with 0.1-mF capacitors. Input leads and output leads should be as short as possible and separated from each other. A peak input voltage greater than 200 mV will begin to saturate the input stages of the TL026C and, while the circuit is in the AGC mode, the output signal may become distorted. To observe the output signal of TL026C or TL592, low-capacitance FET probes or the output voltage divider technique shown in Figure 6 should be used. OUT + OUT – 0.1 mF 0.1 mFREF OUT 30 kW To Scope Monitor Vout 200 W 1.8 kW IN – IN + 50 W AGC 10 kW 10 kW VAGC 20 kW

50 WVI

0.1 mFV1 1/2 TL082 1/2 TL082 TL026C NOTE: V CC+ = 6 V and VCC– = – 6 V for TL026C and amplifiers A1 and A2. Figure 6. Typical Application Circuit With No Attenuation

DIFFERENTIAL HIGH-FREQUENCY AMPLIFIER WITH AGC SLFS007A – JUNE 1985 – REVISED JULY 1990

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0.1 mF VOUT – VOUT + 0.1 mF 50 W 10 kW 12 kW 1/2 TL0820.1 mF OUT – OUT + IN – IN + AGC To Scope Monitor 10 kW 1/2 TL082 30 kW 10 kW VAGC VI 1.8 kW 200 W 1N914 REF OUT TL026C0.1 mF TL592 2 kW 2 kW 510 W X20 Gain NOTE: V CC + = 6 V and VCC – = – 6 V for TL026C and amplifiers A1 and A2. Figure 7. Typical Application Circuit With Attenuation

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL026CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL026C TL026CD.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL026C TL026CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL026C TL026CDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 TL026C TL026CP Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL026CP TL026CP.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TL026CP TL026CPSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T026 TL026CPSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 T026 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL026CDR SOIC D 8 2500 353.0 353.0 32.0 TL026CPSR SO PS 8 2000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TL026CD D SOIC 8 75 507 8 3940 4.32 TL026CD.A D SOIC 8 75 507 8 3940 4.32 TL026CP P PDIP 8 50 506 13.97 11230 4.32 TL026CP.A P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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