TFP501 TI | Alldatasheet
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/C0084/C0070/C0080/C0053/C0048/C0049 /C0080/C0097/C0110/C0101/C0108/C0066/C0117/C0115 /C0072/C0068/C0067/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0082/C0069/C0067/C0069/C0073/C0086/C0069/C0082 SLDS127B – JULY 2001 – REVISED AUGUST 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Supports UXGA Resolution (Output Pixel Rates up to 165 MHz) /C0068Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection (HDCP) Specification Compliant /C0068Encrypted External HDCP Device Key Storage for Exceptional Security and Ease of Implementation /C0068True-Color, 24 Bits/Pixel, 48-bit Dual Pixel Output Mode, 16.7M Colors at 1 or 2 Pixels Per Clock /C0068Laser Trimmed (50-Ω ) Input Stage for Optimum Fixed Impedance Matching /C0068Skew Tolerant up to One Pixel Clock Cycle (High Clock and Data Jitter Tolerance) /C00684x Over-Sampling for Reduced Bit-Error Rates and Better Performance Over Longer Cables /C0068Reduced Power Consumption From 1.8-V Core Operation With 3.3-V I/O’s and Supplies /C0068Reduced Ground-Bounce Using Time Staggered Pixel Outputs /C0068Lowest Noise and Best Power Dissipation Using TI 100-pin TQFP PowerPAD Packaging /C0068Advanced Technology Using TI’s 0.18-µm EPIC-5 CMOS Process /C0068Supports Hot Plug Detection
description
The TFP501 is a Texas Instruments PanelBus flat panel display product, part of a comprehensive family of end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors, and digital TVs, the TFP501 finds applications in any design requiring high-speed digital interface with the additional benefit of an extremely robust and innovative encryption scheme for digital content protection. The TFP501 supports display resolutions up to UXGA, including the standard HDTV formats, in 24-bit true color pixel format. The TFP501 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time staggered pixel outputs for reduced ground-bounce. PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultra-low ground inductance. The TFP501 combines PanelBus circuit innovation and unique implementation for HDCP key protection with TI’s advanced 0.18 µm EPIC-5 CMOS process technology to achieve a completely secure, reliable, low-powered, low noise, high-speed digital interface solution. Footnotes: 1. The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high–speed digital connection to digital displays. The high–bandwidth digital content protection system (HDCP) is an industry standard for protecting DVI outputs from being copied. HDCP was developed by Intel Corporation and is licensed by the Digital Content Protection, LLC. The 2. The TFP501 has an internal voltage regulator that provides the 1.8 V core power supply from the externally supplied 3.3 V supplies. Copyright 2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(TOP VIEW) QO1 QO0 HSYNC VSYNC DE OGND ODCK OV DD RSVD CTL2 CTL1 DGND DV DD QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OV DD OGND QE15 QE14 OGND QO23 OV DD AGND Rx2+ Rx2– AV DD Rx1+ Rx1– AV DD Rx0+ Rx0– AV DD RxC+ RxC – AV DD DDC_SCL DDC_SDA DDC_SA PROM_SCL PROM_SDA PV DD 1 PGND PV DD 2 OCK_INV QO22 QO21 QO20 QO19 QO18 QO17 QO16 DGND CAP QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OV DD QO7 QO6 QO5 QO4 QO3 QO2 DFO PD ST PIXS DGND DV DD STAG SCDT PDO QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OV DD OGND QE8 QE9 QE10 QE11 QE12 QE13
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram + Latch Channel 2 + Latch Channel 1 Latch Channel 0 PLL T.M.D.S. Decoder CH2[9:0] CH1[9:0] CH0[9:0] RED[7:0] CTL2 GRN[7:0] CTL1 BLU[7:0] VSYNC HSYNC QE[23:0] QO[23:0] ODCK DE SCDT CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50 Ω Termination Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- HDCP Decryption RED[7:0] CTL2 GRN[7:0] CTL1 BLU[7:0] VSYNC HSYNC Panel Interface I2C Master I/F for EEPROM PROM_SCL 3.3 V PROM_SDA Key Decryption RAM Block I2C Slave I/F for DDC DDC_SCL DDC_SA DDC_SDA I2C Control Registers Data Recovery and Synchronization
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 79 Analog ground— Ground reference and current return for analog circuitry. AV DD 82, 85, 88, 91 Analog VDD — Power supply for analog circuitry. Nominally 3.3 V. CAP 67 O Bypass capacitor— 4.7 µF tantalum and 0.01 µF ceramic capacitors connected to ground. CTL[2:1] 41, 40 O General purpose control signals— Used for user defined control. In normal mode CTL1 is not powered down via PDO. DDC_SA 94 I Display data channel_serial address— I2C Slave address bit A0 for display data channel (DDC). Refer to I2C Interface section for more details. DDC_SCL 92 I/O Display data channel_serial clock— I2C Clock for the DDC. External pullup resistors = 10 kΩ and 3.3 V tolerant. DDC_SDA 93 I/O Display data channel_serial data— I2C Data for the DDC. External pullup resistors = 10 kΩ and 3.3 V tolerant. DE 46 O Output data enable— Used to indicate time of active video display versus nonactive display or blanking interval. During blanking, only HSYNC, VSYNC and CTL1–2 are transmitted. During times of active display, or nonblanking, only pixel data, QE[23:0] and QO[23:0], is transmitted. High: active display interval Low: blanking interval DFO 1 I Output clock data format— Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; other- wise, ODCK is held low when DE is low. High: DSTN support/ODCK held low when DE = low. Low: TFT support/ODCK runs continuously. DGND 5, 39, 68 Digital ground— Ground reference and current return for digital core. DV DD 6, 38 Digital VDD — Power supply for digital core. Nominally 3.3 V. HSYNC 48 O Horizontal sync output OCK_INV 100 I ODCK Polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL1–2 ) are latched. Normal mode: High: latches output data on rising ODCK edge. Low: latches output data on falling ODCK edge. ODCK 44 O Output data clock— Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with DE, HSYNC, VSYNC and CTL[2:1] are synchronized to this clock. OGND 19, 28, 45, 58, Output driver ground— Ground reference and current return for digital output drivers. OV DD 18, 29, 43, 57, Output driver VDD — Power supply for output drivers. Nominally 3.3 V. PD 2 I Power down— An active low signal that controls the TFP501 power-down state. During power down all output buffers are switched to a high-impedance state and brought low through a weak pulldown. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected, an internal pullup defaults the TFP501 to normal operation. High: normal operation Low: power down PDO 9 I Output drive power down— An active low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. A weak pulldown slowly pulls these outputs to a low level. When PDO is left unconnected an internal pullup defaults the TFP501 to normal operation. High: normal operation/output drivers on. Low: output drive power down.
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION PGND 98 PLL ground – Ground reference and current return for internal PLL. PIXS 4 I Pixel select— Selects between one or two pixel per clock output modes. During 2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1 pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.) High: 2 pixel/clock Low: 1 pixel/clock PROM_SCL 95 I/O EEPROM_serial clock— I2C clock for EEPROM interface data. External pullup resistors = 10 kΩ and 3.3 V tolerant. PROM_SDA 96 I/O EEPROM_serial data— I2C data for EEPROM interface data. External pullup resistors = 10 kΩ and 3.3 V tolerant. PV DD (1, 2) 97, 99 PLL VDD — Power supply for internal PLL. Nominally 3.3 V. QE[0:7] 10–17 O Even blue pixel output— Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only blue pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0/pin 10 MSB: QE7/pin 17 QE[8:15] 20–27 O Even green pixel output— Output for even and odd green pixels when in 1-pixel/clock mode. Output for even only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8/pin 20 MSB: QE15/pin 27 QE[16:23] 30–37 O Even red pixel output— Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16/pin 30 MSB: QE23/pin 37 QO[0:7] 49–56 O Odd blue pixel output— Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0/pin 49 MSB: QO7/pin 56 QO[8:15] 59–66 O Odd green pixel output— Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8/pin 59 MSB: QO15/pin 66 QO[16:23] 69–75, O Odd red pixel output— Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16/pin 69 MSB: QO23/pin 77 RSVD 42 O Reserved— Must be tied high for normal operation. Rx2+ 80 I Channel-2 positive receiver input— Positive side of channel-2 T.M.D.S. low voltage signal differential input pair. Channel-2 receives red pixel data in active display and CTL2 control signal during blanking. Rx2– 81 I Channel-2 negative receiver input— Negative side of channel-2 T.M.D.S. low voltage signal differential input pair. Rx1+ 83 I Channel-1 positive receiver input— Positive side of channel-1 T.M.D.S. low voltage signal differential input pair. Channel–1 receives green pixel data in active display and CTL1 control signal during blanking. Rx1– 84 I Channel-1 negative receiver input— Negative side of channel-1 T.M.D.S. low voltage signal differential input pair. Rx0+ 86 I Channel-0 positive receiver input— Positive side of channel-0 T.M.D.S. low voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals during blanking. Rx0– 87 I Channel-0 negative receiver input— Negative side of channel-0 T.M.D.S. low voltage signal differential input pair.
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION RxC+ 89 I Clock positive receiver input— Positive side of reference clock T.M.D.S. low voltage signal differential input pair. RxC – 90 I Clock negative receiver input— Negative side of reference clock T.M.D.S. low voltage signal differential input pair. SCDT 8 O Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP501 monitors the state DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: active link Low: inactive link ST 3 I Output drive strength select— Selects output drive strength for high or low current drive. (see dc specifications for IOH and IOL vs ST state.) High: high drive strength Low: low drive strength STAG 7 I Staggered pixel select – An active low signal used in 2 pixel/clock pixel mode (PIXS = high). Time staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High: normal simultaneous even/odd pixel output. Low: time staggered even/odd pixel output. VSYNC 47 O Vertical sync output absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD (DVDD , AVDD , OVDD , PVDD ) 3 3.3 3.6 V Pixel time, t(pixel) (see Note 1) 6.06 40 ns Single-ended analog input termination resistance, RT (see Note 2) 45 50 55 Ω Operating free-air temperature, TA 0 25 70 °C NOTES: 1. t (pixel) is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to t(pixel) when in 1-pixel/clock mode and 2 t(pixel) when in 2-pixel/clock mode. 2. The TFP501 is internally optimized using a laser trim process to precisely fix the single-ended termination impedance, RT, to 50 Ω ±10%.
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) dc digital I/O specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level digital input voltage (CMOS Inputs) (see Note 3) 0.7 VDD V VIL Low level digital input voltage (CMOS Inputs) (see Note 3) 0.3 VDD V V High level digital output voltage (see Note 4) DV DD = 3 V, ST = High, IOH = – 5 mA 2.4 VVOH High level digital output voltage (see Note 4)DV DD = 3 V, ST = Low, IOH = – 3 mA 2.4 V V Low level digital output voltage (see Note 4) DV DD = 3.6 V, ST = High, IOL = 10 mA 0.4 VVOL Low level digital output voltage (see Note 4)DV DD = 3.6 V, ST = Low IOL = 5 mA 0.4 V I High level output drive current (see Note 4) ST = High, V OH = 2.4V –5 –12 –18 mA IOH(D) High level output drive current (see Note 4)ST = Low, V OH = 2.4V –3 –7 –12 mA I Low level output drive current (see Note 4) ST = High, V OL = 0.4V 10 13 19 mA IOL(D) Low level output drive current (see Note 4)ST = Low, V OL = 0.4V 5 7 11 mA IIH High level digital input current (see Note 3)VIH = DVDD ±20 µA IIL Low level digital input current (see Note 3)VIL = 0.0 ±60 µA IOZ Hi-Z output leakage current PD = Low or PDO = Low ±20 µA NOTES: 3. Digital inputs are labeled I in I/O column of Terminal Functions Table. 4. Digital outputs are labeled O in I/O column of Terminal Functions Table. dc specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(1) Analog input differential voltage (see Note 5) 150 1200 mV VIC Analog input common mode voltage (see Note 5) AV DD –0.3 AV DD –0.037 V VI(OC) Open circuit analog input voltage AV DD –0.01 AV DD +0.01 V IDD(2PIX) Normal 2-pix/clock power supply current (see Note 7)ODCK = 82.5 MHz 2-pix/clock 460 mA I(PD) Power down current (see Note 6) PD = Low 10 mA I(PDO) Output drive power down current (see Note 6) PDO = Low 35 mA NOTES: 5. Specified as dc characteristic with no overshoot or undershoot. 6. Analog inputs are open circuit (transmitter is disconnected from TFP501.) 7. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE{23:0] and Q0[23:0] CL = 10 pF.
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ac specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(2) Differential input sensitivity (see Note 8) 150 mVp –p VID(3) Maximum differential input 1560 mVp –p tsk(D) Analog input intra–pair (+ to –) differential skew (see Note 12) 0.4 t(bit)† ns tsk(CC) Analog input inter–pair or channel to channel skew (see Note 12) 1.0 t(pixel)‡ ns Worst case differential input clock jitter tolerance (see Note 9 and 12) 112 MHz, 1 pixel/clock 200 ps t Rise time of data and control signals (see ST = Low, C L = 10 pF 1.9 nstr(1) Rise time of data and control signals (see Notes 10 and 11) ST = High, C L = 10 pF 1.9 ns t Fall time of data and control signals ST = Low, C L = 10 pF 1.9 nstf(1) Fall time of data and control signals (see Notes 10 and 11) ST = High, CL = 10 pF 1.9 ns t Rise time of ODCK clock (see Note 10) ST = Low, C L = 10 pF 1.9 nstr(2) Rise time of ODCK clock (see Note 10) ST = High, CL = 10 pF 1.9 ns t Fall time of ODCK clock (see Note 10) ST = Low, C L = 10 pF 1.9 nstf(2) Fall time of ODCK clock (see Note 10) ST = High, CL = 10 pF 1.9 ns 1 pixel/clock PIXS = Low ST=Low, CL=10 pF 1.2 ns OCK_INV = Low ST=High, CL=10 pF 1.2 ns Setup time data and control signal to falling 2 pixel/clock PIXS = High ST=Low, CL=10 pF 2.7 nstsu(1) Setup time, data and control signal to falling edge of ODCK (see Note 11) STAG = High OCK_INV = Low ST=High, CL=10 pF 2.7 ns 2 pixel & STAG PIXS = High ST=Low, CL=10 pF 1.7 nsSTAG = Low OCK_INV = Low ST=High, CL=10 pF 1.7 ns 1 pixel/clock PIXS = Low ST=Low, CL=10 pF 0.9 ns Hold time data and control signal to falling OCK_INV = Low ST=High, CL=10 pF 0.9 ns th(1) Hold time, data and control signal to falling edge of ODCK (see Note 11) 2 pixel and STAG PIXS = High ST=Low, CL=10 pF 2.9 nsSTAG = Low OCK_INV = Low ST=High, CL=10 pF 2.9 ns † t(bit) is 1/10 the pixel time, t(pixel)‡ t(pixel) is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t(pixel) in 1-pixel/clock mode or 2 t(pixel) when in 2-pixel/clock mode. NOTES: 8. Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. 9. Measured differentially at 50% crossing using ODCK output clock as trigger. 10. Rise and fall times measured as time between 20% and 80% of signal amplitude. 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]. 12. By characterization 13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ac specifications (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1 pixel/clock PIXS = Low ST=Low, CL=10 pF 1.9 ns OCK_INV = High ST=High, CL=10 pF 1.9 ns Setup time data and control signal to 2 pixel/clock PIXS = High ST=Low, CL=10 pF 2.9 nstsu(2) Setup time, data and control signal to rising edge of ODCK (see Note 11) STAG = High OCK_INV = High ST=High, CL=10 pF 2.9 ns 2 pixel & STAG PIXS = High ST=Low, CL=10 pF 2.0 nsSTAG = Low OCK_INV = High ST=High, CL=10 pF 2.0 ns 1 pixel/clock PIXS = Low ST=Low, CL=10 pF 0.5 ns Hold time data and control signal to rising OCK_INV = High ST=High, CL=10 pF 0.5 ns th(2) Hold time, data and control signal to rising edge of ODCK (see Note 11) 2 pixel & STAG PIXS = High ST=Low, CL=10pF 1.4 nsSTAG = Low OCK_INV = High ST=High, CL=10pF 1.4 ns f ODCK frequency PIXS = Low 25 165 MHzf(ODCK) ODCK frequency PIXS = High 12.5 82.5 MHz ODCK duty-cycle 40% 50% 60% td(PDL) Delay from PD low to Hi-Z outputs 18 ns td(PDOL) Delay from PDO low to Hi-Z outputs 18 ns t(HSC) Time between DE transitions to SCDT low (see Note 13) 165 MHz 25 ms tt(FSC) Time from DE low to SCDT high (see Note 13) 8 trans(DE)† td(st) ODCK latching edge to QE[23:0] data output STAG = Low, PIXS = High 0.5 t(pixel) ns † trans(DE) is one transition (low-to-high or high-to-low) of the DE signal. NOTES: 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]. 13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 1. Rise and Fall Time of ODCK Figure 2. Rise and Fall Time of Data and Control Signals Figure 3. ODCK Frequency Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK Figure 5. ODCK High to QE[23:0] Staggered Figure 6. Analog Input Intra-Pair Figure 7. Delay From PD Low to Hi-Z Outputs Figure 8. Delay From PDO Low to Hi-Z Outputs
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The TFP501 is a DVI digital receiver that is used in digital display systems to receive and decode T.M.D.S. encoded RGB pixel data streams. High-bandwidth digital content protection (HDCP) receiver functionality provides decryption of the DVI input data streams encrypted at the transmitter, such as TI’s TFP510 HDCP transmitter, to prevent unauthorized viewing or coping of digital content. In a digital display system a host, usually a PC or consumer electronics device, contains a DVI compatible transmitter that receives 24-bit pixel data along with appropriate control signals. The HDCP TFP510 transmitter encrypts and encodes the signals into a high-speed, low-voltage, differential serial bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a DVI and HDCP compatible receiver like the TI TFP501 to decode and decrypt the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to five meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required. T.M.D.S. pixel data and control signal encoding a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, transmits the character that minimizes the number of transitions, and approximates a dc balance of the transmission line. three channels are also used to receive HSYNC, VSYNC, CTL3, and two user definable control signals, CTL[2:1], during inactive display or blanking interval (DE = Low). The following table maps the received input RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH T.M.D.S. INPUT CHANNEL Output Pins (Valid for DE = High) Red[7:0] Channel – 2 (Rx2 ±) QE[23:16] QO[23:16] Green[7:0] Channel – 1 (Rx1 ±) QE[15:8] QO[15:8] Blue[7:0] Channel – 0 (Rx0 ±) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW T.M.D.S. INPUT CHANNEL OUTPUT PINS (VALID FOR DE = LOW) CTL[3:2] (see Note 13) Channel – 2 (Rx2 ±) CTL2 CTL[1:0] (see Note 13) Channel – 1 (Rx1 ±) CTL1 HSYNC, VSYNC Channel – 0 (Rx0 ±) HSYNC, VSYNC NOTE 14: Some DVI transmitters transmit a CTL0 signal. The TFP501 decodes and transfers CTL[2:1] and ignores CTL0 characters. CTL3 is used internally to enable HDCP decryption. CTL3 and CTL0 are not available as TFP501 outputs. determine the state of active display vs blanking, i.e., state of DE. high-bandwidth digital content protection (HDCP) overview TI’s HDCP transmitters and receivers use up to three cipher engines to protect information that may be externally accessible to the user. The downstream encryption described in the specification high-bandwidth digital content protection system Revision 1.0 is used to protect video data passing from the HDCP transmitter to the HDCP receiver via a DVI link. The HDCP transmitter encrypts video data and the receiver decrypts the data as shown in Figure 13.
respect to lower systems level cost, ease of implementation, high performance, and exceptional security. Figure 13. TI’s HDCP Implementation for PC and Display System -T(pixel) channel-to-channel skew tolerance. high-speed serial data transmission. The TFP501 is designed for high jitter tolerance.
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input channels and is maintained as long as the link remains active. optimum impedance matching to standard DVI cables having a characteristic impedance of 100 Ω .
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TFP501 modes of operation The TFP501 provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. The following table outlines the various panel modes that can be supported along with appropriate external control pin settings. PANEL PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV TFT or 16-bit DSTN 1 pixel/clock Falling Free run 0 0 0 TFT or 16-bit DSTN 1 pixel/clock Rising Free run 0 0 1 TFT 2 pixel/clock Falling Free run 0 1 0 TFT 2 pixel/clock Rising Free run 0 1 1 24-bit DSTN 1 pixel/clock Falling Gated Low 1 0 0 None 1 pixel/clock Rising Gated Low 1 0 1 24-bit DSTN 2 pixel/clock Falling Gated Low 1 1 0 24-bit DSTN 2 pixel/clock Rising Gated Low 1 1 1 TFP501 output driver configurations The TFP501 provides flexibility by offering various output driver features that can be used to optimize power consumption, ground-bounce and power-supply noise. The following sections outline the output driver features and their effects. Output driver power down (PDO = low.) Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. A weak pulldown (approximately 10 µA) gradually pulls these high-impedance outputs to a low level to prevent the outputs from floating. The SCDT output, which indicates link-disabled or link-inactive, can be tied directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin defaults the TFP501 to the normal nonpower-down output drive mode if left unconnected. Drive strength (ST = high for high drive strength, ST = low for low drive strength.) The TFP501 allows for selectable output drive strength on the data, control, and ODCK outputs. See the dc specifications table for the values of I OH and IOL current drives for a given ST state. The high output strength offers approximately two times the drive as the low output drive strength. Time staggered pixel output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high.) Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even pixel is delayed from the latching edge of ODCK by 0.25 T (ODCK) . (T(ODCK) is the period of ODCK. The ODCK period is 2 t(pixel) when in 2-pixel/clock mode.) Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP501 drive strength and staggered pixel options allow flexibility to reduce system power supply noise, ground bounce and EMI. Power management. The TFP501 offers several system power management features. The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry remains active. The TFP501 power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry and output drivers. All output drivers are placed into a high-impedance state. All inputs are disabled except for the PD input. The TFP501 does not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullups so if left unconnected they default the TFP501 to normal operating modes.
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TFP501 output driver configurations (continued) Sync detect. The TFP501 offers an output, SCDT, to indicate link activity. The TFP501 monitors activity on DE to determine if the link is active. When 1 million pixel clock periods pass without a transition on DE, the TFP501 considers the link inactive and SCDT is driven low. SCDT goes high immediately after the first eight transitions on DE. SCDT again goes low when no more transitions are seen after 2 18 oscillator clocks. SCDT can be used to signal a system power management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP501 PDO input to power down the output drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in complete power down, the analog inputs are ignored and the SCDT state does not change. An external, system power management circuit to drive PD is preferred. HDCP register map TFP501 is a standard I2C slave device. All the registers can be written and read through the I2C interface. The I2C base address of TFP501 is dependent on pin 10 (A0) as shown below. Pin 10 Write Address (Hex) Read Address (Hex) 0 74 75 1 76 77 I2C register map BKSV Subaddress = 00 Read Only 7 6 5 4 3 2 1 0 BKSV[7:0] Subaddress = 01 Read Only 7 6 5 4 3 2 1 0 BKSV[15:8] Subaddress = 02 Read Only 7 6 5 4 3 2 1 0 BKSV[23:16] Subaddress = 03 Read Only 7 6 5 4 3 2 1 0 BKSV[31:24] Subaddress = 04 Read Only 7 6 5 4 3 2 1 0 BKSV[39:32]
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I2C register map (continued) Video receiver KSV. This value may be used to determine that the video receiver is HDCP capable. Valid KSVs contain 20 ones and 20 zeros, a characteristic that is verified by video transmitter hardware before encryption is enabled. Ri’ Subaddress = 08 Read Only 7 6 5 4 3 2 1 0 Ri’ [7:0] Subaddress = 09 Read Only 7 6 5 4 3 2 1 0 Ri’ [15:8] Link verification response. Updated every 128th frame. It is recommended that graphics systems protect against errors in the I2C transmission by re-reading this value when unexpected values are received. This value is available at all times between updates. AKSV Subaddress = 10 Read/Write Default = 00 7 6 5 4 3 2 1 0 AKSV[7:0] Subaddress = 11 Read/Write Default = 00 7 6 5 4 3 2 1 0 AKSV[15:8] Subaddress = 12 Read/Write Default = 00 7 6 5 4 3 2 1 0 AKSV[23:16] Subaddress = 13 Read/Write Default = 00 7 6 5 4 3 2 1 0 AKSV[31:24] Subaddress = 14 Read/Write Default = 00 7 6 5 4 3 2 1 0 AKSV[39:32] Video transmitter KSV. Writing to 0x14 triggers the authentication sequence in the device. An Subaddress = 18 Read/Write Default = 00 7 6 5 4 3 2 1 0 An[7:0] Subaddress = 19 Read/Write Default = 00 7 6 5 4 3 2 1 0 An[15:8] Subaddress = 1A Read/Write Default = 00 7 6 5 4 3 2 1 0 An[23:16]
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I2C register map (continued) Subaddress = 1B Read/Write Default = 00 7 6 5 4 3 2 1 0 An[31:24] Subaddress = 1C Read/Write Default = 00 7 6 5 4 3 2 1 0 An[39:32] Subaddress = 1D Read/Write Default = 00 7 6 5 4 3 2 1 0 An[47:40] Subaddress = 1E Read/Write Default = 00 7 6 5 4 3 2 1 0 An[55:48] Subaddress = 1F Read/Write Default = 00 7 6 5 4 3 2 1 0 An[63:56] Session random number. This multibyte value must be written by the graphics system before the KSV is written. Bcaps Subaddress = 40 Read Only Default = 10 7 6 5 4 3 2 1 0 Rsvd Repeater KSV-FIFO Fast Rsvd Rsvd Rsvd Rsvd Bit 6: REPEATER, Video repeater capability. This device is not a repeater. Read as ZERO. Bit 5: READY, KSV FIFO ready. This device does not support repeater capability. Read as ZERO. Bit 4: FAST. This device supports 400 kHz transfers. Read as ONE. Bstatus Subaddress = 41 Read Only Default = 00 7 6 5 4 3 2 1 0 Bstatus[7:0] Subaddress = 42 Read Only Default = 00 7 6 5 4 3 2 1 0 Bstatus[15:8] Bstatus. This device does not support repeater capability. All bytes read as 0x00. KSV_FIFO Subaddress = 43 Read Only Default = 00 7 6 5 4 3 2 1 0 KSV_FIFO Key selection vector FIFO. This device is not a repeater. All bytes read as 0x00.
This read-only register contains the 16-bit device ID for the TFP501. DEV_ID[15:0] is hardwired to 0x0501. This read-only register contains the 8-bit revision ID for the TFP501. REV_ID[7:0] is hardwired to 0x01. Figure 16. I2C Start and Stop Conditions
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generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 17. Figure 17. I2C Access Cycles in Figure 18. The subaddress is autoincremented after each data cycle. cycle as shown in Figure 19. Figure 18. I2C Write Cycle
PZP (S-PQFP-G100) www.ti.com THERMAL PAD MECHANICAL DATA PowerPAD™ PLASTIC QUAD FLATPACK
PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002
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PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK 0,13 NOM Thermal Pad (see Note D) 0,75 0,45 0,25 Seating Plane 4146929/A 04/99 Gage Plane 0,27 0,17 100 SQ SQ 15,80 16,20 14,20 13,80 12,00 TYP 1,05 0,95 1,20 MAX 0,50 M0,08 0,08 0°–/C02577°0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026 PowerPAD is a trademark of Texas Instruments.
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