TFP403PZP

TFP403 TI | Alldatasheet

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TI PanelBus™ DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Supports Pixel Rates Up to 165MHz (Including 1080p and WUXGA at 60 Hz) /C0068Digital Visual Interface (DVI 1.0) Specification Compliant /C0068Pin-for-Pin Compatible With TFP501 for Simple Upgrade Path to HDCP /C0068True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels per Clock /C0068Laser Trimmed (50 Ω) Input Stage for Optimum Fixed Impedance Matching /C0068Skew Tolerant up to One Pixel Clock Cycle (High Clock and Data Jitter Tolerance) /C00684x Over-Sampling for Reduced Bit-Error Rates and Better Performance Over Longer Cables /C0068Reduced Power Consumption—1.8-V Core Operation With 3.3 V I/Os and Supplies3 /C0068Reduced Ground Bounce Using Time Staggered Pixel Outputs /C0068Lowest Noise and Best Power Dissipation Using PowerPAD™ Packaging /C0068Advanced Technology Using TI 0.18-μm EPIC-5™ CMOS Process /C0068Supports Hot Plug Detection

description

The Texas Instruments TFP403 is a PanelBus™ flat panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP403 finds applications in any design requiring high-speed digital interface. The TFP403 supports display resolutions up to 1080p and WUXGA in 24-bit true color pixel format. The TFP403 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time staggered pixel outputs for reduced ground bounce. PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultralow ground inductance. The TFP403 combines PanelBus™ circuit innovation with TIs advanced 0.18- μm EPIC-5™ CMOS process technology, along with PowerPAD ™ package technology to achieve a reliable, low-powered, low-noise, high-speed digital interface solution. 1. The Digital Visual Interface Specification (DVI) is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TFP403 is compliant with the DVI Specification Rev. 1.0. 2. High-bandwidth digital content protection (HDCP) is the system used for protecting DVI outputs from being copied. The TFP501 is TI’s DVI receiver with HDCP functionality. 3. The TFP403 has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies. Copyright © 2002 − 2011, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warrant y, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PanelBus, PowerPAD, and EPIC-5 are trademarks of Texas Instruments.

TI PanelBus™ DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011

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Rx2− RSVD RSVD RSVD RSVD RSVD PGND OCK_INV QO22 QO21 QO20 QO18 QO17 QO16 DGND CAP QO13 QO12 QO9 QO8 OGND QO7 QO6 QO5 QO4 QO3 QO2 DFO PD ST PIXS DGND STAG PDO QE0 QE2 QE4 QE5 QE6 DD OGND QE9 QE11 QE12 QE13 QE7 PZP PACKAGE (TOP VIEW) QO23 QO11 QO15 QO14 OGND QE18 SCDT QE8 QE1 QE3 QE10 QE21 VSYNC QO10 QO19 DD Rx1+ Rx1− Rx0+ Rx0− RxC+ RxC− DDAV DDDV DDDV OV DDOV PV DDOV DDAV DDAV DDAV DDOV DDOV DDPV

TI PanelBus™ DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram + Latch Channel 2 + Latch Channel 1 + Latch Channel 0 + PLL Data Recovery and Synchronization TMDS Decoder CH2(0-9) CH1(0-9) CH0(0-9) Panel Interface RED(0-7) CTL3 CTL2 GRN(0-7) CTL1 BLUE(0-7) VSYNC HSYNC QE(0-23) QO(0-23) ODCK DE SCDT CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50-Ω Termination 3.3 V 3.3 V Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 79 GND Analog ground—Ground reference and current return for analog circuitry AVDD 82,85,88, VDD Analog VDD—Power supply for analog circuitry. Nominally 3.3 V CAP 67 VDD Bypass capacitor—4.7 μF tantalum and 0.01 μF ceramic connected to ground. This capacitor is optional for the TFP403, but is required for the TFP501. CTL[2:1] 41,40 DO General-purpose control signals—Used for user defined control. In normal mode CTL1 is not powered down via PDO. DE 46 DO Output data enable—Used to indicate time of active video display versus nonactive display or blank time. During blank, only HSYNC, VSYNC, and CTL1-2 are transmitted. During times of active display, or nonblank, only pixel data, QE[23:0] and QO[23:0], is transmitted. High : Active display time Low: Blank time DFO 1 DI Output clock data format—Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; otherwise ODCK is held low when DE is low. High : DSTN support/ODCK held low when DE = low Low: TFT support/ODCK runs continuously. DGND 5,39,68 GND Digital ground—Ground reference and current return for digital core DVDD 6,38 VDD Digital VDD—Power supply for digital core. Nominally 3.3 V HSYNC 48 DO Horizontal sync output OCK_INV 100 DI ODCK polarity—Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL1-2 ) are latched Normal mode: High : Latches output data on rising ODCK edge Low : Latches output data on falling ODCK edge

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Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION ODCK 44 DO Output data clock—Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with DE, HSYNC, VSYNC, and CTL[2:1] are synchronized to this clock. OGND 19,28,45, 58,76 GND Output driver ground—Ground reference and current return for digital output drivers OVDD 18,29,43, 57,78 VDD Output driver VDD—Power supply for output drivers. Nominally 3.3 V PD 2 DI Power down—An active low signal that controls the TFP403 power-down state. During power down all output buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are disabled, except for PD If PD is left unconnected an internal pullup will default the TFP403 to normal operation. High : Normal operation Low: Power down PDO 9 DI Output drive power down—An active low signal that controls the power-down state of the output drivers. During output drive powerdown, the output drivers (except SCDT and CTL1) are driven to a high impedance state. A weak pulldown will slowly pull these outputs to a low level. When PDO is left unconnected, an internal pullup defaults the TFP403 to normal operation. High : Normal operation/output drivers on Low: Output drive power down. PGND 98 GND PLL GND—Ground reference and current return for internal PLL PIXS 4 DI Pixel select—Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.) High : 2-pixel/clock Low: 1-pixel/clock PVDD 97 VDD PLL VDD—Power supply for internal PLL. Nominally 3.3 V QE[0:7] 10-17 DO Even blue pixel output—Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0/pin 10 MSB: QE7/pin 17 QE[8:15] 20-27 DO Even green pixel output—Output for even and odd green pixels when in 1-pixel/clock mode. Output for even only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8/pin 20 MSB: QE15/pin 27 QE[16:23] 30-37 DO Even red pixel output—Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16/pin 30 MSB: QE23/pin 37 QO[0:7] 49-56 DO Odd blue pixel output—Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0/pin 49 MSB: QO7/pin 56 QO[8:15] 59-66 DO Odd green pixel output—Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8/pin 59 MSB: QO15/pin 66 QO[16:23] 69-75,77 DO Odd red pixel output—Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16/pin 69 MSB: QO23/pin 77

TI PanelBus™ DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION RSVD 42 DO Reserved. Must be tied high for normal operation RSVD 92−96 AI Reserved. See TFP501 data sheet for intended future use. RxC+ 89 AI Clock positive receiver input—Positive side of reference clock. TMDS low voltage signal differential input pair RxC− 90 AI Clock negative receiver input—Negative side of reference clock. TMDS low voltage signal differential input pair Rx0+ 86 AI Channel-0 positive receiver input—Positive side of channel-0. TMDS low voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank. Rx0− 87 AI Channel-0 negative receiver input—Negative side of channel-0. TMDS low voltage signal differential input pair. Rx1+ 83 AI Channel-1 positive receiver input—Positive side of channel-1 TMDS low voltage signal differential input pair. Channel-1 receives green pixel data in active display and CTL1 control signals in blank. Rx1− 84 AI Channel-1 negative receiver input—Negative side of channel-1 TMDS low voltage signal differential input pair Rx2+ 80 AI Channel-2 positive receiver input—Positive side of channel-2 TMDS low voltage signal differential input pair. Channel-2 receives red pixel data in active display and CTL2 control signals in blank. Rx2− 81 AI Channel-2 negative receiver input—Negative side of channel-2 TMDS low voltage signal differential input pair. SCDT 8 DO Sync detect—Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP403 monitors the state DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: Active link Low: Inactive link ST 3 DI Output drive strength select—Selects output drive strength for high or low current drive. (See dc specifications for IOH and IOL vs ST state.) High : High drive strength Low : Low drive strength STAG 7 DI Staggered pixel select—An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High : Normal simultaneous even/odd pixel output Low: Time staggered even/odd pixel output VSYNC 47 DO Vertical sync output

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absolute maximum ratings over operating free-air temperature (unless otherwise noted) † † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified at maximum allowed operating temperature, 70°C. 2. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70°C. recommended operating conditions MIN TYP MAX UNIT Supply voltage, VDD (DVDD, AVDD, PVDD, OVDD) 3 3.3 3.6 V Pixel time, tpix‡ 6.06 40 ns Single ended analog input termination resistance, Rt 45 50 55 Ω Operating free-air temperature, TA 0 25 70 °C ‡ tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode and 2tpix when in 2-pixel/clock mode.

TI PanelBus™ DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) dc digital I/O specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level digital input voltage† 2 DVDD V VIL Low level digital input voltage† 0 0.8 V I High level output drive current‡ ST = High, VOH = 2.4 V 5 10 18 mAIOH High level output drive current‡ ST = Low, VOH = 2.4 V 3 6 12 mA I Low level output drive current‡ ST = High, VOL = 0.8 V 10 13 19 mAIOL Low level output drive current‡ ST = Low, VOL = 0.8 V 5 7 11 mA IOZ Hi-Z output leakage current PD = Low or PDO = Low −1 1 μA † Digital inputs are labeled DI in I/O column of Terminal Functions Table. ‡ Digital outputs are labeled DO in I/O column of Terminal Functions Table. dc specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID Analog input differential voltage (see Note 3) 75 1200 mv VIC Analog input common mode voltage (see Note 3) AVDD-300 AVDD-37 mv VI(OC) Open circuit analog input voltage AVDD-10 AVDD+10 mv IDD(2PIX) Normal 2-pix/clock power supply current (see Note 4) PIXEL RATE = 82.5 MHz 2-pix/clock 400 mA I(PD) Power down current (see Note 5) PD = Low 10 mA I(PDO) Output drive power down current (see Note 5) PDO = Low 45 mA NOTES: 3. Specified as dc characteristic with no overshoot or undershoot. 4. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. 5. Analog inputs are open circuit (transmitter is disconnected from TFP403).

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ac specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(2) Differential input sensitivity† 150 1560 mVp-p tps Analog input intra-pair (+ to -) differential skew (see Note 6) 0.4 tbit‡ t(ccs) Analog Input inter-pair or channel-to-channel skew (see Note 6) Analog Input inter-pair or channel-to-channel skew (see Note 6) 1 tpix§ t(ijit) Worse case differential input clock jitter tolerance¶ (see Note 6) Worse case differential input clock jitter tolerance¶ (see Note 6) 50 ps tf(1) Fall time of data and control signals#, || ST = Low, C L = 5 pF ST = High, C L = 10 pF 2.4 1.9 ns tr(1) Rise time of data and control signals#, || ST = Low, C L = 5 pF ST = High, C L = 10 pF 2.4 1.9 ns tr(2) Rise time of ODCK clock# ST = Low, C L = 5 pF ST = High, C L = 10 pF 2.4 1.9 ns tf(2) Fall time of ODCK clock# ST = Low, C L = 5 pF ST = High, C L = 10 pF 2.4 1.9 ns tsu(1) Setup time, data, and control signal to falling edge of ODCK 1 pixel, OCK_INV = low||, PIXS = low ST = Low, C L = 5 pF ST = High, C L = 10 pF 1.0 ns Hold time data and control 1 pixel OCK INV = low || ST = Low C L = 5 pFth(1) Hold time, data, and control i l t f lli d f ODCK 1 pixel, OCK_INV = low||, PIXS l ST = Low, C L = 5 pF ST Hi h C 10 F 1.0 nsth(1) signal to falling edge of ODCK PIXS = low ST = High, C L = 10 pF 1.0 ns Setup time data and control 1 pixel OCK INV = high || ST = Low C L = 5 pFtsu(2) Setup time, data, and control i l t i i d f ODCK 1 pixel, OCK_INV = high||, PIXS l ST = Low, C L = 5 pF ST Hi h C 10 F 1.0 nstsu(2) signal to rising edge of ODCK PIXS = low ST = High, C L = 10 pF 1.0 ns th(2) Hold time, data, and control signal to rising edge of ODCK 2 pixel and STAG OCK_INV = high PIXS = high ST = Low, C L = 5 pF ST = High, C L = 10 pF 0.5 ns f ODCK frequency PIX = Low (1-PIX/CLK) 25 165 MHzf(ODCK) ODCK frequency PIX = High (2-PIX/CLK) 12.5 82.5 MHz ODCK duty-cycle 40% 50% 60% tpd(PDL) Propagation delay time from PD low to Hi-Z outputs 9 ns tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs 9 ns tt(HSC) Transition time between DE transition to SCDT low/C0107 1e6 tpix tt(FSC) Transition time between DE transition to SCDT high/C0107 1600 tpix td Delay time, ODCK latching edge to QE[23:0] data output STAG = Low Pixs = High 0.5 tpix † Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection. ‡ tbit is 1/10 the pixel time, tpix § tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t pix in 1-pixel/clock mode or 2t pix when in 2-pixel/clock mode. ¶ Measured differentially at 50% crossing using ODCK output clock as trigger. # Rise and fall times measured as time between 20% and 80% of signal amplitude. || Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1] /C0107Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. NOTE 6: By characterization

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Figure 7. Delay From PD Low to Hi-Z Outputs Figure 8. Delay From PDO Low to Hi-Z Outputs Figure 9. Analog Input Channel-to-Channel Skew Figure 10. Time Between DE Transitions to SCDT Low and SCDT High Figure 11. Minimum DE Low and Maximum DE High

TI PanelBus™ DIGITAL RECEIVER SLDS125B − DECEMBER 2000 − REVISED MAY 2011 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description fundamental operation The TFP403 is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a DVI compatible transmitter that receives 24 bit pixel data along with appropriate control signals. The transmitter encodes them into a high-speed low-voltage differential serial bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a DVI compatible receiver like the TI TFP403 to decode the serial bit stream back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to UXGA a high bandwidth receiver with good jitter and skew tolerance is required. TMDS pixel data and control signal encoding TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent and transmits the character that will minimize the number of transitions and approximate a dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[2:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The following table maps the received input data to appropriate TMDS input channel in a DVI compliant system. RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH INPUT CHANNEL OUTPUT PINS (VALID FOR DE = HIGH) Red[7:0] Channel – 2 (Rx2 ±) QE[23:16] QO[23:16] Green[7:0] Channel – 1 (Rx1 ±) QE[15:8] QO[15:8] Blue[7:0] Channel – 0 (Rx0 ±) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW INPUT CHANNEL OUTPUT PINS (VALID FOR DE = LOW) CTL[3:2] (see Note 7) Channel – 2 (Rx2 ±) CTL2 CTL[1: 0] (see Note 7) Channel – 1 (Rx1 ±) CTL1 HSYNC, VSYNC Channel – 0 (Rx0 ±) HSYNC, VSYNC NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP403 decodes and transfers CTL[2:1] and ignores CTL0 characters. CTL3 is used internally to enable HDCP decryption. CTL3 and CTL0 are not available as TFP501 outputs. The TFP403 discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking, i.e., state of DE.

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The TFP403 receives a clock reference from the DVI transmitter that has a period equal to the pixel time, Tpix. the TFP403s design for high jitter tolerance. for each of the three input channels and is maintained as long as the link remains active. normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets. to standard 50-Ω DVI cables. internal resistor, which is matched to the cable impedance, at the TFP403 input provides a pullup to AV DD. Figure 13. The TFP403 is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common mode voltages ranging from (AVDD-300 mV) to (AVDD-37 mV).

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detailed description (continued) TFP403 output driver configurations The TFP403 provides flexibility by offering various output driver features that can be used to optimize power consumption, ground-bounce, and power-supply noise. The following sections outline the output driver features and their effects. Output driver power down (PDO = low), Pulling PDO low will place all the output drivers, except CTL1 and SCDT, into a high-impedance state. The SCDT output which indicates link-disabled or link-inactive can be tied directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin will default the TFP403 to the normal nonpower down output drive mode if left unconnected. Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP403 allows for selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for the values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two times the drive as the low output drive strength. Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period is 2Tpix when in 2-pixel/clock mode.) Depending on system constraints of output load, pixel rate, panel input architecture and board cost the TFP403 drive strength and staggered pixel options allow flexibility to reduce system power-supply noise, ground bounce and EMI. Power Management. The TFP403 offers several system power management features. The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high impedance state while the rest of the device circuitry remains active The TFP403 power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the PD input. The TFP403 will not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullup so if left unconnected they will default the TFP403 to normal operating modes. Sync Detect. The TFP403 offers an output, SCDT to indicate link activity. The TFP403 monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP403 considers the link inactive and SCDT is driven low. The SCDT goes high immediately after the first transition on DE. The SCDT again becomes low when no more transitions are seen after 218 ocillator clocks. SCDT can be used to signal a system power management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP403 PDO input to power down the output drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in complete power down, the analog inputs are ignored and the SCDT state does not change. An external system power management circuit to drive PD is preferred.

designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. required thermally, as the device power dissipation is well within the package capability when not soldered. Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations. package is included only for reference. Table 1. TI 100-TQFP (14 × 14 × 1 mm)/0.5 mm Lead Pitch † Specified with 2 oz. Cu PCB plating. § Measured at ambient temperature, TA = 70°C.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TFP403PZP Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP403PZP TFP403PZP.A Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP403PZP TFP403PZPG4 Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TFP403PZP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TFP403PZP PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 20.3 15.4 15.45 TFP403PZPG4 PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 20.3 15.4 15.45 Pack Materials-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. TQFP - 1.2 mm max height TM PowerPAD PZP 100 PLASTIC QUAD FLATPACK14 x 14 mm Pkg Body, 0.5 mm pitch 16 x 16 mm Pkg Area 4224739/B

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