TFP401APZPG4

TFP401_16 TI1 | Alldatasheet

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Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 TFP401xTIPanelBus™ DigitalReceiver (1) The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TPF401 and TFP401A are compliant with the DVI Specification Rev. 1.0. (2) The TFP401/401A has an internal voltage regulator that provides the 1.8-V core power supply from the external 3.3-V supplies. (3) The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal.

1 Features

1• Supports Pixel Rates up to 165 MHz (Including 1080p and WUXGA at 60 Hz)

• Digital Visual Interface (DVI) Specification Compliant (1)
• True-Color, 24-Bit/Pixel, 16.7M Colors at 1 or 2 Pixels per Clock
• Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching
• Skew Tolerant up to One Pixel-Clock Cycle
• 4× Oversampling
• Reduced Power Consumption – 1.8-V Core Operation With 3.3-V I/Os and Supplies (2)
• Reduced Ground Bounce Using Time-Staggered Pixel Outputs
• Low Noise and Good Power Dissipation Using TI PowerPAD™ Packaging
• Advanced Technology Using TI 0.18-µm EPIC-5 CMOS Process
• TFP401A Incorporates HSYNC Jitter Immunity (3)

2 Applications

• High-Definition TV
• HD PC Monitors
• Digital Video
• HD Projectors
• DVI/HDMI Receivers (HDMI Video-Only)

3 Description

The Texas Instruments TFP401 and TFP401A are TI PanelBus™ flat-panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401/401A finds applications in any design requiring high-speed digital interface. The TFP401 and TFP401A supports display resolutions up to 1080p and WUXGA in 24-bit true- color pixel format. The TFP401/401A offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time-staggered pixel outputs for reduced ground bounce. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TFP401 HTQFP (100) 14.00 mm × 14.00 mm TFP401A (1) For all available packages, see the orderable addendum at the end of the datasheet. TFP401 Diagram

TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 www.ti.com Product Folder Links: TFP401 TFP401A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Table of Contents

14 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision F (February 2015) to Revision G Page Changes from Revision E (July 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

51525354555657585960616263646566676869707172737475 25242322212019181716151413121 110987654321 QO1 QO0 HSYNC DE ODCK OVDD CTL3 CTL2 CTL1 GND DVDD QE23 QE22 QE20 QE19 QE17 QE16 OVDD OGND QE15 QE14 OGND OVDD AGND Rx2+ Rx2− A VDD AGND A VDD Rx1− AGND AGND Rx0+ Rx0− AGND RxC+ RxC− A VDD EXT_RES PGND RSVD OCK_INV QO22 QO21 QO20QO18 QO17 QO16 GND DVDD QO13 QO12 QO9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2 DFOPDST PIXSGNDDVDDST AGPDOQE0 QE2 QE3 QE4 QE5 QE6 OVDDOGND QE9 QE1 1QE12 QE13QE7 QO23 A VDD QO1 1QO15 QO14 OGND QE18 SCDT QE8QE1 QE10 QE21 VSYNC QO10QO19 Rx1+ PVDD TFP401,TFP401A www.ti.com SLDS120G –MARCH 2000–REVISED MAY 2016 Product Folder Links: TFP401 TFP401A Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated

5 Description (Continued)

PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultralow ground inductance. The TFP401 and TFP401A combines PanelBus circuit innovation with TI's advanced 0.18-µm EPIC-5 CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low-noise, high-speed digital interface solution.

6 Pin Configuration and Functions

NAME NO. AGND 79, 83, 87, 89, 92 GND Analog ground – Ground reference and current return for analog circuitry AVDD 82, 84, 88, 95 VDD Analog VDD – Power supply for analog circuitry. Nominally 3.3 V CTL[3:1] 42, 41, 40 DO General-purpose control signals – Used for user-defined control. CTL1 is not powered down via PDO. DE 46 DO Output data enable – Used to indicate time of active video display versus non-active display or blank time. During blank, only HSYNC, VSYNC, and CTL[3:1] are transmitted. During times of active display, or non-blank, only pixel data, QE[23:0], and QO[23:0] are transmitted. High: Active display time Low: Blank time

TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 www.ti.com Product Folder Links: TFP401 TFP401A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. DFO 1 DI Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low. High: DSTN support/ODCK held low when DE = low Low: TFT support/ODCK runs continuously. DGND 5, 39, 68 GND Digital ground – Ground reference and current return for digital core DVDD 6, 38, 67 VDD Digital VDD – Power supply for digital core. Nominally 3.3 V EXT_RES 96 AI Internal impedance matching – The TFP401/401A is internally optimized for impedance matching at 50 Ω. An external resistor tied to this pin has no effect on device performance. HSYNC 48 DO Horizontal sync output RSVD 99 DI Reserved. Must be tied high for normal operation OVDD 18, 29, 43, 57, 78 VDD Output driver VDD – Power supply for output drivers. Nominally 3.3 V ODCK 44 DO Output data clock – Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], are synchronized to this clock. OGND 19, 28, 45, 58, 76 GND Output driver ground – Ground reference and current return for digital output drivers OCK_INV 100 DI ODCK polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[3:1]) are latched. Normal mode: High: Latches output data on rising ODCK edge Low: Latches output data on falling ODCK edge PD 2 DI Power down – An active-low signal that controls the TFP401/401A power-down state. During power down, all output buffers are switched to a high-impedance state. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High : Normal operation Low: Power down PDO 9 DI Output drive power down – An active-low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High: Normal operation/output drivers on Low: Output drive power down PGND 98 GND PLL GND – Ground reference and current return for internal PLL PIXS 4 DI Pixel select – Selects between one- and two-pixels-per-clock output modes. During the 2- pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel). High: 2-pixel/clock Low: 1-pixel/clock PVDD 97 VDD PLL VDD – Power supply for internal PLL QE[8:15] 20–27 DO Even green-pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even-only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8/pin 20 MSB: QE15/pin 27 QE[16:23] 30–37 DO Even red-pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even-only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16/pin 30 MSB: QE23/pin 37 QO[0:7] 49–56 DO Odd blue-pixel output – Output for odd-only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0/pin 49 MSB: QO7/pin 56

TFP401,TFP401A www.ti.com SLDS120G –MARCH 2000–REVISED MAY 2016 Product Folder Links: TFP401 TFP401A Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. QO[8:15] 59–66 DO Odd green-pixel output – Output for odd-only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8/pin 59 MSB: QO15/pin 66 QO[16:23] 69–75, 77 DO Odd red-pixel output – Output for odd-only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16/pin 69 MSB: QO23/pin 77 QE[0:7] 10–17 DO Even blue-pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even-only blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0/pin 10 MSB: QE7/pin 17 RxC+ 93 AI Clock positive receiver input – Positive side of reference clock. TMDS low-voltage signal differential input pair RxC– 94 AI Clock negative receiver input – Negative side of reference clock. TMDS low-voltage signal differential input pair Rx0+ 90 AI Channel-0 positive receiver input – Positive side of channel-0. TMDS low-voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank. Rx0– 91 AI Channel-0 negative receiver input – Negative side of channel-0. TMDS low-voltage signal differential input pair Rx1+ 85 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal differential input pair Channel-1 receives green-pixel data in active display and CTL1 control signals in blank. Rx1– 86 AI Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal differential input pair Rx2+ 80 AI Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal differential input pair Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank. Rx2– 81 AI Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal differential input pair SCDT 8 DO Sync detect - Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP401/401A monitors the state of DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: Active link Low: Inactive link ST 3 DI Output drive strength select – Selects output drive strength for high- or low-current drive. (See dc specifications for IOH and IOL vs ST state). High: High drive strength Low: Low drive strength STAG 7 DI Staggered pixel select – An active-low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High: Normal simultaneous even/odd pixel output Low: Time-staggered even/odd pixel output VSYNC 47 DO Vertical sync output

TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 www.ti.com Product Folder Links: TFP401 TFP401A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Specified with PowerPAD bond pad on the backside of the package soldered to a 2-oz. (0.071-mm thick) Cu plate PCB thermal plane. Specified at maximum allowed operating temperature, 70°C. (3) PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70°C.

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT DVDD, AVDD, OVDD, PVDD Supply voltage –0.3 4 V VI Input voltage range, logic/analog signals –0.3 4 V Operating ambient temperature 0 70 °C Package power dissipation/PowerPAD package Soldered(2) 4.3 W Not soldered(3) 2.7 JEDEC latchup (EIA/JESD78) 100 mA Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1- pixel/clock mode and 2tpix when in 2-pixel/clock mode.

7.3 Recommended Operating Conditions

VDD (DVDD, AVDD, PVDD, OVDD) Supply voltage 3 3.3 3.6 V tpix (1) Pixel time 6.06 40 ns Rt Single-ended analog-input termination resistance 45 50 55 Ω TA Operating free-air temperature 0 25 70 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) TFP401, TFP401A UNITPZP (HTQFP)

100 PINS

RθJA Junction-to-ambient thermal resistance 26 °C/W RθJC(top) Junction-to-case (top) thermal resistance 12.3 RθJB Junction-to-board thermal resistance 7.3 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 7.2 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.6

TFP401,TFP401A www.ti.com SLDS120G –MARCH 2000–REVISED MAY 2016 Product Folder Links: TFP401 TFP401A Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated (1) Digital inputs are labeled DI in I/O column of Terminal Functions table. (2) Digital outputs are labeled DO in I/O column of Terminal Functions table.

7.5 DC Digital I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level digital input voltage(1) 2 DVDD V VIL Low-level digital input voltage(1) 0 0.8 V IOH High-level output drive current(2) ST = high, VOH = 2.4 V 5 10 14 mA ST = low, VOH = 2.4 V 3 6 9 IOL Low-level output drive current(2) ST = high, VOL = 0.8 V 10 13 19 mA ST = low, VOL = 0.8 V 5 7 11 IOZ Hi-Z output leakage current PD = low or PDO = low –1 1 μA (1) Specified as dc characteristic with no overshoot or undershoot (2) Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. (3) Analog inputs are open circuit (transmitter is disconnected from TFP401/401A).

7.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID Analog input differential voltage(1) 75 1200 mV VIC Analog input common-mode voltage(1) AVDD – 300 AVDD – 37 mV VI(OC) Open-circuit analog input voltage AVDD – 10 AVDD + 10 mV IDD(2PIX) Normal 2-pix/clock power supply current (2) ODCK = 82.5 MHz, 2-pix/clock 370 mA IPD Power-down current (3) PD = low 10 mA IPDO Output drive power-down current(3) PDO = low 35 mA (1) Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. (2) By characterization (3) tbit is 1/10 the pixel time, tpix (4) tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode. (5) Measured differentially at 50% crossing using ODCK output clock as trigger (6) Rise and fall times measured as time between 20% and 80% of signal amplitude. (7) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].

7.7 AC Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(2) Differential input sensitivity(1) 150 1560 mVp-p tps Analog input intra-pair (+ to –) differential skew(2) 0.4 tbit (3) tccs Analog input inter-pair or channel-to-channel skew (2) 1 tpix (4) tijit Worst-case differential input clock jitter tolerance(2)(5) 50 ps tf1 Fall time of data and control signals(6)(7) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tr1 Rise time of data and control signals(6)(7) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tr2 Rise time of ODCK clock(6) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9 tf2 Fall time of ODCK clock(6) ST = low, CL = 5 pF 2.4 ns ST = high, CL = 10 pF 1.9

TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 www.ti.com Product Folder Links: TFP401 TFP401A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (8) Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. tsu1 Setup time, data and control signal to falling edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = low 1.8 ns2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 3.8 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low 0.7 th1 Hold time, data and control signal to falling edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = low 0.6 ns2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low 2.5 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 2.9 tsu2 Setup time, data and control signal to rising edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = high 2.1 ns2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 4 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 1.5 th2 Hold time, data and control signal to rising edge of ODCK 1 pixel/clock, PIXS = low, OCK_INV = high 0.5 ns2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 2.4 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 2.1 fODCK ODCK frequency PIX = low (1-PIX/CLK) 25 165 MHz PIX = high (2-PIX/CLK) 12.5 82.5 ODCK duty-cycle 40% 50% 60% tpd(PDL) Propagation delay time from PD low to Hi-Z outputs 9 ns tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs 9 ns tt(HSC) Transition time between DE transition to SCDT low(8) 1e6 tpix tt(FSC) Transition time between DE transition to SCDT high(8) 1600 tpix td(st) Delay time, ODCK latching edge to QE[23:0] data output STAG = low, PIXS = high 0.25 tpix tWL(PDL_MIN) Minimum time PD is asserted low 9 ns tDEL Minimum DE low 128 Tpixel

7.8 Typical Characteristics

Figure 1. Imax vs Input Frequency

8 Parameter Measurement Information

Figure 2. Rise and Fall Times of Data and Control Signals Figure 3. Rise and Fall Times of ODCK Figure 4. ODCK Frequency Figure 5. Data Setup and Hold Times to Rising and Falling Edges of ODCK Figure 6. ODCK High to QE[23:0] Staggered Data Figure 7. Analog Input Intra-Pair Differential Skew Figure 8. Delay From PD Low to Hi-Z Outputs Figure 9. Delay From PDO Low to Hi-Z Outputs Figure 10. Delay From PD Low to High Before Figure 11. Minimum Time PD Low

+ Latch Channel 2 + Latch Channel 1 + Latch Channel 0 + PLL Data Recovery and Synchronization TMDS Decoder CH2(0-9) CH1(0-9) CH0(0-9) Panel Interface RED(0-7) CTL3 CTL2 GRN(0-7) CTL1 BLU(0-7) VSYNC HSYNC QE(0-23) QO(0-23) ODCK DE SCDT CTL3 CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50-W Termination 3.3 V 3.3 V Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- Copyright © 2016, Texas Instruments Incorporated TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 www.ti.com Product Folder Links: TFP401 TFP401A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The TFP401/401A is a digital visual interface (DVI)-compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a TMDS-compatible transmitter that receives 24-bit pixel data along with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a TMDS-compatible receiver like the TI TFP401/401A to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat-panel drive circuitry to produce an image on the display. Because the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 TMDS Pixel Data and Control Signal Encoding

TMDS stands for transition-minimized differential signaling. Only one of two possible TMDS characters for a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. Table 1 maps the received input data to the appropriate TMDS input channel in a DVI-compliant system.

and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output. Table 1. TMDS Pixel Data and Control Signal Encoding determine the state of active display versus blanking, i.e., the state of DE.

9.3.2 TFP401/401A Clocking and Data Synchronization

design for high jitter tolerance. each of the three input channels and is maintained as long as the link remains active.

9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching

impedance matching to standard 50-Ω DVI cables. ranging from 150 mV to 1.56 V with common-mode voltages ranging from (AVDD – 300 mV) to (AVDD – 37 mV).

Figure 15. TMDS Differential Input and Transmitter Connection Figure 16. TMDS Inputs

9.3.4 TFP401A Incorporates HSYNC Jitter Immunity

displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem. data synchronization at the input of the display timing controller. between monitor and panel modules).

Figure 17. HSYNC Regeneration Timing Diagram

9.4 Device Functional Modes

9.4.1 TFP401/401A Modes of Operation

panel modes that can be supported, along with appropriate external control pin settings. Table 2. TFP401/401A Modes of Operation

9.4.2 TFP401/401A Output Driver Configurations

9.4.2.1 Output Driver Power Down

(PDO = low). Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. defaults the TFP401/401A to the normal nonpower-down output drive mode if left unconnected.

9.4.2.2 Drive Strength

times the drive as the low-output drive strength.

TFP401,TFP401A SLDS120G –MARCH 2000–REVISED MAY 2016 www.ti.com Product Folder Links: TFP401 TFP401A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated

9.4.2.3 Time-Staggered Pixel Output

This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low time- staggers the even- and odd-pixel outputs so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixel/clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 tcip. (tcip is the period of ODCK. The ODCK period is 2 tpix when in 2- pixel/clock mode). Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP401/401A drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise, ground bounce, and EMI.

9.4.2.4 Power Management

The TFP401/401A offers several system power-management features. The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry remains active. The TFP401/401A power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the PD input. The TFP401/401A does not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullups, so if left unconnected they default the TFP401/401A to normal operating modes.

9.4.2.5 Sync Detect

The TFP401/401A offers an output, SCDT, to indicate link activity. The TFP401/401A monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP401/401A considers the link inactive, and SCDT is driven low. While SCDT is low, if two DE transitions are detected within 1600 pixel clock periods, the link is considered active, and SCDT is pulled high. SCDT can be used to signal a system power management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP401/401A PDO input to power down the output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external system power-management circuit to drive PD is preferred.

10 Applications and Implementation

validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.2 Typical Application

Figure 18. Typical Application

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters

10.2.2 Detailed Design Procedure

10.2.2.1 Data and Control Signals

The trace length of data and control signals out of the receiver should be kept as close to equal as possible. (longer traces can be acceptable).

• ER = 4.35
• Relative permittivity of 50% resin FR-4 @ 1 GHz
• Delay = 177 pS/inch (1) Length of rising edge = TR(picoseconds) ÷ Delay where
• TR = 3 nS
• = 3000 ps ÷ 177 ps per inch
• = 16.9 inches (2) Length of rising edge ÷ 6 = Max length of trace for lumped circuit where

Figure 19. Data and Control Signals Design

10.2.2.2 Configuration Options

byte/clock, 2-bytes/clock, falling/rising clock edge. You can leave place holders for future configuration changes. Figure 20. Configuration Options Design

10.2.2.3 Power Supplies Decoupling

Figure 21. Power Supplies Decoupling Design

10.2.3 Application Curve

between the 18-bit GPU and a 24-bit LCD where “x”and “y”represent the 2 LSB of the panel. Figure 22. 16-bit GPU to 24-bit LCD Figure 23. 18-bit GPU to 24-bit LCD

11 Power Supply Recommendations

• DVDD: Place one 0.01 uF capacitor as close as possible between each DVDD device pin (Pins 6, 38, 67) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor.
• OVDD: Place one 0.01 uF capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43, 57, 78) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor.
• AVDD: Place one 0.01 uF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88, 95) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor.
• PVCC: Place three 0.01 uF capacitors in parallel as close as possible between the PVDD device pin (Pin 97) and ground. A 22 uF tantalum capacitor should be placed between the supply and 0.01 uF capacitors. A ferrite bead should be used between the source and the 22 uF capacitor.

12 Layout

12.1 Layout Guidelines

12.1.1 Layer Stack

Figure 24. Layer Stack

12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)

PCBs are only 20-50%, and 99.9% is the value of a well-balanced twisted pair cable. all route directly from the DVI connector pins to the device, no external components are needed.

12.1.3 DVI Connector

connector, minimizing the via capacitance is the goal.

12.2 Layout Example

Figure 25. DVI Connector Routing

Keep data lines as far as possible from each other. Figure 26. Data Lines Routing

Connect the thermal pad to ground. Figure 27. Ground Routing

13 Device and Documentation Support

13.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 4. Related Links

13.2 Trademarks

PowerPAD, PanelBus are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14.1 TI PowerPAD 100-TQFP Package

Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations. package is included only for reference.

(2) Airflow is at 0 LFM (0 m/s) (no airflow). Table 5. TI 100-TQFP (14 mm × 14 mm × 1 mm) / 0.5-mm Lead Pitch

www.ti.com 11-May-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TFP401APZP ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401APZPG4 ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TFP401APZP TFP401PZP ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TFP401PZP TFP401PZPG4 ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TFP401PZP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 11-May-2016 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TFP401A :

• Automotive: TFP401A-Q1
• Enhanced Product: TFP401A-EP NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

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