TFP401A-EP TI | Alldatasheet

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www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 TIPanelBus™DIGITALRECEIVER Check forSamples: TFP401A-EP 1FEATURES SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS 2• Supports PixelRates Up to165 MHz (including 1080p and WUXGA at60Hz) • ControlledBaseline

  • DigitalVisualInterface(DVI)Specification • One Assembly/TestSite Compliant (1)
  • One FabricationSite
  • True-Color,24 Bit/Pixel,16.7M ColorsatOne • AvailableinMilitary(–55°C/125°C)or Two PixelsPer Clock Temperature Range (Custom temperature
  • Laser Trimmed InternalTerminationResistors ranges available) forOptimum FixedImpedance Matching • Extended Product LifeCycle
  • Skew TolerantUp toOne PixelClock Cycle • Extended Product-Change Notification
  • 4x Over-Sampling • Product Traceability
  • Reduced Power Consumption -1.8V Core OperationWith 3.3V I/Osand Supplies(2)

DESCRIPTION

  • Reduced Ground Bounce Using The Texas InstrumentsTFP401A isa TIPanelBus ™Time-StaggeredPixelOutputs flatpanel displayproduct,partof a comprehensive
  • Low Noise and Power DissipationUsing TI familyof end-to-endDVI 1.0 compliantsolutions. PowerPAD ™ Packaging Targeted primarilyat desktop LCD monitorsand digitalprojectors,the TFP401A findsapplicationsin• Advanced Technology Using TI0.18-mm any designrequiringhigh-speeddigitalinterface.TheEPIC-5™ CMOS Process TFP401A supportsdisplayresolutionsup to 1080p• TFP401A IncorporatesHSYNC Jitter and WUXGA in 24-bittruecolorpixelformat.TheImmunity (3) TFP401A offersdesignflexibilityto driveone or two pixelsper clock,supportsTFT or DSTN panels,and providesan optionfortime staggeredpixeloutputs forreduced ground bounce.PowerPAD ™ advanced packagingtechnologyresultsinbestof classpower (1) The DigitalVisualInterfaceSpecification,DVI,isan industry dissipation,footprint,and ultra-low groundstandarddevelopedby theDigitalDisplayWorkingGroup inductance.The TFP401A combines PanelBus ™(DDWG) forhigh-speeddigitalconnectiontodigitaldisplays. circuitinnovationwith TI's advanced 0.18-mmThe TFP401A iscomplianttotheDVI SpecificationRev.1.0. (2) The TFP401A has an internalvoltageregulatorthatprovides EPIC-5™ CMOS processtechnology,along withTI the1.8-Vcorepower supplyfromtheexternallysupplied PowerPAD ™ package technology to achieve a 3.3-Vsupplies. reliable,low-powered,low-noise,high-speeddigital(3) The TFP401A incorporatesadditionalcircuitrytocreatea interfacesolution.stableHSYNC fromDVI transmittersthatintroduce undesirablejitteron thetransmittedHSYNC signal. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PanelBus,PowerPAD, EPIC-5 aretrademarksofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

Rx2− AVDD AGND AVDD Rx1− AGND AGND Rx0+ Rx0− AGND RxC+ RxC− AVDD EXT_RES PGND RSVD OCK_INV QO22 QO21 QO20 QO18 QO17 QO16 GND DVDD QO13 QO12 QO9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2 DFO PD ST PIXS GND DVDD STAG PDO QE0 QE2 QE3 QE4 QE5 QE6 OVDD OGND QE9 QE11 QE12 QE13 QE7 100-PIN PACKAGE (TOP VIEW) QO23 AVDD QO11 QO15 QO14 OGND QE18 SCDT QE8 QE1 QE10 QE21 VSYNC QO10 QO19 Rx1+ PVDD TFP401A-EP SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com ORDERING INFORMATION (1) PACKAGED DEVICE (2) TA 100-TQFP (PZP) –55°C to125°C TFP401AMPZPEP (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI Web siteatwww.ti.com. (2) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB designguidelinesareavailableat www.ti.com/sc/package.

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+ Latch Channel 2 + Latch Channel 1 + Latch Channel 0 + PLL Data Recovery and Synchronization TMDS Decoder CH2(0-9) CH1(0-9) CH0(0-9) Panel Interface RED(0-7) CTL3 CTL2 GRN(0-7) CTL1 BLU(0-7) VSYNC HSYNC QE(0-23) QO(0-23) ODCK DE SCDT CTL3 CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50-Ω Termination 3.3 V 3.3 V Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- TFP401A-EP www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 FUNCTIONAL BLOCK DIAGRAM TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AGND 79,83,87,89,92 GND AnalogGround -Ground referenceand currentreturnforanalogcircuitry. AV DD 82,84,88,95 VDD AnalogVDD -Power supplyforanalogcircuitry.Nominally3.3V General-purposecontrolsignals-Used foruserdefinedcontrol.CTL1 isnotpowered-downCTL[3:1] 42,41,40 DO viaPDO. Outputdataenable-Used toindicatetimeofactivevideodisplayversusnon-activedisplay orblanktime.Duringblank,onlyHSYNC, VSYNC, and CTL1-3 aretransmitted.Duringtimes DE 46 DO ofactivedisplay,ornon-blank,onlypixeldata,QE[23:0]and QO[23:0],istransmitted. High:Activedisplaytime Low: Blanktime Outputclockdataformat-Controlstheoutputclock(ODCK) formatforeitherTFT orDSTN panelsupport.ForTFT supportODCK clockrunscontinuously.ForDSTN supportODCK DFO 1 DI onlyclockswhen DE ishigh,otherwiseODCK isheldlowwhen DE islow. High:DSTN support/ODCKheldlowwhen DE = low Low: TFT support/ODCKrunscontinuously. DGND 5,39,68 GND Digitalground-Ground referenceand currentreturnfordigitalcore DV DD 6,38,67 VDD DigitalVDD -Power supplyfordigitalcore.Nominally3.3V Internalimpedance matching-The TFP401A isinternallyoptimizedforimpedance matchingEXT_RES 96 AI at50 W. An externalresistortiedtothispinhas no effecton deviceperformance. HSYNC 48 DO Horizontalsyncoutput RSVD 99 DI Reserved.Must be tiedhighfornormaloperation. OV DD 18,29,43,57,78 VDD OutputdriverVDD -Power supplyforoutputdrivers.Nominally3.3V Outputdataclock-Pixelclock.AllpixeloutputsQE[23:0]and QO[23:0](ifin2-pixel/clockODCK 44 DO mode) alongwithDE, HSYNC, VSYNC and CTL[3:1]aresynchronizedtothisclock. OGND 19,28 ,45,58,76 GND Outputdriverground-Ground referenceand currentreturnfordigitaloutputdrivers ODCK Polarity-SelectsODCK edge on whichpixeldata(QE[23:0]and QO[23:0])and controlsignals(HSYNC, VSYNC, DE, CTL1-3 )arelatched. OCK_INV 100 DI Normal Mode: High:Latchesoutputdataon risingODCK edge Low :Latchesoutputdataon fallingODCK edge Copyright© 2009–2011,Texas InstrumentsIncorporated 3

SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. Power down -An activelowsignalthatcontrolstheTFP401A power-down state.During power down alloutputbuffersareswitchedtoa highimpedance state.Allanalogcircuitsare powered down and allinputsaredisabled,exceptforPD.PD 2 DI IfPD isleftunconnectedan internalpullupdefaultstheTFP401A tonormaloperation. High:Normal operation Low: Power down Outputdrivepower down -An activelowsignalthatcontrolsthepower-down stateofthe outputdrivers.Duringoutputdrivepower down, theoutputdrivers(exceptSCDT and CTL1) aredriventoa highimpedance state.When PDO isleftunconnected,an internalpullupPDO 9 DI defaultstheTFP401A tonormaloperation. High:Normal operation/outputdriverson Low: Outputdrivepower down. PGND 98 GND PLL GND -Ground referenceand currentreturnforinternalPLL Pixelselect-Selectsbetween one ortwo pixelsperclockoutputmodes. Duringthe 2-pixel/clockmode, botheven pixels,QE[23:0],and odd pixels,QO[23:0],areoutputin tandem on a givenclockcycle.During1-pixel/clock,even and odd pixelsareoutput sequentially,one ata time,withtheeven pixelfirst,on theeven pixelbus,QE[23:0].(ThePIXS 4 DI firstpixelperlineispixel-0,theeven pixel.The second pixelperlineispixel-1,theodd pixel). High:2-pixel/clock Low: 1-pixel/clock PV DD 97 VDD PLL VDD -Power supplyforinternalPLL Even greenpixeloutput-Outputforeven and odd greenpixelswhen in1-pixel/clockmode. Outputforeven onlygreenpixelwhen in2-pixel/clockmode. Outputdataissynchronizedto QE[8:15] 20-27 DO theoutputdataclock,ODCK. LSB: QE8/pin20 MSB: QE15/pin27 Even redpixeloutput-Outputforeven and odd redpixelswhen in1-pixel/clockmode. Outputforeven onlyredpixelwhen in2-pixel/clockmode. Outputdataissynchronizedtothe QE[16:23] 30-37 DO outputdataclock,ODCK. LSB: QE16/pin30 MSB: QE23/pin37 Odd bluepixeloutput-Outputforodd onlybluepixelwhen in2-pixel/clockmode. Not used, and heldlow,when in1-pixel/clockmode. Outputdataissynchronizedtotheoutputdata QO[0:7] 49-56 DO clock,ODCK. LSB: QO0/pin49 MSB: QO7/pin56 Odd greenpixeloutput-Outputforodd onlygreenpixelwhen in2-pixel/clockmode. Not used,and heldlow,when in1-pixel/clockmode. Outputdataissynchronizedtotheoutput QO[8:15] 59-66 DO dataclock,ODCK. LSB: QO8/pin59 MSB: QO15/pin66 Odd redpixeloutput-Outputforodd onlyredpixelwhen in2-pixel/clockmode. Not used, and heldlow,when in1-pixel/clockmode. Outputdataissynchronizedtotheoutputdata QO[16:23] 69-75,77 DO clock,ODCK. LSB: QO16/pin69 MSB: QO23/pin77 Even bluepixeloutput-Outputforeven and odd bluepixelswhen in1-pixel/clockmode. Outputforeven onlybluepixelwhen in2-pixelperclockmode. Outputdataissynchronized QE[0:7] 10-17 DO totheoutputdataclock,ODCK. LSB: QE0/pin10 MSB: QE7/pin17 Clockpositivereceiverinput-Positivesideofreferenceclock.TMDS lowvoltagesignalRxC+ 93 AI differentialinputpair. Clocknegativereceiverinput-Negativesideofreferenceclock.TMDS lowvoltagesignalRxC- 94 AI differentialinputpair. Channel-0positivereceiverinput-Positivesideofchannel-0.TMDS lowvoltagesignal differentialinputpair.Rx0+ 90 AI Channel-0receivesbluepixeldatainactivedisplayand HSYNC, VSYNC controlsignalsin blank.

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www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. Channel-0negativereceiverinput-Negativesideofchannel-0.TMDS lowvoltagesignalRx0- 91 AI differentialinputpair. Channel-1positivereceiverinput-Positivesideofchannel-1TMDS lowvoltagesignal Rx1+ 85 AI differentialinputpair. Channel-1receivesgreenpixeldatainactivedisplayand CTL1 controlsignalsinblank. Channel-1negativereceiverinput-Negativesideofchannel-1TMDS lowvoltagesignalRx1- 86 AI differentialinputpair. Channel-2positivereceiverinput-Positivesideofchannel-2TMDS lowvoltagesignal Rx2+ 80 AI differentialinputpair. Channel-2receivesredpixeldatainactivedisplayand CTL2, CTL3 controlsignalsinblank. Channel-2negativereceiverinput-Negativesideofchannel-2TMDS lowvoltagesignalRx2- 81 AI differentialinputpair. Sync detect-Outputtosignalwhen thelinkisactiveorinactive.The linkisconsideredtobe activewhen DE isactivelyswitching.The TFP401A monitorsthestateDE todeterminelink activity.SCDT can be tiedexternallytoPDO topower down theoutputdriverswhen thelinkSCDT 8 DO isinactive. High:Activelink Low: Inactivelink Outputdrivestrengthselect-Selectsoutputdrivestrengthforhighorlowcurrentdrive.(See dc specificationsforIOH and IOL vs ST state).ST 3 DI High:Highdrivestrength Low :Low drivestrength Staggeredpixelselect-An activelowsignalused inthe2-pixel/clockpixelmode (PIXS= high).Time staggerstheeven and odd pixeloutputstoreducegroundbounce. STAG 7 DI Normal operationoutputstheodd and even pixelssimultaneously. High:Normal simultaneouseven/oddpixeloutput Low: Time staggeredeven/oddpixeloutput VSYNC 47 DO Verticalsyncoutput ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT DV DD ,AV DD ,OV DD ,PV DD Supplyvoltagerange -0.3 4 V VI Inputvoltagerange,logic/analogsignals -0.3 4 V Operatingambienttemperaturerange -55 125 °C Tstg Storagetemperaturerange(2) –65 150 °C Tc Case temperaturefor10 seconds 260 °C Lead temperature1,6mm (1/16inch)fromcase for10 seconds 260 °C Soldered(3) 4.3 Package power dissipation/PowerPAD ™ W Not soldered(4) 2.7 KV HumanESD protection,allpins 25 Body Model JEDEC latchup(EIA/JESD78) 100 mA (1) Stressesbeyond thoselistedunder"absolutemaximum ratings" may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions" isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Long-termhigh–temperaturestorageand/orextendeduse atmaximum recommended operatingconditionsmay resultina reductionof overalldevicelife.See http://www.ti.com/ep_qualityforadditionalinformationon enhanced plasticpackaging (3) SpecifiedwithPowerPAD ™ bond pad on thebacksideofthepackage solderedtoa 2 oz.Cu platePCB thermalplane.Specifiedat maximum allowedoperatingtemperature,70°C. (4) PowerPAD ™ bond pad on thebacksideofthepackage isnotsolderedtoa thermalplane.Specifiedatmaximum allowedoperating temperature,70°C. Copyright© 2009–2011,Texas InstrumentsIncorporated 5

SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT VDD (DVDD ,AV DD ,PV DD ,OV DD ) Supplyvoltage 3 3.3 3.6 V tpix(1) Pixeltime 6.06 40 ns R t Singleended analoginputterminationresistance 45 50 57 Ω TA Operatingfree-airtemperature -55 125 °C (1) tpixisthepixeltimedefinedas theperiodoftheRxC clockinput.The periodoftheoutputclock,ODCK isequaltotpixwhen in 1-pixel/clockmode and 2tpixwhen in2-pixel/clockmode. DC DIGITAL I/OELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Highleveldigitalinputvoltage(1) 2 DV DD V VIL Low leveldigitalinputvoltage(1) 0 0.8 V IOH Highleveloutputdrivecurrent(2) ST = High, VOH =2.4 5 10 16.3 V mA ST = Low, VOH = 2.4 3 6 10.3 V IOL Low leveloutputdrivecurrent(2) ST = High, VOL = 0.8 8 13 19 V mA ST = Low, VOL = 0.8 4 7 11 V IOZ Hi-Zoutputleakagecurrent PD = Low orPDO = Low -1 1 μA (1) DigitalinputsarelabeledDI inI/Ocolumn ofTerminalFunctionsTable. (2) DigitaloutputsarelabeledDO inI/Ocolumn ofTerminalFunctionsTable. DC ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID Analoginputdifferentialvoltage(1) 75 1200 mV VIC Analoginputcommon mode voltage(1) AV DD -300 AV DD -37 mV VI(OC) Open circuitanaloginputvoltage AV DD -10 AV DD +10 mV IDD(2PIX) Normal 2-pix/clockpower supply ODCK = 82.5MHz 370 mAcurrent(2) 2-pix/clock IPD Power down current(3) PD = Low 10 mA IPDO Outputdrivepower down current(3) PDO = Low 35 mA (1) Specifiedas dc characteristicwithno overshootorundershoot. (2) Alternating2-pixelblack/2-pixelwhitepattern.ST = high,STAG = high,QE[23:0]and QO[23:0]CL = 10 pF. (3) Analoginputsareopen circuit(transmitterisdisconnectedfromTFP401A).

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www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 AC ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID(2) Differentialinputsensitivity(1) 150 1560 mV p-p tps Analoginputintra-pair(+to-) 0.4 tbit(3) differentialskew (2) tccs AnalogInputinter-pairor 1 tpix(4) channel-to-channelskew (2) tijit Worse case differentialinputclock 50 psjittertolerance(5),(2)(6) tf1 Falltimeofdataand control ST = Low, CL=5 pF 2.4 nssignals(7),(8)(6) ST = High, CL=10 pF 1.9 tr1 Risetimeofdataand control ST = Low, CL=5 pF 2.4 nssignals(7),(8)(6) ST = High, CL=10 pF 1.9 tr2 RisetimeofODCK clock(7)(6) ST = Low, CL=5 pF 2.4 ns ST = High, CL=10 pF 1.9 tf2 FalltimeofODCK clock(7)(6) ST = Low, CL=5 pF 2.4 ns ST = High, CL=10 pF 1.9 tsu1 Setuptime,dataand controlsignalto 1 pixel/clock,PIXS = low, 1.8 fallingedge ofODCK (6) OCK_INV = low 2 pixel/clock,PIXS = high, 3.8 nsSTAG = high,OCK_INV = low 2 pixeland STAG, PIXS = high, 0.6 STAG = low,OCK_INV = low th1 Holdtime,dataand controlsignalto 1 pixel/clock,PIXS = low, 0.6 fallingedge ofODCK (6) OCK_INV = low 2 pixeland STAG, PIXS = high, 2.5 nsSTAG = low,OCK_INV = low 2 pixel/clock,PIXS = high, 2.9 STAG = high,OCK_INV = low tsu2 Setuptime,dataand controlsignalto 1 pixel/clock,PIXS = low, 2.1 risingedge ofODCK (6) OCK_INV = high 2 pixel/clock,PIXS = high, 4 nsSTAG = high,OCK_INV = high 2 pixeland STAG, PIXS = high, 1.5 STAG = low,OCK_INV = high th2 Holdtime,dataand controlsignalto 1 pixel/clock,PIXS = low, 0.3 risingedge ofODCK (6) OCK_INV = high 2 pixeland STAG, PIXS = high, 2.4 nsSTAG = low,OCK_INV = high 2 pixel/clock,PIXS = high, 2.1 STAG = high,OCK_INV = high fODCK ODCK frequency PIX = Low (1-PIX/CLK) 25 165 MHz PIX = High(2-PIX/CLK) 12.5 82.5 ODCK duty-cycle 45% 60% 75% tpd(PDL) PropagationdelaytimefromPD low 9 ns toHi-Zoutputs(6) (1) Specifiedas ac parametertoincludesensitivitytoovershoot,undershootand reflection. (2) By characterization (3) tbitis1/10thepixeltime,tpix (4) tpixisthepixeltimedefinedas theperiodoftheRxC inputclock.The periodofODCK isequaltotpixin1-pixel/clockmode or2tpixwhen in2-pixel/clockmode. (5) Measured differentiallyat50% crossingusingODCK outputclockas trigger. (6) Not ProductionTest (7) Riseand falltimesmeasured as timebetween 20% and 80% ofsignalamplitude. (8) Data and controlsignalsare:QE[23:0],QO[23:0],DE, HSYNC, VSYNC and CTL[3:1] Copyright© 2009–2011,Texas InstrumentsIncorporated 7

SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com AC ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd(PDOL) PropagationdelaytimefromPDO low 9 ns toHi-Zoutputs(6) tt(HSC) Transitiontimebetween DE transition ~17-26 ms toSCDT low(9) tt(FSC) Transitiontimebetween DE transition 8 DE toSCDT high(9) transitions td(st) Delaytime,ODCK latchingedge to STAG = Low 0.25 tpix(4) QE[23:0]dataoutput PIXS = High (9) Linkactiveorinactiveisdeterminedby amount oftimedetectedbetween DE transitions.SCDT indicateslinkactivity.

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80% 80% 20% 20% tr1 tf1 QE(0-23), QO(0-23), DE CTK(1-3), HSYNC, VSYNC 80% 20% 80% 20% tr2 tf2 ODCK fODCK ODCK t(su1) t(h1) t(su2) t(h2) VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL ODCK QE(0-23), QO(0-23), DE CTL(1-3), HSYNC, VSYNC OCK_INV 50% VOH td(st) ODCK QE(O-23) PD ODCK, DE, CTL(1-3), HSYNC, VSYNC, SCDT tpd(PDL) VIL TFP401A-EP www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 PARAMETER MEASUREMENT INFORMATION Figure1. Rise and FallTIme ofData and ControlSignals Figure2. Rise and FallTime ofODCK Figure3. ODCK Frequency Figure4. Data Setup and Hold Time toRisingand FallingEdge ofODCK Figure5. ODCK High toQE[23:0]Staggered Data Output Figure6. Analog InputIntra-PairDifferentialSkew Figure7. Delay from PD Low toHi-ZOutputs Copyright© 2009–2011,Texas InstrumentsIncorporated 9

ODCK, DE, CTL(2-3), HSYNC, VSYNC tpd(PDOL) VIL PD DFO, ST, PIXS, STAG, OCK_INV VIH tp(PDH-V) twL(PDL_MIN) PD VIL tccs 50% 50% TX2 TX1 TX0 tt(HSC) tt(FSC) DE SCDT tDEL tDEH DE TFP401A-EP SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure8. Delay from PDO Low toHi-ZOutputs Figure9. Delay from PD Low toHigh BeforeInputsareActive Figure10. Minimum Time PD Low Figure11. Analog InputChannel-to-ChannelSkew Figure12. Time Between DE TransitionstoSCDT Low and SCDT High Figure13. Minimum DE Low and Maximum DE High

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www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 FUNDAMENTAL OPERATION The TFP401A isa digitalvisualinterface(DVI)compliantTMDS digitalreceiverthatisused indigitalflatpanel displaysystems toreceiveand decode TMDS encoded RGB pixeldatastreams.Ina digitaldisplaysystem a host,usuallya PC orworkstation,containsa TMDS compatibletransmitterthatreceives24 bitpixeldataalong withappropriatecontrolsignalsand encodes them intoa high-speedlow-voltagedifferentialserialbitstreamfit fortransmissionovera twisted-paircabletoa displaydevice.The displaydevice,usuallya flat-panelmonitor,will requirea TMDS compatiblereceiverliketheTITFP401A todecode theserialbitstreamback tothesame 24 bit pixeldataand controlsignalsthatoriginatedatthehost.Thisdecoded datacan thenbe applieddirectlytothe flatpaneldrivecircuitryto produce an image on the display.Since the hostand displaycan be separatedby distancesup to5 metersor more, serialtransmissionofthepixeldataispreferred.To supportmodern display resolutionsup toUXGA a highbandwidthreceiverwithgood jitterand skew toleranceisrequired. TMDS PIXEL DATA AND CONTROL SIGNAL ENCODING TMDS standsfortransitionminimizeddifferentialsignaling.Only one of two possibleTMDS charactersfora givenpixelwillbe transmittedata giventime.The transmitterkeeps a runningcountofthenumber ofones and zerospreviouslysentand transmitsthecharacterthatwillminimizethenumber oftransitionsand approximatea dc balanceof the transmissionline.Three TMDS channelsare used to receiveRGB pixeldata duringactive displaytime,DE = high.The same threechannelsalsoreceivecontrolsignals,HSYNC, VSYNC, and user definedcontrolsignalsCTL[3:1].These controlsignalsare receivedduringinactivedisplayor blanking-time. Blanking-timeiswhen DE = low.The followingtablemaps thereceivedinputdatatoappropriateTMDS input channelina DVI compliantsystem. RECEIVED PIXEL DATA OUTPUT PINSINPUT CHANNELACTIVE DISPLAY DE = HIGH (VALID FOR DE = HIGH) Red[7:0] Channel-2 (Rx2 +) QE[23:16]QO[23:16] Green[7:0] Channel-1 (Rx1 +) QE[15:8]QO[15:8] Blue[7:0] Channel-0 (Rx0 +) QE[7:0]QO[7:0] RECEIVED CONTROL DATA UTPUT PINSINPUT CHANNELBLANKING DE = LOW (VALID FOR DE = LOW) CTL[3:2] Channel-2 (Rx2 +) CTL[3:2] CTL1:0 Channel-1 (Rx1 +) CTL1 HSYNC, VSYNC Channel-0 (Rx0 +) HSYNC, VSYNC (1) Some TMDS transmitterstransmita CTL0 signal.The TFP401A decodes and transfersCTL[3:1]and ignoresCTL0 characters.CTL0 is notavailableas a TFP401A output. The TFP401A discriminatesbetween validpixelTMDS charactersand controlTMDS characterstodeterminethe stateofactivedisplayversusblanking,i.e.,stateofDE. Copyright© 2009–2011,Texas InstrumentsIncorporated 11

SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com TFP401A CLOCKING AND DATA SYNCHRONIZATION The TFP401A receivesa clockreferencefromtheDVI transmitterthathas a periodequaltothepixeltime,Tpix. The frequencyof thisclockisalsoreferredto as the pixelrate.Since the TMDS encoded data on Rx[2:0] contains10 bitsper8-bitpixel,itfollowsthattheRx[2:0]serialbitrateis10 timesthepixelrate.Forexample,the requiredpixelratetosupportan UXGA resolutionwith60-Hz refreshrateis165 MHz. The TMDS serialbitrateis 10x thepixelrateor 1.65Gb/s.Due tothetransmissionofthishigh-speeddigitalbitstream,on threeseparate channels(ortwisted-pairwires)oflongdistances(3-5meters),phase synchronizationbetween thedatasteams and theinputreferenceclockisnotspecified.Inaddition,skew between thethreedatachannelsiscommon. The TFP401A uses a 4x oversamplingscheme oftheinputdatastreamstoachievereliablesynchronizationwithup to 1-Tpixchannel-to-channelskew tolerance.Accumulatedjitteron the clockand data linesdue to reflections and externalnoisesourcesisalsotypicalofhighspeed serialdatatransmission,hence theTFP401A 's design forhighjittertolerance. The inputclocktotheTFP401A isconditionedby a phase-locked-loop(PLL)toremove high-frequencyjitterfrom theclock.The PLL providesfour10x clockoutputsofdifferentphase tolocateand sync theTMDS datastreams (4xoversampling).Duringactivedisplaythepixeldataisencoded tobe transitionminimized,whereas inblank, the controldata isencoded to be transitionmaximized.A DVI complianttransmitterisrequiredto transmitin blankfora minimum periodoftime,128-Tpix,tospecifysufficienttimefordatasynchronizationwhen thereceiver sees a transitionmaximizedcode.Synchronizationduringblank,when thedataistransitionmaximized,specifies reliabledatabitboundarydetection.Phase synchronizationtothedatastreamsisuniqueforeach ofthethree inputchannelsand ismaintainedas longas thelinkremainsactive. TFP401A TMDS INPUT LEVELS AND INPUT IMPEDANCE MATCHING The TMDS inputsto the TFP401A receiverhave a fixedsingle-endedterminationto AVDD The TFP401A is internallyoptimizedusinga lasertrimprocessto preciselyfixthe impedance at 50 W. The devicefunctions normallywithor withouta resistoron theEXT_RES pin,so itremainsdrop-incompatiblewithcurrentsockets. The fixedimpedance eliminatestheneed foran externalresistorwhileprovidingoptimum impedance matching tostandard50-W DVI cables. Figure14 shows a conceptualschematicofa DVI transmitterand TFP401A receiverconnection.A transmitter drivesthetwistedpaircableviaa currentsource,usuallyachievedwithan open-draintypeoutputdriver.The internalresistor,which ismatched tothecableimpedance,attheTFP401A inputprovidesa pulluptoAVDD . Naturally,when thetransmitterisdisconnectedand theTFP401A DVI inputsareleftunconnected,theTFP401A receiverinputspullupto AVDD. The singleended differentialsignaland fulldifferentialsignalis shown in Figure15.The TFP401A isdesignedtorespondtodifferentialsignalswingsrangingfrom150 mV to1.56V with common mode voltagesrangingfrom(AVDD-300 mV) to(AVDD-37 mV).

12 Copyright© 2009–2011,Texas InstrumentsIncorporated

at 50 Ω AVDD DVI Compliant Cable DATADATA TI TFP401/401A Receiver DVI Transmitter Current Source 1/2 VIDIFF AVCC AVCC - 1/2 VIDIFF a ) Single-Ended Input Signal + 1/2 VIDIFF - 1/2 VIDIFF VIDIFF b) Differential Input Signal TFP401A-EP www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 Figure14. TMDS DifferentialInputand TransmitterConnection Figure15. TMDS Inputs TFP401A INCORPORATES HSYNC JITTER IMMUNITY SeveralDVI transmittersavailableinthemarketintroducejitteron thetransmittedHSYNC and VSYNC signals duringtheTMDS encryptionprocess.The HSYNC signalcan shiftby one pixelposition(oneclock)fromnominal ineitherdirection,resultinginup totwo cyclesofHSYNC shift.ThisjittercarriesthroughtotheDVI receiver,and ifthepositionofHSYNC shiftscontinuously,thereceivercan losetrackoftheinputtimingand pixelnoisewill occuron thedisplay.For thisreason,a DVI compliantreceiverwithHSYNC jitterimmunityshouldbe used inall displaysthatcouldbe connectedtohostPCs withtransmittersthathave thisHSYNC jitterproblem. The TFP401A integratesHSYNC regenerationcircuitrythatprovidesa seamlessinterfacetothesenoncompliant transmitters.The positionofthedataenable(DE) signalisalwaysfixedinrelationtodata,irrespectiveofthe locationofHSYNC. The TFP401A receiveruses theDE and clocksignalsrecreatestableverticaland horizontal sync signals.The circuitfilterstheHSYNC outputofthereceiver,and HSYNC isshiftedtothenearesteighthbit boundary,producinga stableoutputwithrespecttodata,as shown inFigure16.Thiswillensureaccuratedata synchronizationattheinputofthedisplaytimingcontroller. Copyright© 2009–2011,Texas InstrumentsIncorporated 13

HSYNC Shift by ± 1 Clock ODCK HSYNC IN DE HSYNC OUT TFP401A-EP SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com ThisHSYNC regenerationcircuitistransparenttothemonitorand need notbe removed even ifthetransmitted HSYNC isstable.Forexample,thePanelBus™ lineofDVI 1.0complianttransmitters,such as theTFP6422 and TFP420, do not have the HSYNC jitterproblem.The TFP401A willoperatecorrectlywitheithercompliantor noncomplianttransmitters.In contrast,the TFP401 isidealforcustomerswho have controlover the transmit portionofthedesignsuch as bundledsystem manufacturersand forinternalmonitoruse (theDVI connection between monitorand panelmodules). Figure16. HSYNC RegenerationTiming Diagram TFP401A MODES OF OPERATION The TFP401A providessystems designflexibilityand valueby providingthesystem designerwithconfigurable optionsor modes ofoperationtosupportvaryingsystem architectures.The followingtableoutlinesthevarious panelmodes thatcan be supportedalongwithappropriateexternalcontrolpinsettings. ODCK LATCHPANEL PIXEL RATE ODCK DFO PIXS OCK_INVEDGE TFT or16-bit 1 pix/clock Falling Freerun 0 0 0DSTN TFT or16-bit 1 pix/clock Rising Freerun 0 0 1DSTN TFT 2 pix/clock Falling Freerun 0 1 0 TFT 2 pix/clock Rising Freerun 0 1 1 24-bitDSTN 1 pix/clock Falling Gated low 1 0 0 NONE 1 pix/clock Rising Gated low 1 0 1 24-bitDSTN 2 pix/clock Falling Gated low 1 1 0 24-bitDSTN 2 pix/clock Rising Gated low 1 1 1 TFP401A OUTPUT DRIVER CONFIGURATIONS The TFP401A providesflexibilityby offeringvariousoutputdriverfeaturesthatcan be used tooptimizepower consumption,ground-bounceand power-supplynoise.The followingsectionsoutlinetheoutputdriverfeatures and theireffects. Output driverpower down (PDO = low),PullingPDO low willplaceallthe outputdrivers,exceptCTL1 and SCDT, intoa high-impedancestate.The SCDT outputwhich indicateslink-disabledor link-inactivecan be tied directlytothePDO inputtodisabletheoutputdriverswhen thelinkisinactiveorwhen thecableisdisconnected. An internalpullupon thePDO pinwilldefaulttheTFP401A tothenormalnonpower down outputdrivemode if leftunconnected. Drive Strength (ST = high forhigh drivestrength,ST=low forlow drivestrength.)The TFP401A allowsfor selectableoutputdrivestrengthon thedata,controland ODCK outputs.See thedc specificationstableforthe valuesof IOH and IOL currentdrivesfora givenST state.The highoutputstrengthoffersapproximatelytwo timesthedriveas thelowoutputdrivestrength.

14 Copyright© 2009–2011,Texas InstrumentsIncorporated

www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 Time Staggered PixelOutput.Thisoptionworks onlyinconjunctionwiththe2-pixel/clockmode (PIXS = high). SettingSTAG = low willtimestaggertheeven and odd pixeloutputso as toreducetheamount ofinstantaneous currentsurgefromthepower supply.Depending on thePCB layoutand designthiscan helpreducetheamount ofsystem groundbounce and power supplynoise.The timestaggerissuch thatin2-pixel/clockmode theeven pixelisdelayedfromthelatchingedge ofODCK by 0.25Tcip.(TcipistheperiodofODCK. The ODCK periodis 2Tpixwhen in2-pixel/clockmode.) Depending on system constraintsofoutputload,pixelrate,panelinputarchitectureand boardcosttheTFP401A drivestrengthand staggeredpixeloptionsallowflexibilitytoreducesystem power-supplynoise,groundbounce and EMI. Power Management. The TFP401A offersseveralsystempower management features. The outputdriverpower down (PDO = low)isan intermediatemode whichoffersseveraluses.Duringthismode, alloutputdriversexceptSCDT and CTL1 are drivento a high-impedancestatewhilethe restof the device circuitryremainsactive The TFP401A power down (PD = low)isa completepower down inthatitpowers down the digitalcore,the analogcircuitry,and outputdrivers.Alloutputdriversareplacedintoa Hi-Zstate.Allinputsaredisabledexcept forthePD input.The TFP401A willnotrespondtoany digitaloranaloginputsuntilPD ispulledhigh. Both PDO and PD have internalpullups,so ifleftunconnectedtheydefaulttheTFP401A tonormaloperating modes. Sync Detect.The TFP401A offersan output,SCDT, toindicatelinkactivity.The TFP401A monitorsactivityon DE to determineifthe linkisactive.When 2^18 clocksproduced by an on-chipfreerunningoscillatorwhose frequencyisaround 10-15 MHz pass withouta transitionon DE, theTFP401A considersthelinkinactiveand SCDT isdrivenlow.Hence SCDT goes low aftertheterminalcountofthecounterisreachedthatis17~26 ms. When SCDT islow,if8 DE edges are detectedwithintheterminalcountof2^18 clocks,thelinkisconsidered activeand SCDT goes high. SCDT can be used tosignala system power management circuittoinitiatea system power down when thelink isconsideredinactive.The SCDT can alsobe tieddirectlytotheTFP401A PDO inputtopower down theoutput driverswhen thelinkisinactive.Itisnotrecommended touse theSCDT todrivethePD inputsince,once in completepower-down,theanaloginputsareignoredand theSCDT statedoes notchange.An externalsystem power management circuittodrivePD ispreferred. SYNC DETECT OPERATION Some graphicscardwhen insleep/standbymode send charactersthatcan make theDE toggleand make SCDT high,hence insuch applications,torobustlydetermineifthelinkisinactiveorinactivemode, itisrecommended thata sync signallikeHSYNC can be used inadditiontotheSCDT. Timingformaton therecoveredHSYNC signalcan be used inadditiontoSCDT todetermineifthelinkisreceivinga validvideoformat. Inapplicationswhere PD isbeingpulsed(tosave power whileinsleep/standbymode) when thelinkisinactive, and SCDT isused solelytodeterminethelinkactivity,theninsuch cases SCDT shouldnotbe used until25 ms ofsignaland power application. There isa rarepossibilitythatSCDT can getstuckhighon power up orremovaloftheDVI signal.For example: Ifthe power on a DVI distributionbox sourcingthe signalto the receiveriscycledrapidly(2-3times/second), thenthereisa smallpossibility,(1in~40-50times)ofcyclingpower thatSCDT may be stuckhighwhen thebox ispowered off. TIPOWERPAD ™ 100-TQFP PACKAGE The TFP401A ispackaged in TI's thermallyenhanced PowerPAD ™ 100TQFP packaging.The PowerPAD ™ package isa 14 mm y 14 mm y 1 mm TQFP outlinewith0.5-mm lead-pitch.The PowerPAD ™ package has a speciallydesigneddiemount pad thatoffersimprovedthermalcapabilityover typicalTQFP packages of the same outline.The TI 100-TQFP PowerPAD ™ package offersa back-sidesolderplanethatconnectsdirectlyto thediemount pad forenhanced thermalconduction.Solderingtheback sideoftheTFP401A totheapplication board isnotrequiredthermallyas thedevicepower dissipationiswellwithinthepackage capabilitywhen not soldered.Iftracesorviasarelocatedundertheback sidepad,theyshouldbe protectedby suitablesoldermask orotherassemblytechniquetopreventinadvertentshortingtotheexposed back sidepad. Copyright© 2009–2011,Texas InstrumentsIncorporated 15

SLDS160A –MARCH 2009–REVISED JULY 2011 www.ti.com Solderingtheback sidepad ofthedevicetoa thermallandconnectedtothePCB groundplaneisrecommended forelectricaland EMI considerations.The thermallandmay be solderedto the exposed PowerPAD ™ using standardreflowsolderingtechniques. The recommended pad sizeforthegrounded thermallandis5.6mm sq.minimum, centeredinthedeviceland pattern.When viasare requiredto ground the land,multipleviasare recommended fora low impedance connectiontothegroundplane.Viasintheexposed pad shouldbe smallenough orfilledtopreventwickingthe solderaway from the interfacebetween the package body and the thermallandon the surfaceof the board duringsolderreflow. More informationon thispackage and otherrequirementsforusingthermallandsand thermalviasaredetailedin the TI applicationreportPowerPAD ™ ThermallyEnhanced Package ApplicationReport, TI literaturenumber SLMA002, availableviatheTIWeb pages beginningatwww.ti.com. Table 1 outlinesthe thermalpropertiesof the TI 100-TQFP PowerPAD ™ package. The 100-TQFP non- PowerPAD ™ package isincludedonlyforreference. Table1.TI100-TQFP (14X 14 X 1 mm)/0.5 mm LEAD PITCH PowerPAD ™ PowerPAD ™WITHOUTPARAMETER (1)(2) NOT CONNECTED TO PCB CONNECTED TO PCBPowerPAD ™ THERMAL PLANE THERMAL PLANE (1) Theta-JA 45°C/W 27.3°C/W 17.3°C/W Theta-JC 3.11°C/W 0.12°C/W 0.12°C/W Maximum power dissipation(3) 1.6W 2.7W 4.3W (1) Specifiedwith2-oz.Cu PCB plating. (2) Airflowisat0 LFM (noairflow) (3) Measured atambienttemperature,TA = 70°C.

16 Copyright© 2009–2011,Texas InstrumentsIncorporated

www.ti.com SLDS160A –MARCH 2009–REVISED JULY 2011 REVISTION HISTORY Changes from Original(March 2009)toRevisionA Page

  • Changed 1stbulletinFEATURES: FROM: SupportsUXGA Resolution(OutputPixelRate Up to165MHz) TO:
  • Changed sentenceinfirstparagraphofdescriptionFROM: supportsdisplayresolutionsup toUXGA in24-bittrue Copyright© 2009–2011,Texas InstrumentsIncorporated 17

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TFP401AMPZPEP Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -55 to 125 TFP401AMPZPEP TFP401AMPZPEP.A Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -55 to 125 TFP401AMPZPEP V62/09627-01XE Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -55 to 125 TFP401AMPZPEP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-May-2025 OTHER QUALIFIED VERSIONS OF TFP401A-EP :

  • Catalog : TFP401A
  • Automotive : TFP401A-Q1 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product
  • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TFP401AMPZPEP PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 20.3 15.4 15.45 V62/09627-01XE PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 20.3 15.4 15.45 Pack Materials-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. TQFP - 1.2 mm max height TM PowerPAD PZP 100 PLASTIC QUAD FLATPACK14 x 14 mm Pkg Body, 0.5 mm pitch 16 x 16 mm Pkg Area 4224739/B

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