STM32MP251A_V01 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Introduction
  • 2 Description
  • 3 Functional overview
  • 3.1 Dual-core Arm Cortex-A35 subsystem (CA35SS)
  • 3.1.1 Features
  • 3.1.2 Overview
  • 3.2 Arm Cortex-M33 core with TrustZone and FPU (CM33)
  • 3.3 Arm Cortex-M0+ core (CM0P)
  • 3.4 Graphic processing unit (GPU)
  • 3.5 Neural processor unit (NPU)
  • 3.6 Memories
  • 3.6.1 External SDRAM
  • 3.6.2 Embedded SRAM
  • 3.7 DDR3L/DDR4/LPDDR4 controller (DDRCTRL)
  • 3.8 Boot modes
  • 3.9 Power supply management (PWR)
  • 3.9.1 Power supply scheme
  • 3.9.2 Power-supply supervisor
  • 3.10 Low-power strategy
  • 3.11 Resource isolation framework (RIF)
  • 3.12 Reset and clock controller (RCC)
  • 3.12.1 Features
  • 3.12.2 Clock management
  • 3.12.3 Reset sources
  • 3.13 Hardware semaphore (HSEM)
  • 3.14 Inter-processor communication controller (IPCC1/2)
  • 3.14.1 Main features
  • 3.15 General-purpose input/outputs (GPIO)
  • 3.16 Bus-interconnect matrix
  • 3.17 High-performance DMA controllers (HPDMA1/2/3)
  • 3.18 Low-power DMA controller (LPDMA1)
  • 3.19 Cortex-M33 nested vectored interrupt controller (NVIC)
  • 3.20 Cortex-M0+ nested vectored interrupt controller (NVIC)
  • 3.21 Extended interrupt and event controller (EXTI1/2)
  • 3.22 Cyclic redundancy check calculation unit (CRC)

Features

Includes ST state-of-the-art patented technology. Cores

  • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone®
  • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up to 400 MHz – L1 16-Kbyte I / 16-Kbyte D – Arm® TrustZone®
  • 32-bit Arm® Cortex®-M0+ in SmartRun domain – Up to 200 MHz (up to 16 MHz in autonomous mode) Memories
  • External DDR memory up to 4 Gbytes – Up to DDR3L-2133 16/32-bit – Up to DDR4-2400 16/32-bit – Up to LPDDR4-2400 16/32-bit
  • 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes in SmartRun domain
  • Two Octo-SPI memory interfaces
  • Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC Security/safety
  • TrustZone® peripherals, active tamper, environmental monitors, display secure layers, hardware accelerators
  • Complete resource isolation framework Reset and power management
  • POR, PDR, PVD, and BOR
  • On-chip LDO and power-switches for RETRAM, BKPSRAM, VSW, and SmartRun domains
  • Dedicated supplies for Cortex®-A35 and GPU/NPU (if present)
  • Internal temperature sensors
  • Low-power modes: Sleep, Stop, and Standby
  • DDR memory retention in Standby mode VFBGA361 (10 × 10 mm) pitch 0.5 mm VFBGA424 (14 × 14 mm) pitch 0.5 mm TFBGA436 (18 × 18 mm) pitch 0.8 mm Product summary STM32MP25xA/D STM32MP251A, STM32MP251D, STM32MP253A, STM32MP253D, STM32MP255A, STM32MP255D, STM32MP257A, STM32MP257D Arm® based dual Cortex®-A35 1.5 GHz + Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe® STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Datasheet DS14285 - Rev 2 - June 2024 For further information contact your local STMicroelectronics sales office. Prerelease product(s)
  • Controls for PMIC companion chip Low-power consumption Clock management
  • Internal oscillators: 64 MHz HSI, 4/16 MHz MSI, 32 kHz LSI
  • External oscillators: 16-48 MHz HSE, 32.768 kHz LSE
  • Up to 8× PLLs with fractional mode General-purpose inputs/outputs
  • Up to 172 secure I/O ports with interrupt capability – Up to 6 wake-up inputs – Up to 8 tamper input pins + 8 active tampers output pins Interconnect matrix
  • Bus matrices – 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz – 32-bit Arm® AMBA® AHB interconnect, up to 400 MHz

4 DMA controllers to unload the CPU

  • 48 + 4 physical channels in total
  • 3× dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16 channels each
  • 1× low-power DMA controller with 4 channels in SmartRun domain Up to 51 communication peripherals
  • 8× I2C FM+ (1 Mbit/s, SMBus/PMBus®)
  • 4× I3C (12.5 Mbit/s)
  • 5× UART + 4× USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1× LPUART
  • 8× SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock)(+2 with OCTOSPI + 4 with USART)
  • 4× SAI (stereo audio: I2S, PDM, SPDIF Tx)
  • SPDIF Rx with 4 inputs
  • 3× SDMMC up to 8-bit (SD/e•MMC™/SDIO)
  • Up to 3× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TTCAN)
  • 1× USB 2.0 high-speed Host with embedded 480 Mbits/s PHY
  • 1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY (5 Gbits/s PHY shared with PCI Express)
  • 1× USB Type-C® Power Delivery control with two CC lines PHY
  • 1 × PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)
  • Up to 3× Gigabit Ethernet interfaces – 1× Gigabit Ethernet GMAC with one PHY interface (optional) – 1× Gigabit Ethernet GMAC with one external PHY interface, optionally internally connected to one embedded Ethernet switch providing two external PHY interfaces – TSN, IEEE 1588v2 hardware, MII/RMII/RGMII STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 2/234 Prerelease product(s)
  • Camera interface #1 (5 Mpixels @30 fps) – MIPI CSI-2®, 2× data lanes up to 2.5 Gbit/s each – 8- to 16-bit parallel, up to 120 MHz – RGB, YUV, JPG, RawBayer with Lite-ISP – Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines
  • Camera interface #2 (1 Mpixels @15 fps) – 8- to 14-bit parallel, up to 80 MHz – RGB, YUV, JPG – Cropping
  • Digital parallel interface up to 16-bit input or output 7 analog peripherals
  • 3 × ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)
  • Internal temperature sensor (DTS)
  • 1× multifunction digital filter (MDF) with up to 8 channels/8 filters
  • 1× audio digital filter (ADF) with 1 filter and sound activity detection
  • Internal (VREFBUF) or external ADC reference VREF+ Graphics
  • Optional 3D GPU: VeriSilicon® - Up to 900 MHz – OpenGL® ES 3.1 - Vulkan 1.3 – OpenCL™ 3.0, OpenVX™ 1.3 – Up to 150 Mtriangle/s, 900 Mpixel/s
  • LCD-TFT controller, up to 24-bit // RGB888 – Up to FHD (1920 × 1080) @60 fps – 3 layers including a secure layer – YUV support, 90° output rotation
  • Optional MIPI DSI®, 4× data lanes, up to 2.5 Gbit/s each – Up to QXGA (2048 × 1536) @60 fps
  • Optional FPD-1 and OpenLDI JEIDA/VESA (LVDS), up to 2× links of 4× data lanes, up to 1.1 Gbit/s per lane – Up to QXGA (2048 × 1536) @60 fps Artificial intelligence
  • Optional NPU: VeriSilicon® - Up to 900 MHz – TensorFlowLite - ONNX - Linux NN Video processing
  • Optional hardware video encoder and decoder up to 600 MHz – H264/VP8 up to FHD (1920×1080) @60 fps – JPEG up to 500 Mpixel/s – 128 Kbytes of video RAM Up to 34 timers and 7 watchdogs
  • 4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • 3× 16-bit advanced motor control timers
  • 10× 16-bit general-purpose timers (including 2 basic timers without PWM)
  • 5× 16-bit low-power timers
  • Secure RTC with subsecond accuracy and hardware calendar
  • Up to 2× 4 Cortex®-A35 system timers (secure, non-secure, virtual, hypervisor) STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 3/234 Prerelease product(s)
  • 2× SysTick Cortex®-M33 timer (secure, non-secure)
  • 1× SysTick Cortex®-M0+ timer
  • 7× watchdogs (5× independent and 2× window) Hardware acceleration
  • ECDSA verification with SCA
  • HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC
  • True random number generator
  • CRC calculation unit Debug mode
  • Arm® CoreSight™ trace and debug: SWD and JTAG interfaces 12288-bit fuses including 96-bit unique ID All packages are ECOPACK2 compliant STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 4/234 Prerelease product(s)

1 Introduction

This document provides information on STM32MP25xA/D devices, such as description, functional overview, pin assignment and definition , electrical characteristics, packaging and ordering information. It must be read in conjunction with the STM32MP25xA/D reference manual (RM0457). For information on the device errata with respect to the datasheet and reference manual, refer to the STM32MP25xA/D errata sheet (ES0598). For information on the Arm® Cortex®- M33 core, refer to the Cortex®- M33 Technical Reference Manual, available from the www.arm.com website. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Introduction DS14285 - Rev 2 page 5/234 Prerelease product(s)

2 Description

STM32MP25xA/D devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency. STM32MP25xA/D devices also embed a Cortex®-M33 32-bit RISC core operating at up to 400 MHz frequency. The Cortex®-M33 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions, TrustZone®, and a memory protection unit (MPU) which enhances application security. The devices also embed a Cortex®-M0+ 32-bit RISC core operating at up to 200 MHz frequency (16 MHz when running from backup regulator). This processor is located in the SmartRun domain, and can be used to ensure very-low-power peripheral activity when all other processors and domains are stopped. STM32MP25xA/D devices can also embed a 3D graphic processing unit (VeriSilicon®, OpenGL ES 3.1, Vulkan 1.3, OpenCL 3.0, OpenVX 1.3) running at up to 900 MHz, with performances up to 150 Mtriangle/s, 900 Mpixel/s. The graphic processing unit can provide a neural processor unit (VeriSilicon®, TensorFlowLite, ONNX, Linux NN) running at up to 900 MHz. STM32MP25xA/D devices provide an external SDRAM interface supporting external memories up to 32‑Gbit density (4 Gbytes), 16- or 32-bit DDR3L up to 1066 MHz, 16- or 32-bit LPDDR4 or DDR4 up to 1200 MHz. The devices incorporate high-speed embedded memories: 808 Kbytes of internal SRAM (including 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video SRAM (which can be used as general purpose), two banks of 128 Kbytes each of AHB SRAM, three banks of 8, 8, and 16 Kbytes of AHB SRAM in SmartRun domain, 128 Kbytes of AHB SRAM in backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multi-layer AXI interconnect supporting access to internal and external memories. Each device offers three ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, 4 general-purpose 32-bit timers, three PWM timers for motor control, five low-power timers, and a true random number generator (RNG) STM32MP25xA/D devices offer a video encoder and a video decoder. The devices support 8 multi-function digital filters (MDF), and one dedicated audio-digital filter with sound-activity detection (ADF). The devices feature the following standard and advanced communication interfaces. Standard peripherals

  • eight I2Cs
  • four I3Cs
  • four USARTs and five UARTs
  • one low-power UART
  • eight SPIs, three I2Ss full-duplex master/slave. The I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock.
  • four SAI serial audio interfaces
  • one SPDIF Rx interface
  • three SDMMC interfaces
  • an USB 2.0 Host with embedded Hi-Speed PHY
  • an USB 2.0/3.0 dual-role data with both Hi-Speed and 5Gbits/s SuperSpeed PHYs
  • three FDCAN interfaces, including one supporting TTCAN mode (optional)
  • two Gigabit Ethernet Interface, with TSN support (optional)
  • one Gigabit Ethernet Switch connected to ETH1 and providing two external PHY interfaces, with TSN support (optional) Advanced peripherals including
  • a flexible memory control (FMC) interface
  • two Octo-SPI flash memory interface STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Description

DS14285 - Rev 2 page 6/234 Prerelease product(s)

  • two camera interfaces for CMOS sensors, one with basic ISP, demosaicing and parallel or MIPI CSI interface
  • an LCD-TFT display interface
  • a MIPI DSI display interface (optional)
  • an LVDS display interface (optional) A comprehensive set of power-saving mode allows the design of low-power applications. STM32MP25xA/D devices are proposed in various packages up to 436 balls with 0.5 mm to 0.8 mm pitch. The set of included peripherals can change with the selected device. These features make STM32MP25xA/D devices suitable for a wide range of consumer, industrial, white goods and medical applications. Figure 1 shows the general block diagram of STM32MP25xA/D devices.

Table 1. STM32MP25xA/D features and peripheral counts

900 MHz(1)

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24 bits 2 (Cortex-M33, secure and non-secure) 24 bits 1 (Cortex-M0+) Cortex-A35 (CNT) 64 bits Up to 2 × 4 (secure, non-secure, Virtual, Hypervisor)(1) RTC 1 Watchdog 7 (5× independent, 2× window) Communication Peripherals SPI Total 8 having I2S 3 I2C (with SMB/PMB support) 8 I3C 4 USART (Smartcard, SPI, IrDA, LIN) + UART (IrDA, LIN)(2) 4 + 5 LPUART 1 SAI 4 (up to 8 audio channels), with I2S master/ slave, PCM input, SPDIF-TX PCI Express (PCIE) Yes, 1× TX + 1× RX, embedded 5 Gbit/s PHY USB USB 2.0 Host (USBH) 1 port, embedded Hi-Speed PHY USB 2.0/3.0 Dual Role (USB3DR)(2) Yes, embedded Hi-Speed and SuperSpeed

5 Gbps PHY

Embedded PHYs 3 (2× Hi-Speed + 1x SuperSpeed 5 Gbps) Type-C support (UCPD) Yes, includes two CC-lines embedded PHY SPDIFRX 4 inputs FDCAN Up to 3(1) SDMMC (SD, SDIO, e•MMC)(2) 3 (8 + 8 + 4 bits). OCTOSPI(2) 2 FMC Parallel address/data 8/16 bits 4× CS, up to 4x 64 Mbytes(1) Parallel AD-Mux 8/16 bits 4× CS, up to 4x 64 Mbytes(1) NAND 8/16 bits(2) Yes, 4 x CS, SLC, BCH4/8(1) Gigabit Ethernet interfaces Up to 3(1) LCD-TFT (LTDC) - Up to 314 MHz pixel clock (when used with DSI or LVDS) Parallel interface Up to 24-bits 150 MHz pixel clock (up to 1080p60) Display serial interface (DSI) 4× data lanes 2.5 Gbit/s each (up to 1536p60)(1) LVDS display interface (LVDS) Up to dual-link of 4× data lanes 1.1 Gbit/s each (up to 1536p60)(1) Camera interface - CSI-2 + RGB/RawBayer parallel CSI-2 serial (CSI + DCMIPP) 2× data lanes 2.5 Gbit/s each, path shared with DCMIPP Parallel RGB/RawBayer (DCMIPP) Up to 120 MHz, path shared with CSI. Image signal processing (ISP) Yes, embedded inside DCMIPP Parallel RGB (DCMI) Up to 80 MHz STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 8/234 Prerelease product(s)

Parallel interface (PSSI) 16-bit input or output, path shared with DCMI and DCMIPP HPDMA 3 instances, 48 physical channels in total LPDMA 1 instance, 4 physical channels Public key accelerator (PKA) ECDSA verification. 64-bit core Hash (HASH) SHA-1, SHA-2 and SHA-3 (up to 512), MD5, HMAC Random number generator (RNG) True-RNG. FIPS 140-2 NDRNG (NIST SP800-90B certifiable) Fuses (one-time programming) 12288 effective bits Multi-function digital filter (MDF) 8 input channels with 8 filters Audio digital filter (ADF) 1 input channel with 1 filter and sound-activity detection GPIOs with interrupt (total count) Up to 172(1) Wake-up pins Up to 6(1) Tamper input/active output pins Up to 8 inputs and 8 outputs(1) Up to 12 bit ADC 3 (up to 5 Msps each) ADC channels in total (differential) Up to 23 channels (or 11 differential)(1) VREF generation (VREFBUF) 1.21 V, 1.5 V, or VREF+ input VREF+ input pin Yes 1. See next tables for details. 2. Can be a boot source. Table 2. STM32MP25xA/D differences per product lines

800 Mpixel/s

900 Mpixel/s

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Feature STM32MP251x STM32MP253x STM32MP255x STM32MP257x Embedded SRAM Video RAM No 128 Kbytes, shared between VDEC and VENC(3) CPU system 256 + 128 Kbytes 256 Kbytes(3) Timers A35 (CNT) 64 bits 4 (S, NS, V, H) 2x 4 (secure, non-secure, Virtual, Hypervisor) FDCAN No 3 (1x TT-FDCAN), 10-Kbyte shared buffer Gigabit Ethernet interfaces External interfaces 1, R(G)MII, MII 2, R(G)MII, MII 3, R(G)MII GMAC (ETH), TSN, PTP, EEE 1 2 3 ports Gigabit Switch (ETHSW) No No No 2 external ports Display serial interface (DSI) No 4× data lanes 2.5 Gbit/s each (up to 1536p60) LVDS display interface (LVDS) No Up to dual-link of 4x data lanes 1.1 Gbit/s each (up to 1536p60)(4) 1. GPU and NPU share performance. 2. This is the performance of either VDEC or VENC running alone. VDEC and VENC share performances as they are using same video RAM. 3. If neither VDEC nor VENC are used, the video RAM can be used as general purpose memory, thus giving a total of 384 Kbytes for CPU system. 4. Single or dual-link depends on the package (see next table for details). Table 3. STM32MP25xA/D differences per packages STM32MP25xxAL STM32MP25xxAK STM32MP25xxAI VFBGA361 VFBGA424 TFBGA436 Packages Body size (mm) 10×10 14×14 18×18 Pitch (mm) 0.5 0.5 0.8 Thickness (mm) 1 1 1.2 Ball count 361 424 436 SDRAM - Up to 2 x 4.8 Gbytes/s internal buses DDR3L 16 bits 1066 MHz Up to 1 Gbyte, single rank 32 bits 1066 MHz - Up to 2 Gbytes, single rank DDR4 16 bits 1200 MHz Up to 4 Gbytes, single rank 32 bits 1200 MHz - Up to 4 Gbytes, single rank LPDDR4 16 bits 1200 MHz Up to 2 Gbytes, single rank 32 bits 1200 MHz - Up to 4 Gbytes, single rank two channels in parallel (lockstep) FMC Parallel address.data 8/16-bits - 4× CS, up to 4× 64 MBytes Parallel AD-mux 8/16-bits 4× CS, up to 4× 64 MBytes NAND 8/16-bits (1) Yes, 4× CS, SLC, BCH4/8 LVDS display interface (LVDS) Single-link of 4× data lanes 1.1 Gbit/s each (up to 1080p60) (2) Dual-link of 4× data lanes 1.1 Gbit/s each (up to 1536p60)(2) GPIO with interrupt (total count) 144 144 172 Wakeup pins 6 6 6 Tamper input/active output pins 8 + 8 8 + 8 8 + 8 ADC ADC channels in total (differential) 23 (11)(3) 21 (10) 23 (11)(3) STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 10/234 Prerelease product(s)

  1. Can be a boot source. 2. Availability depends on device. 3. Including 2 (or 1 differential) low-noise inputs on dedicated ANA0/ANA1 pins. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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Figure 1. STM32MP25xA/D block diagram

1.5 GHz + MMU

32 KB I$

32 KB D$

400 MHz + MPU

512 KB L2$ + SCU

6 CSI

18 ETH2 GMAC (TSN)

10 DSI

2 UCPD1 (USB Type-C)

900 MHz

600 MHz600 MHz

200 MHz400 MHz 600 MHz200 MHz 600 MHz

400 MHz 200 MHz300 MHz200 MHz 200 MHz300 MHz300 MHz 200 MHz

200 MHz200 MHz

300 MHz300 MHz 200 MHz

400 MHz

2 M0P SWD

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3 Functional overview

3.1 Dual-core Arm Cortex-A35 subsystem (CA35SS)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details).

3.1.1 Features

  • Armv8-A architecture
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • 32-Kbyte L1 instruction cache for each CPU
  • 32-Kbyte L1 data cache for each CPU
  • 512-Kbyte level2 cache
  • Arm A64 + A32 + Thumb-2 instruction set
  • Arm TrustZone security technology
  • Arm NEON advanced SIMD
  • DSP and SIMD extensions
  • VFPv4 floating-point
  • Hardware virtualization support
  • Performance monitoring Uuit (PMU)
  • Program trace macrocell (PTM) that supports instruction trace only
  • Integrated generic interrupt controller (GIC) with 384 shared peripheral interrupts
  • Integrated generic timer (CNT) Note: The cryptographic extension is not supported.

3.1.2 Overview

The Cortex-A35 processor uses a highly-efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.

3.1.2.1 Thumb-2 technology

Delivers the peak performance of traditional Arm code, while also providing up to a 30 % reduction in memory requirement for instructions storage.

3.1.2.2 TrustZone technology

Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry partners.

3.1.2.3 PMU

The PMU provides six performance monitors that can be configured to gather statistics on the operation of each core and the memory system. The information can be used for debug and code profiling.

3.1.2.4 NEON and FPU

Advanced SIMD is a media and signal processing architecture that adds instructions primarily for audio, video, 3‑D graphics, image, and speech processing. The floating-point architecture provides support for single-precision and double-precision floating-point operations. All scalar floating-point instructions are available in the A64 instruction set. All VFP instructions are available in A32 and T32 instruction sets. The same advanced SIMD instructions are available in both A32 and T32 instruction sets. The A64 instruction set offers additional advanced SIMD instructions, including double-precision floating-point vector operations. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 13/234 Prerelease product(s)

3.1.2.5 Hardware virtualization

Highly-efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to simultaneously access the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.

3.1.2.6 Optimized L1 caches

Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. There is also the option of cache coherence for enhanced inter- processor communication, or support of a rich SMP capable OS for simplified multicore software development.

3.1.2.7 Integrated L2 cache controller

Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to reduce the power consumption associated with off-chip memory access.

3.1.2.8 Snoop control unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cachetocache and system memory transfers, cache coherence and other capabilities for the processor. This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver.

3.1.2.9 Generic interrupt controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication, and the routing and prioritization of system interrupts. Supporting up to 416 independent interrupts (including 384 shared interrupt), under software control, each interrupt can be distributed across Cortex‑A35 cores, hardware prioritized, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provide one of the key features required to enhance the capabilities of a solution utilizing an hypervisor.

3.2 Arm Cortex-M33 core with TrustZone and FPU (CM33)

The Arm Cortex-M33 core with TrustZone and FPU is a 32-bit RISC processor that features exceptional code- efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. It is comprise of:

  • Arm TrustZone technology, using the Armv8-M main extension supporting secure and non-secure states
  • floating-point extension (FPU)
  • Armv8-M DSP extension
  • a nested vectored interrupt controller (NVIC) closely integrated with the processor
  • a memory system with memory protection unit (MPU) with up to 16 non-secure regions and 16 secure regions
  • a security attribution unit (SAU) with up to 8 regions
  • an implementation defined attribution unit (IDAU)
  • debug components including breakpoints (BPU), data watchpoints (DWT), instrumentation and processor trace (ITM/ETM), cross trigger interface (CTI)
  • 16-Kbyte instruction and 16-Kbyte data caches (ICACHE/DCACHE)

3.3 Arm Cortex-M0+ core (CM0P)

The Cortex-M0+ processor is built on a highly area- and power-optimized 32bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8bit and 16bit microcontrollers. The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 14/234 Prerelease product(s)

3.4 Graphic processing unit (GPU)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). STM32MP25xA/D devices include a 3D graphics engine (VeriSilicon GC8000UL). The GPU is a dedicated graphics processing unit accelerating numerous 3D graphics applications such as graphical user interface (GUI), menu display or animations. It works together with an optimized software stack design for industry-standard APIs with support for Android™ and Linux® embedded development platforms. The GPU is used to accelerate parallel computing (GPGPU), via the typical OpenCL or Vulkan API, or more image-based API like OpenVX or OpenCV. This wide support guarantees to be able to accelerate any application up to the most recent ones, with graphic performances reaching 25.6 GFlops. The GPU is built in a separate power domain, which allows the GPU to be switched off when not used in the long- term, or even to play with dynamic voltage frequency scaling (DVFS). The GPU graphic hardware acceleration is exposed through the following API:

  • OpenVG 1.2 for 2D or curve drawing
  • OpenGL/ES 3.1 for 3D apps (backward compatible: OES2.1 and OES1.1)
  • Vulkan 1.3 for modern 3D apps
  • OpenCL 3.0 for parallel programming
  • OpenVX 1.3 for acceleration of computer vision applications The GPU provides the following graphic theoretical performance (values for 800 MHz):
  • Vertex: 200 MVtx/s
  • Triangle: 133 MTrg/s
  • Texel: 800 MTex/s
  • Pixel: 800 MPix/s
  • Float 16bit: 25.6 GFlops
  • Float 32bit: 12.8 GFlops

3.5 Neural processor unit (NPU)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). The NPU provides powerful hardware acceleration for neural network, to allow efficient artificial intelligence (AI) applications. The NPU acceleration is implemented by hardware neural operator inserted into the GPU. As such, it benefits of both optimized hardware (the neural operator), and of the flexibility and efficiency of the existing GPU shaders. The NPU neural hardware acceleration is exposed through the following API:

  • TensorFlowLite-API
  • ONNX
  • Linux NN-API-Adapter The NPU flexibility is used to optimally accelerate the following frameworks (nonexhaustive list)
  • TensorFlow non-exhaustive hardware support
  • TensorFlowLite full hardware support (including its SoftMax subset)
  • Caffe, Caffe2
  • CNTK, Torch, Theano, Darknet The NPU provides the following neural theoretical performance, below values for 800 MHz (values for 900 MHz overdrive inside parenthesis):
  • Integer operations: 1.2 (1.35) TOPS (8-bit integer) To reduce the required DDR bandwidth during neural computations, the NPU embeds natively 128 Kbytes of memory.

3.6 Memories

3.6.1 External SDRAM

STM32MP25xA/D devices embed a controller for the external SDRAM which supports the following devices STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 15/234 Prerelease product(s)

  • DDR3L, 16- or 32-bit data, up to 2 Gbytes, up to DDR3L-2133 (1066 MHz clock)
  • DDR4, 16- or 32-bit data, up to 4 Gbytes, up to DDR4-2400 (1200 MHz clock)
  • LPDDR4, 16- or 32-bit data, up to 4 Gbytes, up to LPDDR4-2400 (1200 MHz clock)

3.6.2 Embedded SRAM

  • SYSRAM in MPU domain: 256 Kbytes with half/full hardware erase mechanism on reset
  • VDERAM in MPU domain: 128 Kbytes (not usable when either VDEC or VENC is used) with hardware erase mechanism on enable as general purpose RAM
  • SRAM1 in MCU domain: 128 Kbytes with hardware erase mechanism on tamper detection
  • SRAM2 in MCU domain: 128 Kbytes
  • LPSRAM1 in SmartRun domain: 8 Kbytes with hardware erase mechanism on reset The content of this area can be retained in Standby or VBAT mode, and can be protected by the CRC mechanism.
  • LPSRAM2 in SmartRun domain: 8 Kbytes with hardware erase mechanism on reset
  • LPSRAM3 in SmartRun domain: 16 Kbytes
  • RETRAM (retention RAM): 128 Kbytes with hardware erase mechanism on reset The content of this area can be retained in Standby or VBAT mode, and can be protected by ECC and CRC mechanisms.
  • BKPSRAM (backup SRAM): 8 Kbytes with hardware erase mechanism on tamper detection The content of this area can be protected against possible unwanted accesses, and can be retained in Standby or VBAT mode. The content can also be protected by ECC mechanism.

3.7 DDR3L/DDR4/LPDDR4 controller (DDRCTRL)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details).

  • JEDEC compliant LPDDR4 SDRAM up to 2400 MT/s
  • JEDEC compliant DDR4 SDRAM up to 2400 MT/s with DLL on-range
  • JEDEC compliant DDR3L SDRAM up to 2133 MT/s with DLL on-range
  • 2 x 128-bit AXI4 ports – up to 16 QoS levels and up to 3 traffic classes are supported per direction. – CID-based firewalling function with poisoning output signaling Low-power features:
  • Linked with the RCC, ability to move the DDR memory subsystem in self refresh through automatic way, hardware way, or software way (ASR, HSR and SSR).

3.8 Boot modes

At startup, the boot source used by the internal boot ROM is selected by BOOT pins and OTP settings. Table 4. Default interfaces Unless otherwise mentioned in table below.

Table 5. Boot sources

0 UART and USB(2) (3)

1 SD-Card - - - SD-Card SD-Card Serial NAND Serial NOR

3 Development boot(2)

4 Serial NOR - - - Serial NOR Serial NOR SLC NAND Serial NOR

5 Serial NAND - - - - - e•MMC(4) Serial NOR

6 SLC NAND - - - - - e•MMC(4) HyperFlash™

12 Development boot(2)

15 UART and USB(3)

  1. Two flash memory config. Indirect Cortex-A35 boot (from Cortex-M33) or used during Cortex-A35 D1Standby exit
  2. Cannot be override by OTP.
  3. Wait incoming connection on USART2/6 or UART5/8/9 on default pins and USB high-speed device on USB3DR_DP/DM.
  4. Only 8-bit memory is supported as some FMC and OCTOSPIM port2 pins are shared (usage of FMC in 16-bit mode is exclusive of usage of

The default pins used during boot are described in Table 6 . cannot be used with FMC 16 bits. OCTOSPI port2 in 8-bit mode cannot be used with FMC. Table 6. Minimum set of default pins used during boot ROM phase Most can be changed using OTP settings. This table is for default OTP settings.

Interface type Signal Pin IO supply domain FMC SLC NAND 8-bits SLC NAND 16-bits FMC_D1 VDDIO2(1)PE6 FMC_D2 PE7 FMC_D3 PD15 VDD FMC_D4 PD14 FMC_D5 PB13 FMC_D6 PD12 FMC_D7 PB14 FMC_D8 PB5 VDDIO4(2)FMC_D9 PB6 FMC_D10 PB7 FMC_D11 PD13 VDD FMC_D12 PB8 VDDIO4(2) FMC_D13 PB9 FMC_D14 PB11 FMC_D15 PB10 OCTOSPI M Port1 Serial NOR, Serial NAND HyperFlash™ OCTOSPIM_P1_CLK PD0 VDDIO3 OCTOSPIM_P1_NCS1 PD3 OCTOSPIM_P1_IO0 PD4 OCTOSPIM_P1_IO1 PD5 OCTOSPIM_P1_IO2 PD6 OCTOSPIM_P1_IO3 PD7 OCTOSPIM_P1_IO4 PD8 OCTOSPIM_P1_IO5 PD9 OCTOSPIM_P1_IO6 PD10 OCTOSPIM_P1_IO7 PD11 OCTOSPIM_P1_NCLK PD1 OCTOSPIM_P1_DQS PD2 OCTOSPI M Port2 Serial NOR, Serial NAND HyperFlash™ OCTOSPIM_P2_CLK PB10 VDDIO4(2) OCTOSPIM_P2_NCS1 PB8 OCTOSPIM_P2_IO0 PB0 OCTOSPIM_P2_IO1 PB1 OCTOSPIM_P2_IO2 PB2 OCTOSPIM_P2_IO3 PB3 OCTOSPIM_P2_IO4 PB4 OCTOSPIM_P2_IO5 PB5 OCTOSPIM_P2_IO6 PB6 OCTOSPIM_P2_IO7 PB7 OCTOSPIM_P2_NCLK PB11 OCTOSPIM_P2_DQS PB9 SDMMC1 SD-Card or eMMC SDMMC1_CK PE3 VDDIO1 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 18/234 Prerelease product(s)

Interface type Signal Pin IO supply domain SDMMC1 SD-Card or eMMC SDMMC1_CMD VDDIO1 PE2 SDMMC1_D0 (3) PE4 SDMMC2 SD-Card or eMMC SDMMC2_CK PE14 VDDIO2(1)SDMMC2_CMD PE15 SDMMC2_D0(3) PE13 USART2 USART2_RX PA8 VDD USART2_TX PA4 UART5 UART5_RX PB15 VDD UART5_TX PA0 USART6 USART6_RX PF4 VDD USART6_TX PF5 UART8 UART8_RX PF3 VDD UART8_TX PG3 UART9 UART9_RX PB14 VDD UART9_TX PD13 1. Some FMC and SDMMC2 pins are shared, this means that usage of FMC is exclusive of usage of SDMMC2. 2. Some FMC and OCTOSPIM port2 pins are shared, this means that usage of FMC in 16-bit mode is exclusive of usage of OCTOSPIM Port2. 3. Only used as input by boot ROM Although low-level boot is done using internal clocks, ST supplies software packages as well as major external interfaces (such as DDR or USB) require a crystal or an external oscillator to be connected on HSE pins. See the product reference manual for constrains and recommendations regarding connection of HSE pins and supported frequencies.

3.9 Power supply management (PWR)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details).

3.9.1 Power supply scheme

The system requires supply on VDD, VDDA18AON, VDDCPU and VDDCORE to start, and to allow independent supplies for VDDGPU, VDDA18ADC, VBAT, VDD33USB, VDD33UCPD, VDDIO2, VDDIO3, VDDIO4, VDDIO1, and VDDQDDR.

  • VDD power supply input for I/Os (1.8 V or 3.3 V typical)
  • VDDA18AON power supply input for system analog such as reset, power management, oscillators and OTP
  • VBAT optional power supply input for backup domain, and optionally D3 domain when VDD is not present (VBAT mode)
  • VDDCORE digital core domain supply, dependent on VDD supply. VDD must be present before VDDCORE. – VDDCSI, VDDDSI, VDDLVDS, VDDCOMBOPHY, VDDCOMBOPHYTX, and VDDPCIECLK are usually connected to VDDCORE.
  • VDDCPU digital CPU domain supply (Cortex-A35), dependent on VDD supply. VDD must be present before VDDCPU.
  • VDDGPU digital GPU domain supply, dependent on VDD supply. VDD must be present before VDDGPU.
  • VDDQDDR DDR I/O supply
  • VDDA18ADC analog power supply input for ADCs and voltage reference buffers, independent from any other supply
  • VREF+ external reference voltage for ADCs, independent from any other supply – reference voltage output when the voltage reference buffer is enabled – independent external reference voltage input when the voltage reference buffer is disabled STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 19/234 Prerelease product(s)
  • VSSA separate analog and reference voltage ground
  • VDD33USB supply input for USB HS PHY, independent from any other supply
  • VDD33UCPD supply input for USB Type-C CC1 and CC2 pins, independent from any other supply
  • VDDIO3 supply input, mostly for OCTOSPIM_P1 I/Os, independent from any other supply
  • VDDIO4 supply input, mostly for OCTOSPIM_P2 I/Os, independent from any other supply
  • VDDIO2 supply input, mostly for e.MMC I/Os, independent from any other supply
  • VDDIO1 supply input, mostly for SD Card I/Os, independent from any other supply
  • VSS common ground for all supplies except for analog

3.9.2 Power-supply supervisor

The devices have an integrated power-on reset (POR) and power-down reset (PDR) circuitry, coupled with a brownout reset (BOR) circuitry:

  • Power-on reset (POR) The POR supervisor monitors VDD and VDDA18AON power supplies, and compares them to a fixed threshold. The devices remain in reset mode when VDD and VDDA18AON are below this threshold.
  • Power-down reset (PDR) The PDR supervisor monitors VDD and VDDA18AON power supplies. A reset is generated when VDD or VDDA18AON drops below a fixed threshold.
  • Brownout reset (BOR) The BOR supervisor monitors VDD power supply. A 2.7 V BOR thresholds can be enabled through option bytes. A reset is generated when VDD drops below this threshold. The BOR must not be enabled when VDD = 1.8 V typ. is used.
  • Power-on reset VDDCORE (POR_VDDCORE) The POR_VDDCORE supervisor monitors VDDCORE power supply, and compares it to a fixed threshold. The VDDCORE domain remains in reset mode when VDDCORE is below this threshold,
  • Power-down reset VDDCORE (PDR_VDDCORE) The PDR_VDDCORE supervisor monitors VDDCORE power supply. A VDDCORE domain reset is generated when VDDCORE drops below a fixed threshold.
  • Power-on reset VDDCPU (POR_VDDCPU) The POR_VDDCPU supervisor monitors VDDCPU power supply, and compares it to a fixed threshold. The VDDCPU domain remains in reset mode when VDDCPU is below this threshold.
  • Power-down reset VDDCPU (PDR_VDDCPU) The PDR_VDDCPU supervisor monitors VDDCPU power supply. A VDDCPU domain reset is generated when VDDCPU drops below a fixed threshold.
  • Power-on reset VSW (POR_VSW) The POR_VSW supervisor monitors VSW power supply, and compares it to a fixed threshold. The VSW domain remains in reset mode when VSW is below this threshold. The devices also include monitoring which can generate tamper events, interrupt, or wake-up:
  • Programmable voltage detector (PVD) The PVD monitors the PVD_IN pin, and compares it to a fixed threshold. An interrupt or a wake-up can be generated when PVD_IN is below or above the threshold.
  • VDDCORE monitoring Monitors VDDCORE power supply and compares it to a fixed threshold. A tamper event, an interrupt, or a wake-up can be generated when VDDCORE is below or above the threshold.
  • VDDCPU monitoring Monitors VDDCPU power supply, and compares it to a configurable threshold. A tamper event, an interrupt, or a wake-up can be generated when VDDCPU is below or above the threshold.
  • VDDGPU monitoring Monitors VDDGPU power supply and compares it to a configurable threshold. An interrupt or a wake-up can be generated when VDDGPU is below or above the threshold. A GPU reset is also generated if VDDGPU is below the threshold (VDDGPURDY = 0). STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 20/234 Prerelease product(s)
  • Peripheral voltage monitoring Monitors independently VDDIO2, VDDIO3, VDDIO4, VDDIO1, VDD33UCPD, VDD33USB and VDDA18ADC power supplies with fixed thresholds. An interrupt or a wake-up can be generated when supplies are below or above the thresholds.

3.10 Low-power strategy

Several low-power modes are available to save power when the Cortex-A35 and/or the Cortex-M33 do not need to execute code (when waiting for an external event). It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time, and available wake-up sources.

  • Slowing down system clocks (see RCC section in the reference manual)
  • Controlling individual peripheral clocks (see RCC section in the reference manual)
  • Low-power modes: – CSleep (CPU clock stopped) – CStop (CPU subsystem clock stopped) – D1 DStop1 (CPU subsystem clock stopped, normal mode signaled to external regulator) – D1 DStandby (domain power down and wake-up via reset) – Stop1, LP-Stop1, and LPLV-Stop1 (system clock stalled, normal or low-power mode signaled to external regulator supplying the VDDCPU and the VDDCORE) – Stop2, LP-Stop2, and LPLV-Stop2 (system clock stalled, powered down mode signaled to external regulator supplying the VDDCPU, and normal or low-power mode signaled to external regulator supplying the VDDCORE) – Standby1 (system powered down and D3 domain in autonomous mode running with local clocks) – Standby2 (system powered down, D3 domain also in power down)

3.11 Resource isolation framework (RIF)

The RIF is a comprehensive set of hardware blocks designed to enforce and manage the isolation of STM32 hardware resources like memory and peripherals. Within a defined hardware execution compartment (eight are available), privileged, unprivileged, secure, and non- secure application softwares can assign their own embedded memory buffers, external memory regions, and peripherals thanks to the RIF hardware. The RIF architectural framework extends to FMC, SYSCFG, IPCC, HSEM, DMA, RTC, TAMP, RCC, PWR, EXTI, or GPIO.

3.12 Reset and clock controller (RCC)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). The RCC manages the generation of all clocks, as well as the clock gating and the control of system and peripheral resets. It provides a high flexibility in the choice of clock sources, and allows application of clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the peripheral activity rate. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 21/234 Prerelease product(s)

3.12.1 Features

  • RIF aware
  • Reset part: – Generation of local and system reset – Bidirectional pad reset (NRST) to reset of external devices, or to reset the device – Output pad reset (NRSTC1MS) to reset of external mass-storage devices used by the Cortex-A35
  • Clock generation part: – Generation and distribution of clocks for the complete system – 5 separate PLLs (excluding external Cortex-A35, DDRCTRL, and GPU ones): ◦ Integer or fractional mode ◦ Spread-spectrum function to reduce the amount of EMI peaks ◦ Possibility to change on-the-fly the fractional ratios of the PLLs – Smart clock gating for reduction of power dissipation – 2 external oscillators: ◦ HSE that supports a wide range of crystals: 16 to 48 MHz ◦ LSE for 32.768 kHz crystals – 3 Internal oscillators: ◦ HSI that runs around 64 MHz ◦ MSI that runs around 16 MHz or 4 MHz ◦ LSI that runs around 32 kHz – Buffered clock outputs for external devices
  • Two independent interrupt interfaces (one dedicated to Cortex-A35, and one dedicated to Cortex-M33)
  • Two independent failure events (HSE and LSE)
  • Two independent events to wake up processors (one dedicated to Cortex-A35 and one dedicated to Cortex-M33)

3.12.2 Clock management

The RCC provides a high flexibility to the application in the choice of the clock generators:

  • from HSI, high-speed internal oscillator (~ 64 MHz)
  • from HSE, high-speed external oscillator (16 to 48 MHz)
  • from LSE; low-speed external oscillator (32 kHz)
  • from LSI, low-speed internal oscillator (~ 32 kHz)
  • from MSI, low-power internal oscillator (~ 4 MHz or ~ 16 MHz) The RCC offers a good flexibility for the application to select the appropriate clock for CPUs and peripherals. More especially for peripherals that need a specific clock like SPI(I2S), SAI, and SDMMC. Each clock source can be switched on or off independently in order to optimize the power consumption. There are mainly three clock paths:
  • Cortex-A35 bus matrix
  • Cortex-M33 and its bus matrix
  • peripheral kernel clocks The Cortex-A35, the GPU, and DDRCTRL clocking are derived locally because of high frequency use. The RCC manages only source clocks for their related local PLLs.

3.12.3 Reset sources

There are several sources able to generate a reset:

  • supply monitors (VDD, VDDCORE, VDDCPU , VDDGPU or VSW) lower than expected values
  • independent watchdogs timeout
  • D1 domain exit from DStandby state
  • exit from Standby mode
  • external signals driving the NRST pin STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 22/234 Prerelease product(s)
  • software commands The coverage (or scope) of the resets differ according to the source initiating the reset, with the following categories:
  • power-on/off resets
  • system resets
  • local resets An application reset can be generated from one of the following sources:
  • reset from the NRST pin
  • reset from low-voltage detection on VDD
  • reset from the independent watchdogs
  • software reset from RCC registers
  • failure on HSE
  • RETRAM CRC or ECC error A system reset can be generated from one of the following sources:
  • reset from application reset
  • reset from low-voltage detection on VDDCORE
  • a reset from low-voltage detection on VDDCPU The NRST reset is activated by:
  • low voltage on VDD
  • failure on HSE
  • reset from the independent watchdogs
  • software reset from RCC registers
  • RETRAM CRC or ECC error
  • assertion of NRST by an external source

3.13 Hardware semaphore (HSEM)

The hardware semaphore provides 16 (32-bit) register-based semaphores. The semaphores can be used to ensure synchronization between different processes that run on a core and between different cores. The HSEM provides a non-blocking mechanism to lock semaphores in an atomic way. The following functions are provided:

  • Locking a semaphore can be done in two ways: – 2-step lock: by writing CoreID and ProcessID to the semaphore, followed by a read check. – 1-step lock: by reading the CoreID from the semaphore
  • Interrupt generation when a semaphore is freed – Each semaphore can generate an interrupt on one of the interrupt lines.
  • Semaphore clear protection – A semaphore is only cleared when CoreID and ProcessID matches.
  • Global semaphore clear per CoreID

3.14 Inter-processor communication controller (IPCC1/2)

The IPCC is used to communicate data between two processors. It provides a non-blocking signaling mechanism to post and retrieve communication data in an atomic way (signaling for 16 channels for IPPC1, and four channels for IPCC2). The IPCC communication data must be located in a common memory, which is not part of the IPCC.

3.14.1 Main features

  • Status signaling for the four channels – Channel occupied/free flag, also used as lock STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 23/234 Prerelease product(s)
  • Two interrupt lines per processor – One for RX channel occupied (communication data posted by sending processor) – One for TX channel free (communication data retrieved by receiving processor)
  • Interrupt masking per channel – Channel occupied mask – Channel free mask
  • Two channel operation modes – Simplex (each channel has its own communication data memory location) – Half duplex (a single channel in associated to a bidirectional communication data information memory location)

3.15 General-purpose input/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (with or without pull-up or pull-down), or as peripheral alternate function. Some of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs are in analog mode to reduce power consumption. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/O registers. Access to each GPIO configuration bits can be restricted to secure‑only and/or privileged‑only. These configuration bits can also be allocated to a specific CPU.

3.16 Bus-interconnect matrix

For more details on interconnect, see the reference manual (RM0457). STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 24/234 Prerelease product(s)

Figure 2. AXI STNoC multi-frequency network

600 MHz 400 MHz 300 MHz 200 MHz

Figure 3. MCU multi-Layer AHB 400 MHz

Figure 4. MCU multi-Layer AHB 200 MHz

400 MHz MLAHB

Figure 5. SmartRun multi-Layer AHB matrix

200 MHz MLAHB

3.17 High-performance DMA controllers (HPDMA1/2/3)

  • AXI master and AHB master
  • Memory-mapped data transfers from a source to a destination: – Peripheral-to-memory – Memory-to-peripheral – Memory-to-memory – Peripheral-to-peripheral
  • Autonomous data transfers during Sleep and Stop modes
  • Per channel event generation
  • Per channel interrupt generation
  • 16 concurrent DMA channels
  • Per channel FIFO
  • Linked-list support
  • TrustZone support
  • Privileged/unprivileged support
  • Channel isolation support STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 27/234 Prerelease product(s)

3.18 Low-power DMA controller (LPDMA1)

  • AHB master
  • Memory-mapped data transfers from a source to a destination: – Peripheral-to-memory – Memory-to-peripheral – Memory-to-memory – Peripheral-to-peripheral
  • Autonomous data transfers during Sleep and Stop modes
  • Per channel event generation
  • Per channel interrupt generation
  • 4 concurrent DMA channels
  • Linked-list support
  • TrustZone support
  • Privileged/unprivileged support
  • Channel isolation support

3.19 Cortex-M33 nested vectored interrupt controller (NVIC)

The devices embed a NIC that can support up to 320 maskable interrupt channels, not including the Cortex®‑M33 interrupt lines.

  • 16 programmable priority levels
  • Closely coupled NVIC gives low-latency interrupt processing
  • Interrupt entry vector table address passed directly to the core
  • Early processing of interrupts
  • Processing of late arriving, higher-priority interrupts
  • Tail chaining
  • Processor context automatically saved
  • Interrupt entry restored on interrupt exit with no instruction overhead NVIC registers are banked across secure and non-secure states. The NVIC provides flexible interrupt management features with minimum interrupt latency.

3.20 Cortex-M0+ nested vectored interrupt controller (NVIC)

The devices embeds an NVIC that can support up to 32 maskable interrupt channels, not including the Cortex- M0+ core interrupt lines.

  • 4 programmable priority levels
  • Closely coupled NVIC that gives low-latency interrupt processing
  • Interrupt entry vector table address passed directly to the core
  • Early processing of interrupts
  • Processing of late arriving, higher-priority interrupts
  • Support tail chaining
  • Processor context automatically saved
  • Interrupt entry restored on interrupt exit with no instruction overhead This NVIC provides flexible interrupt management features with minimum interrupt latency.

3.21 Extended interrupt and event controller (EXTI1/2)

The EXTI manages individual CPU and system wake-up through configurable and direct event inputs. It provides wake-up requests to the power control, and generates an interrupt request to the CPU NVIC or GIC, and events to the CPU event inputs. For each CPU, an additional event generation block (EVG) is needed to generate the CPU event signal. The EXTI wake-up requests allow the system to be woken up from Stop mode, and CPUs to be woken up from CStop and CStandby modes. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 28/234 Prerelease product(s)

The interrupt request and event request generation can also be used in Run mode. The EXTI also includes the EXTI I/Oport selection. Each interrupt or event can be set as secure to restrict access to secure software only. EXTI1 is shared between Cortex-A35 and Cortex-M33 while EXTI2 is shared between all cores.

3.22 Cyclic redundancy check calculation unit (CRC)

The CRC calculation unit is used to get a CRC code using a programmable polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps computing a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

3.23 Flexible memory controller (FMC)

The FMC main features are the following:

  • Interface with static-memory mapped devices including: – NOR flash memory – Static or pseudo-static random access memory (SRAM, PSRAM) – NAND flash memory with 4-bit/8-bit BCH hardware ECC
  • 8-,16-bit data bus width
  • Independent chip-select control for each memory bank
  • Independent configuration for each memory bank
  • Write FIFO

3.24 Octo-SPI memory interface (OCTOSPI1/2)

The OCTOSPI supports two protocols used by most external serial memories such as serial PSRAMs, serial NAND and serial NOR flash memories, HyperRAMs, and HyperFlash memories:

  • Indirect mode: all the operations are performed using the OCTOSPI registers.
  • Automatic status-polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting.
  • Memory-mapped mode: the external memory is memory mapped ,and is seen by the system as if it was an internal memory supporting both read and write operations. The OCTOSPI supports multiple protocols:
  • XSPI protocol and its various flavors (such as XCELLA, OCTABUS, HyperBus™ as defined by memory providers)

3.25 Octo-SPI I/O manager (OCTOSPIM)

The OCTOSPIM is an internal multiplexer:

  • Efficient OCTOSPI pin assignment by allowing pin swapping
  • Multiplexing two single-, dual-, quad, or octal-SPI interfaces over the same external bus: interfaces (with for example different security attributes) share then the same memory, or access two memories embedded in a multichip package.

3.26 Analog-to-digital converters (ADC1/2/3)

STM32MP25xA/D devices embed three analog-to-digital converters, which resolution can be configured to 12, 10, or 8 bits. Each ADC shares up to 20 channels, performing conversions in single-shot or scan mode. In scan mode, an automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:

  • simultaneous ADC1/ADC2 conversion
  • interleaved ADC1/ADC2 conversion The ADC can be served by DMA, thus allows the automatic transfer of ADC converted values to a destination location without any software action. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 29/234 Prerelease product(s)

In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some, or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. In order to synchronize A/D conversion, the ADCs can be triggered by timers.

3.27 Digital temperature sensor (DTS)

The DTS is a high-precision low-power junction temperature sensor, based on a configurable controller plus one or multiple embedded temperature sensors. The sensor can operate in two distinct modes to provide temperature readings:

  • first mode used to a provide calibrated accurate temperature
  • second mode that does not require any calibration Main features:
  • Two programmable (rise or fall) hardware alarms incorporating hysteresis
  • Status registers recording the minimum and maximum data values received
  • A power-up timer with IRQ to support manual operation
  • A calibration sequence requiring no knowledge of die temperature.

3.28 VBAT operation

The VSW domain supplies the RTC, the TAMP, the LSI, the LSE, the IWDG5, the backup registers, the LPSRAM1, the retention RAM, and the backup SRAM. In order to optimize the battery duration, this power domain is supplied by VDD when available, or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD has dropped below the PDR level. The voltage on VBAT pin can be provided by an external battery, by a supercapacitor, or directly by VDD. In the later case, VBAT mode is not functional. VBAT operation is activated when VDD is not present. Note: None of these events (external interrupts, watchdog reset, TAMP event, or RTC alarm/events) can directly restore the VDD supply, and force the device out of the VBAT operation. Nevertheless, watchdog reset (taken as a tamper event), TAMP events, and RTC alarm/events can be used to generate a signal to an external circuitry (typically a PMIC) that can restore the VDD supply.

3.29 Voltage reference buffer (VREFBUF)

STM32MP25xA/D devices embed a voltage reference buffer which can be used as voltage reference for ADC, and as voltage reference for external components through VREF+ pin. An external voltage reference must be provided through the VREF+ pin when the internal voltage reference buffer is off.

3.30 Multifunction digital filter (MDF1)

The MDF is a high-performance module dedicated to the connection of external sigma-delta (Σ∆) modulators.

3.30.1 Features

  • 8 serial digital inputs: – configurable SPI interface to connect various digital sensors – configurable Manchester coded interface support – compatible with PDM interface to support digital microphones
  • 2 common clocks input/output for ΣΔ modulator(s)
  • Flexible matrix (BSMX) for connection between filters and digital inputs
  • 2 inputs for connecting internal ADCs STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 30/234 Prerelease product(s)
  • 8 flexible digital filter paths, including – A Configurable CIC filter: ◦ Can be split into 2 CIC filters: high resolution filter, and out-off limit detector ◦ Can be configured in Sinc4 filter ◦ Can be configured in Sinc5 filter ◦ Adjustable decimation ratio – A reshape filter to improve the out-off band rejection and in-band ripple – A high pass filter to cancel the DC offset – An offset error cancellation – Gain control – Saturation blocks – An out-off limit detector
  • Short-circuit detector,
  • Clock absence detector
  • 16 or 24-bit signed output data resolution,
  • Continuous or single conversion,
  • Possibility to delay independently each bitstream
  • Various trigger possibilities
  • Break generation on out-of limit or short-circuit detector events
  • Autonomous functionality in Stop modes
  • DMA can be used to read the conversion data
  • Interrupts services Targeted applications:
  • Audio: speech capture
  • Motor control
  • Metering

3.31 Audio digital filter (ADF1)

The audio digital filter (ADF) is a high-performance module dedicated to the connection of external ΣΔ modulators.

3.31.1 Features

  • 1 serial digital input: – configurable SPI interface to connect various digital sensors – configurable Manchester coded interface support – compatible with PDM interface to support digital microphones
  • 2 common clocks input/output for ΣΔ modulators
  • 1 flexible digital filter paths, including: – A MCIC filter configurable in Sinc4 or Sinc5 filter with an adjustable decimation ratio – A reshape filter to improve the out-off band rejection and in-band ripple – A high pass filter to cancel the DC offset – Gain control – Saturation blocks
  • Clock absence detector
  • Sound activity detector
  • 4-bit signed output data resolution
  • Continuous or single conversion
  • Possibility to delay the selected bitstream
  • One trigger input
  • Autonomous functionality in Stop modes STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 31/234 Prerelease product(s)
  • DMA can be used to read the conversion data
  • Interrupts services Targeted applications:
  • Audio: speech capture
  • Metering

3.32 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8- to 14-bit parallel interface, to receive video data. The camera interface can support a resolution of 1 Mpixels @15 fps.

  • Programmable polarity for the input pixel clock and synchronization signals
  • Parallel data communication can be 8-, 10-, 12-, or 14-bit
  • 8-bit progressive video monochrome or RawBayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)
  • Continuous mode or snapshot (a single frame) mode
  • Capability to automatically crop the image

3.33 Parallel synchronous slave interface (PSSI)

The PSSI and the DCMI use the same circuitry.These two peripherals cannot be used at the same time: when using the PSSI, DCMI registers cannot be accessed, and vice-versa. The PSSI and the DCMI share also the same alternate functions and interrupt vector. The PSSI is a generic synchronous 8/16-bit parallel data input/output slave interface. It enables the transmitter to send a data valid signal that indicates when the data is valid, and the receiver to output a flow control signal that indicates when it is ready to sample the data. Main features:

  • Slave mode operation
  • 8-bit or 16-bit parallel data input or output
  • 8-word (32-byte) FIFO
  • Data enable (PSSI_DE) alternate function input, and Ready (PSSI_RDY) alternate function output

3.34 Digital camera interface with pixel processing (DCMIPP)

  • Parallel input interface: – Up to 16 bits @120 MHz, up to 2 Mpixels sensors @30 fps – Pixel format: RGB565, 888, YUV422, RawBayer/Mono 8/10/12/14
  • When connected to CSI-2 input interface: – Up to 200 Mpixel/s, up to 5 Mpix sensors @30 fps, supports MIPI CSI-2 v1.3 – Pixel format: all MIPI CSI-2 v1.3: RGB565, 888, YUV422, RawBayer – Features: interleaved packets, 4 virtual channels
  • Flow selection and frame control
  • Byte-to-pixel conversion
  • Statistic removal
  • Bad pixel removal (automatic detection and correction of bad pixels from sensor array)
  • Decimation of one pixel every 1/2/4/8
  • Integrated image processing used to connect low-cost camera module without any embedded ISP – Color conversion to adapt to the sensor and tune the Illumination – Contrast enhancement – RawBayer to RGB conversion (demosaicing) – Exposure control – Statistics extraction
  • Decimation on pipe 0 (pipe dump) STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 32/234 Prerelease product(s)
  • Multiple pipelines for parallel applications: – Pipe0 (for data dump), for a direct dump without processing – Pipe1 (for main use), with downsize, color conversion, YUV-planar – Pipe2 (for ancillary use), with downsize, color conversion, YUV-planar
  • Downsize – Box-filtering, with any decimal ratio, up to 8x8, on pipe1 and pipe2
  • Gamma conversion
  • RGB to YUV color conversion
  • Output pixel format: – Pipe0: any data as is, Y/Rb: 8/10/12/14 statistics, bitstreams – Pipe2: RGB888, RGB565, YUV422-1, Y8, ARGB and RGBA (co-planar only) – Pipe1: Pipe2 formats + YUV422-2, YUV420-2, YUV420-3 (multi-planar possible)
  • AXI master

3.35 Camera serial interface (CSI)

The CSI provides an interface between the system and the PHY, allowing communication with a CSI-2 compliant camera.

  • Compliant with MIPI Alliance standard v1.3
  • Up to two data lanes, up to 2.5 Gbit/s per lane in high-speed (HS) mode and 10 Mbit/s in low-power (LP) mode
  • Data transmission in HS and LP modes
  • Escape mode (ESC), and ultra-low-power state mode (ULPS)
  • CSI-2 virtual channel and data type filtering supporting interleaved data – Up to 4 virtual channels – Support data formats specified into the MIPI Alliance standard for CSI-2 v1.3 (18 data formats, plus the user defined onces, up to 7 independent data types)
  • Internal connection with the DCMIPP

3.36 LCD-TFT display controller (LTDC)

The LTDC handles display composition and rotation, with the following main features:

  • 3 display layers with dedicated FIFO
  • Input pixel flexible format, including YUV420 full-planar
  • Secure layer: protected access to buffer and configuration registers
  • Output rotation: 90 and 270 degrees
  • Horizontal and vertical mirror
  • Color lookup-table, color keying, gamma, and dithering on output LTDC parallel interface:
  • Provides a 24-bit parallel digital RGB, and delivers all signals to interface directly to a broad range of LCD and TFT panels.
  • Up to 150 Mpixel/s, which correspond up to FHD (1920 × 1080) @60 fps resolution with HDMI blankings
  • Output pixel formats: RGB888, RGB666, RGB565, YUV422-16 bits LTDC DSI interface:
  • The LTDC provide pixels to the display serial interface (DSI). LTDC LVDS interface:
  • The LTDC provide pixels to the LVDS display interface (LVDS). STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 33/234 Prerelease product(s)

3.37 Display serial interface (DSI)

Note: Features may be limited or absent in some devices or packages (see Section 2: Description for details). The DSI is part of a group of communication protocols defined by the MIPI Alliance. The MIPI DSI host controller is a digital core that implements all protocol functions defined in the MIPI DSI specification. It provides an interface between the system and the MIPI D-PHY that allows the communication with a DSI- compliant display.

  • Compliant with MIPI Alliance standards
  • Interface with MIPI D-PHY
  • Supports all commands defined in the MIPI Alliance specification for DCS
  • Bidirectional communication and escape mode support through data lane 0
  • Supports non-continuous clock in D-PHY clock lane for additional power saving
  • Supports ultra-low-power mode with PLL disabled
  • ECC and checksum capabilities
  • Support for end of transmission packet (EoTp)
  • Fault recovery schemes
  • Configurable selection of system interfaces: – AMBA APB for control and optional support for generic and DCS commands – Video mode interface through LTDC – Adapted command mode interface through LTDC – Independently programmable virtual channel ID in video mode, adapted command mode and APB slave
  • Video mode interfaces features: – LTDC interface color coding mappings into 16, 18 and 24-bit interface – Programmable polarity of all LTDC interface signals
  • Adapted interface features: – Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands – LTDC interface color coding mappings into 16, 18 and 24-bit interface
  • Video mode pattern generator
  • Up to 4 × data lanes, up to 2.5 Gbps each
  • Up to QXGA (2048 × 1536) @60 fps

3.38 LVDS display interface (LVDS)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). The LVDS supports the following high-level features:

  • FPD-Link-I and OpenLDI (v0.95) protocols
  • Single-link or dual-link operation
  • Single-display or double-display (with the same content duplicated on both)
  • Flexible bit-mapping, including JEIDA and VESA
  • RGB888 or RGB666 output
  • Up to 2 links of 4 data lanes, up to 1.1 Gbit/s per lane – FPD bitrate: 784 Mbit/s per lane (112 Mpixel/s per link, 224 Mpixel/s if dual Link) – OpenLDI bitrate: 1100 Mbit/s per lane (157 Mpixel/s per link, 314 Mpixel/s if dual link)
  • Up to QXGA (2048 × 1536) @60 fps with dual link
  • Up to WSXGA+ (1680 × 1050) @60 fps with single FPD link (1080p60 supported with OpenLDI)

3.39 Video encoder (VENC)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 34/234 Prerelease product(s)

  • Video encode – H264 (MPEG4_Part10/AVC, baseline/main/high up to 5.2), VP8 – Up to 1080p60 for H264/VP8 (performance shared with the VDEC)
  • Still-image encode – JPEG (baseline interleaved) – Up to 500 Mpixel/s for JPEG (performance shared with the VDEC)
  • VDERAM – 128 Kbytes – Hardware handshake between VENC and VDEC – Can be statically assigned to CPU as additional system RAM by SYSCFG setting

3.40 Video decoder (VDEC)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details).

  • Video decode – H264 (MPEG4_Part10/AVC, baseline/main/high up to 5.2), VP8 – Up to 1080p60 for H264/VP8 (performance shared with the VENC)
  • Still-image decode – JPEG (baseline interleaved). – Up to 500 Mpixel/s for JPEG (performance shared with the VENC)
  • VDERAM – 128 Kbytes – Hardware handshake between VENC and VDEC – Can be statically assigned to CPU as additional system RAM by SYSCFG setting

3.41 True random number generator (RNG )

All devices embed an RNG that deliver s 32-bit random numbers generated by an integrated analog circuit.

3.42 Hash processor (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-2 family, SHA-3 family), and the HMAC (keyed-hash message authentication code) algorithm. The HMAC is suitable for applications that require a message authentication. The HASH computes FIPS (federal information processing Standards) approved digests of 160-, 224-, 256-, 384-, and 512-bit length, for messages of any length:

  • less than 264 bits (for SHA-1, SHA-224, and SHA-256)
  • less than 2128 bits (for SHA-384, SHA-512)

3.43 Public key accelerator (PKA)

The PKA is intended for ECDSA signature generation and verification. For a given operation, all needed computations are performed within the accelerator: no further hardware/ software elaboration is needed to process inputs or outputs.

3.44 Boot and security and OTP control (BSEC)

The BSEC is used to control an OTP (one-time programmable) fuse box, used for embedded non-volatile storage for device configuration and security parameters. Embedded non-volatile secrets are stored in the BSEC upper area that is only accessible while BSEC is operating in a closed state. In open state those non-volatile secrets are permanently hidden. The BSEC use is reserved to trusted domain CPU, and boot CPU following a BSEC reset (cold/warm or hot). STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 35/234 Prerelease product(s)

3.45 Timers and watchdogs

system timers in each Cortex-A35. All timer counters can be frozen in debug mode. The table below compares features of the different timers. Table 7. Timer feature comparison

  1. The maximum timer clock depends on RCC settings.
  2. 16 MHz bus clock when supplied by the backup regulator (LP-Stop1/2, LPLV-Stop1/2 or Standby1).
  3. 32 kHz timer clock in autonomous mode (Stop1/2, LP-Stop1/2, LPLV-Stop1/2 or Standby1).

3.45.1 Advanced-control timers (TIM1/8/20)

  • input capture
  • output compare
  • PWM generation (edge- or center-aligned modes)
  • one-pulse mode output STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 36/234 Prerelease product(s)

If configured as standard 16-bit timers, the advanced-control timers have the same features as the general- purpose timers. If configured as 16-bit PWM generators, they have full modulation capability (0 to 100%). The advanced-control timers can work together with general-purpose timers via the timer link feature for synchronization or event chaining. TIM1, TIM8 and TIM20 support independent DMA request generation.

3.45.2 General-purpose timers (TIM2/3/4/5/10/11/12/13/14/15/16/17)

There are twelve synchronizable general-purpose timers embedded in STM32MP25xA/D devices (see Table 7 for differences).

  • TIM2, TIM3, TIM4, TIM5 These timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. They feature four independent channels for input capture/output compare, PWM, or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. These timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1, TIM8 and TIM20, via the timer link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 have independent DMA request generation. They can handle quadrature (incremental) encoder signals, and the digital outputs from one to four halleffect sensors.
  • TIM10, TIM11, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM, or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases.

3.45.3 Basic timers (TIM6/TIM7)

These timers are used as a generic 16-bit time base, and support independent DMA request generation.

3.45.4 Low-power timer (LPTIM1/2/3/4/5)

These low-power timers have an independent clock and run in Stop mode if they are clocked by LSE, LSI, or an external clock. They can wake up the device from Stop mode.

  • 16-bit up counter with 16-bit autoreload register
  • 16-bit compare register
  • Configurable output: pulse, PWM
  • Continuous/one-shot mode
  • Selectable software/hardware input trigger
  • Selectable clock source: – Internal clock source: LSE, LSI, HSI (RCC flexgen output) – External clock source over LPTIM input (working even with no internal clock source running, used by the pulse counter application)
  • Programmable digital glitch filter
  • Encoder mode (LPTIM1/2)

3.45.5 Independent watchdog (IWDG1/2/3/4/5)

The IWDG is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI). As it operates independently from the main clock, the IWDG can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

3.45.6 System window watchdog (WWDG1/2)

The WWDG is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 37/234 Prerelease product(s)

3.45.7 SysTick timer

This timer is embedded in the Cortex-M33 (two instances, secure and non-Secure) , and in the Cortex-M0+ core. It is dedicated to real-time operating systems, but can also be used as standard downcounter.

  • 24-bit downcounter
  • Autoreload capability
  • Maskable system interrupt generation when the counter reaches 0
  • Programmable clock source

3.45.8 Cortex-A35 generic timers (CNT)

The Cortex-A35 generic timers are fed by value from system timing generation (STGEN). The Cortex-A35 processor provides a set of four timers for each processor:

  • Physical timer for use in secure and non-secure modes. The registers for the physical timer are banked to provide secure and non-secure copies.
  • Virtual timer for use in non-secure mode
  • Physical timer for use in hypervisor mode These generic timers are not memory-mapped peripherals: they are accessible only by specific Cortex-A35 coprocessor instructions (cp15).

3.46 System timer generation (STGEN)

The STGEN generates a time-count value that provides a consistent view of time for all Cortex-A35 generic timers.

  • 64-bit wide to avoid roll-over issues
  • Starts from zero or a programmable value
  • control APB interface (STGENC) that enables the timer to be saved and restored across powerdown events
  • Read-only APB interface (STGENR) that enables the timer value to be read by nonsecure software and debug tools
  • timer value incrementing that can be stopped during system debug

3.47 Real-time clock (RTC)

The RTC provides an automatic wake-up to manage all low-power modes. It is an independent BCD timer/counter that provides a time-of-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wake-up flag with interrupt capability. After backup domain reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode, or under reset).

  • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year
  • Daylight saving compensation programmable by software
  • Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields.
  • Automatic wake-up unit that generates a periodic flag that triggers an automatic wakeup interrupt
  • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.
  • Accurate synchronization with an external clock using the subsecond shift feature
  • Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds
  • Timestamp function for event saving STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 38/234 Prerelease product(s)
  • Maskable interrupts/events: – Alarm A – Alarm B – Wake-up interrupt – Timestamp
  • TrustZone support: – RTC fully securable – Alarm A, alarm B, wake-up timer and timestamp individual secure or non-secure configuration

3.48 Tamper and backup registers (TAMP)

The 128 x 32-bit backup registers are retained in all low-power modes, and in VBAT mode. They can be used to store sensitive data as their content is protected by a tamper detection circuit. 16 tamper pins (eight input and eight outputs), and 14 internal tampers are available for anti-tamper detection. The eight external tamper pins can be configured for edge detection, edge and level, level detection with filtering, or up to eight active tamper which increases the security level by auto-checking that tamper pins are not externally opened or shorted.

  • 128 backup registers (TAMP_BKPxR) implemented in the RTC domain that remains powered-on by VBAT when the VDD power is switched off
  • 8 external tamper detection events: – Each external event can be configured to be active or passive. – External passive tampers with configurable filter and internal pull-up
  • 14 internal tamper events
  • Any tamper detection can generate an RTC timestamp event.
  • Any tamper detection erases backup registers.
  • TrustZone support: – Tamper secure or non-secure configuration – Backup registers configuration in three configurable-size areas: ◦ 1 read/write secure area ◦ 1 write secure/read non-secure area ◦ 1 read/write non-secure area
  • Monotonic counter

3.49 Inter-integrated circuit interface (I2C1/2/3/4/5/6/7/8)

STM32MP25xA/D devices embed eight I2C interfaces, that handle communications between the device and the serial I2C bus. Each I2C interface controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports:

  • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 Kbit/s – Fast-mode (Fm), with a bitrate up to 400 Kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching
  • System management bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert
  • Power system management protocol (PMBus) specification rev 1.1 compatibility STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 39/234 Prerelease product(s)
  • Independent clock: a choice of independent clock sources that allows the I2C communication speed to be independent from the PCLK reprogramming
  • Wake-up from Stop mode on address match
  • Programmable analog and digital noise filters
  • 1-byte buffer with DMA capability

3.50 Improved inter-integrated circuit (I3C1/2/3/4)

STM32MP25xA/D devices embed four I3C interfaces, that handle communication between the device and others that are all connected on an I3C bus, like sensors and host processors. The I3C peripheral implements all required features of the MIPI I3C specification v1.1. It can control all I3C bus‑specific sequencing, protocol, arbitration and timing, and can be acting as controller (formerly known as master), or as target (formerly known as slave). The I3C peripheral, acting as controller, improves the I2C interface features still preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast‑mode (Fm) or legacy I2C fast‑mode plus (Fm+), provided that this latter does not perform clock stretching. The I3C peripheral can be used with DMA in order to off‑load the CPU.

  • MIPI I3C specification v1.1 (see I3C section in the reference manual), as: – I3C primary controller – I3C secondary controller – I3C target
  • Registers configuration from the host application via the APB slave port
  • Queued transfers: – Transmit FIFO (TX‑FIFO) for data bytes/words to be transmitted on I3C bus – Receive FIFO (RX‑FIFO) for received data bytes/words on I3C bus – Control FIFO (C‑FIFO) for control words to be sent on I3C bus, when controller – Status FIFO (S‑FIFO) for status words as received on I3C bus, when controller – For each FIFO, optional DMA mode with a dedicated DMA channel
  • Messages: – Legacy I2C read/write messages to legacy I2C targets in Fm/Fm+ – I3C SDR read/write private messages – I3C SDR (write) broadcast CCC messages – I3C SDR read/write direct CCC messages
  • Frame‑level management, when controller: – Software‑triggered or hardware‑triggered transfer – Optional C‑FIFO and TX‑FIFO preload – Multiple messages encapsulation – Optional arbitrable header
  • Programmable bus timing, when controller – SCL high and low period – SDA hold time – Bus free (minimum) time (between a stop and a start) – Bus available/idle condition time, maximum clock stall time – Minimum clock stall time during 9th bit
  • Target‑initiated requests management: – In‑band interrupts, with programmable IBI payload (up to 4 bytes) – Bus control request, with recovery flow support and hand‑off delay – Hot‑join mechanism – Pending read notification STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 40/234 Prerelease product(s)
  • Bus error management – M0, M1, M2, and M3, when controller – S0, S1, S2, S3, S4, S5, and S6 when target – bus control switch error and recovery – target reset
  • Separately programmed event/flag generation and management – Separated identification and clear control – Host application notification via event/flag polling, and/or via interrupt with a perevent programmable enable – Error type identification
  • Autonomous mode and transfers during Sleep and Stop modes via DMA
  • Autonomous wake‑up on – Slave request acknowledge, when controller – Missed start detection, when target – Reset pattern detection, when target

3.51 Universal synchronous asynchronous receiver transmitter (USART1/2/3/6,

UART4/5/7/8/9) STM32MP25xA/D devices embed four USART and five UART (see Table 8. USART/UART features for feature summary). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode, and have LIN master/slave capability. They provide hardware management of CTS and RTS signals, and RS485 Driver Enable. They can communicate at speeds of up to 10 Mbit/s. The USARTs embed a 64-bytes transmit FIFO (TXFIFO) and a 64-bytes receive FIFO (RXFIFO). The FIFO mode is enabled by software, and is disabled by default. All USARTs provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. They have a clock domain independent from the CPU clock: this allows the USARTx to wake up the device from Stop mode using baudrates up to 200 Kbaud. Wake-up events from Stop mode are programmable and can be one of the following:

  • start bit detection
  • any received data frame
  • a specific programmed data frame All USARTs can be served by the DMA controller. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 41/234 Prerelease product(s)

Table 8. USART/UART features

3.52 Low-power universal asynchronous receiver transmitter (LPUART1)

allows multiprocessor communication. software, and is disabled by default. The LPUART has a clock domain independent from the CPU clock, and can wake up the system from Stop mode.

  • a start bit detection
  • any received data frame
  • a specific programmed data frame
  • specific TXFIFO/RXFIFO status when FIFO mode is enabled Even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low-energy consumption. The LPUART interface can be served by the LPDMA controller.

3.53 Serial peripheral interface (SPI1/2/3/4/5/6/7/8) inter-integrated sound interfaces

frame is configurable from 4 to 16 bits. and Tx FIFOs with DMA capability. as an input or output channel. sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability.

3.54 Serial audio interfaces (SAI1/2/3/4)

The devices embed four SAIs that are used to design many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM, or AC’97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio subblocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. Up to eight microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio subblocks can be either receiver or transmitter, and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously.

3.55 SPDIF receiver interface (SPDIFRX)

The SPDIFRX is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby® or DTS® (up to 5.1).

  • Up to 4 inputs available
  • Automatic symbol rate detection
  • Maximum symbol rate: 12.288 MHz
  • Stereo stream from 32 to 192 kHz supported
  • Supports audio IEC-60958 and IEC-61937, consumer applications
  • Parity bit management
  • Communication using DMA for audio samples
  • Communication using DMA for control and user channel information
  • Interrupt capabilities The SPDIFRX receiver provides all necessary features to detect the symbol rate, and to decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal is available, the SPDIFRX re‑samples the incoming signal, decodes the Manchester stream, and recognizes frames, sub-frames, and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate: this signal is used to compute the exact sample rate for clock drift algorithms.

3.56 Secure digital input/output MultiMediaCard interface (SDMMC1/2/3)

Three SDMMCs provide an interface between the AHB bus and SD memory cards, SDIO and e.MMC devices. SDMMC features include the following:

  • Full compliance with MultiMediaCard System Specification Version 5.1 Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit (HS200 speed limited by maximum allowed I/O speed, HS400 is not supported).
  • Full compatibility with previous versions of MultiMediaCards (backward compatibility)
  • Full compliance with SD memory card specifications version 6.0 (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI and UHS-II modes not supported)
  • Full compliance with SDIO card specification version 4.0 Card support for two different databus modes: 1-bit (default) and 4-bit (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI and UHS-II modes not supported)
  • Data transfer up to 208 Mbyte/s for the 8-bit mode (depending on the maximum allowed I/O speed)
  • Data and command output enable signals to control external bidirectional drivers
  • The SDMMC host interface embeds a dedicated DMA controller that allows high-speed transfers between the interface and the SRAM.
  • IDMA linked list support Each SDMMC is coupled with a delay block (DLYBSD) that supports an external data frequency above 100 MHz.

3.57 Controller area network (FDCAN1/2/3)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 43/234 Prerelease product(s)

The CAN subsystem consists of three FDCANs, a shared message RAM, and a clock calibration unit. All FDCANs are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B), and CAN FD protocol specification version 1.0. FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized time- triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication. A 10 Kbyte message RAM implements filters, receives FIFOs, receives buffers, transmits event FIFOs, transmits buffers (and triggers for TTCAN). This message RAM is shared between all FDCANs. The common clock calibration unit is optional. It can be used to generate a calibrated clock for FDCANs from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.

3.58 Universal serial bus Hi-Speed host (USBH)

The devices embed one USB Hi-Speed host (up to 480 Mbit/s) with one physical port. USBH supports both low, full-speed (OHCI) as well as Hi-Speed (EHCI) operations. It integrates a physical interface (PHY) which can be used for either low-speed (1.2 Mbit/s), full-speed (12 Mbit/s) ,or Hi-Speed operation (480 Mbit/s). The USBH is compliant with the USB 2.0 specification.

3.59 USB Type-C Power Delivery controller (UCPD1)

The devices embed one controller compliant with USB Type-C Rev.1.2 and USB Power Delivery Rev. 3.1 specifications. The UCPD use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

  • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
  • USB Power Delivery message transmission and reception The digital controller handles notably:
  • USB Type-C level detection with de-bounce, generating interrupts
  • byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible)
  • USB Power Delivery timing dividers (including a clock pre-scaler)
  • CRC generation/checking
  • 4b5b encode/decode
  • ordered sets (with a programmable ordered set mask at receive)
  • frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages. 3.60 Universal serial bus 3.0 dual role data (USB3DR)
  • 5 Gbit/s PHY (COMBOPHY)
  • xHCI model.
  • Dual Role Data. The USB3DR can be configured statically as a Host or Device port.
  • OTG is not supported: – Dynamic switch from Host (resp. Device) to Device (resp. Host) role is not supported. – Host Negotiation Protocol (HNP), Role Swap Protocol (RSP), Session Request Protocol (SRP), Attach Detection Protocol (ADP) are not supported.
  • USB3 SuperSpeed mode (5 Gbit/s), as well as USB2 Low-Speed/Full-Speed/Hi-Speed modes (when Host) or USB2 Full-Speed/Hi-Speed modes (when Device).
  • Descriptor caching and data pre-fetching to meet system performance.
  • Variable FIFO buffer allocation for each endpoint.
  • Simultaneously 4 Gbps IN and 4 Gbps OUT bandwidth
  • DMA engine
  • Supports Battery Charging v1.2, with the exception of the Accessory Charger Adapter mode The standards supported are:
  • Universal Serial Bus 3.0 Specification, Revision 1.0, November 12, 2008 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 44/234 Prerelease product(s)
  • Universal Serial Bus Specification, Revision 2.0, USB Implementers Forum, Inc., April 27, 2000
  • Errata for “USB Revision 2.0 April 27 2000” as of May 28, 2002, USB-IF
  • eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.1, Intel Corp., December 20, 2013
  • UTMI+ Specification, Revision 1.0, ULPI Working Group, February 25, 2004
  • Battery Charging Specification, Revision 1.2, December 7, 2010

3.61 PCI Express interface (PCIE)

The PCIE controller has the following features:

  • one lane Generation2 PCIe
  • dual-mode (RC or EP)
  • PTM
  • 256 byte maximum payload size
  • Remote device maximum read request size 1K Byte
  • Single Virtual Channel
  • Single Function
  • Legacy INTx support, MSI and GICv2m host support
  • ASPM L0s and L1, and L1.1 substate
  • AER
  • internal ATU
  • 5 Gbit/s PHY (COMBOPHY) An included PCIe reference clock generator (REFGEN) provides a 100 MHz differential clock to a PCIe link partner. This can be used to eliminate the external 100 MHz clock source that is typically found in PCIe common- clock implementations. The PCIE internal reference clock is 25 MHz (without SSC). There is also the option of an external PCIE differential reference clock 100 MHz (with SSC). 3.62 5-Gbit/s PHY controller (COMBOPHY) The COMBOPHY control a 5-Gbit/s multi-protocol PHY, that is used by the USB3DR or the PCIE (mutually exclusive). It supports data rates up to 5 Gbit/s for USB3.0, 5 Gbit/s for PCIe gen2, and 2.5 Gbit/s for PCIe gen1. The COMBOPHY includes the physical coding sublayer (PCS) blocks that perform 8-/10bit encoding/decoding, and resynchronizing RX data to the local clock domain. The COMBOPHY is single lane. The SuperSpeed lane multiplexing for USB Type-C must be managed by a switch outside the device.

3.63 Gigabit Ethernet MAC interface (ETH1/2)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). The devices embed two fully independent instances of a 10/100/1000 Ethernet MAC controller, that enable transmission and reception of data over Ethernet, in compliance with IEEE 802.3-2008. Each Ethernet MAC controller is connected to an external Ethernet PHY via a standard media independent interface. Features provided by the Ethernet controller include:

  • 10, 100, and 1000 Mbps data transfer rates
  • Full-duplex and half-duplex operations
  • Standard or Jumbo Ethernet packets
  • Two independent Rx queues and two independent Tx queues, with each queue associated to a (subset of) PCP code(s) STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 45/234 Prerelease product(s)
  • Configurable media-independent interface to external PHY: – RGMII – MII – RMII – MDIO master interface for external PHY device configuration – Internal or external reference clocks
  • Low-power support: – Energy Efficient Ethernet (EEE) compliant with IEEE 802.3az-2010; – Detection of LAN wake-up frames and “Magic Packet” frames
  • Timing and synchronization: – compliance with IEEE 1588-2008 (PTP) and IEEE 802.1AS-Rev – hardware “auxiliary timestamp trigger” for accurate sampling of the “PTP system clock” – Internal or external system time
  • Time-sensitive networking: – “Forwarding and Queuing Enhancements for Time-Sensitive Streams” compliant with IEEE 802.1Qav – “Enhancements to Scheduled Traffic” compliant with IEEE 802.1Qbv, with a gate control list depth up to 128 – “Frame Preemption” compliant with IEEE 802.1Qbu and IEEE 802.3br
  • Preamble and start-of-frame data insertion (for Tx) and deletion (for Rx)
  • Option for automatic CRC generation (for Tx), checking and stripping (for Rx)
  • Source address field insertion or replacement in transmitted packets
  • Filtering options: – Perfect match with a given SA/DA (up to 3 MAC addresses are supported) – 64-bit Hash filter match – Several multicast/broadcast rules supported – Based on IEEE 802.1q ‘VLAN tag’ field (perfect match, hash filtering) – Support for different ‘VLAN tag’ filtering for each Rx queue – Based on TCP/UDP/IP address (perfect match, inverse filtering)
  • TCP/IP offloading: – Checksum calculation and insertion in the transmit path – Checksum error detection in the receive path. – TCP segmentation offload (automatic split of a large TCP packet into smaller Ethernet frames)

3.64 Gigabit Ethernet switch (ETHSW)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details). A 3-port gigabit Ethernet switch is included. The switch supports TSN and related standards, and also includes a cut-through accelerator (called ACM) for the two external ports. Two switch ports are available externally providing RGMII and RMII interfaces. The third port is connected internally to the ETH1 controller. The switch can be completely bypassed. In this case, ETH1 is connected directly to a single external port.

3.65 Debug infrastructure

The devices offer a comprehensive set of debug and trace features to support software development and system integration.

  • Breakpoint debugging
  • Code execution tracing
  • Software instrumentation
  • JTAG debug port
  • Serial-wire debug port
  • Trigger input and output STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 46/234 Prerelease product(s)
  • Serial-wire trace port
  • Trace port
  • Arm CoreSight debug and trace components The debug can be controlled via a JTAG/serial-wire debug access port, using industry standard debugging tools. A trace port allows data to be captured for logging and analysis. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Functional overview DS14285 - Rev 2 page 47/234 Prerelease product(s)

4 Pinouts/ballouts, pin description, and alternate functions

4.1 Ballout schematics

Figure 6. STM32MP25xA/D VFBGA361 pinout

  1. The above figure shows the package top view.
  2. VDDGPU, VDDA18DSI, VDDDSI, VDDA18LVDS, and VDDLVDS are DNU on product without the related

in same ways as for a product with enabled feature. Refer to AN5489 for additional details.

Figure 7. STM32MP25xA/D VFBGA424 pinout

  1. The above figure shows the package top view.
  2. VDDGPU, VDDA18DSI, VDDDSI, VDDA18LVDS, and VDDLVDS are DNU on product without the related

in same ways as for a product with enabled feature. Refer to AN5489 for additional details.

Figure 8. STM32MP25xA/D TFBGA436 pinout

  1. The above figure shows the package top view.
  2. VDDGPU, VDDA18DSI, VDDDSI, VDDA18LVDS, and VDDLVDS are DNU on product without the related

in same ways as for a product with enabled feature. Refer to AN5489 for additional details.

Table 9. I/O power domains

  1. Does not includes analog peripherals which have one or more dedicated supplies (for example PHYs).
  2. Usually used for SD-Card using SDMMC1.
  3. Usually used for e.MMC or SD-Card using SDMMC2.
  4. Usually used for OCTOSPIM_P1.
  5. Usually used for OCTOSPIM_P2.
  6. VSW is supplied by VBAT in absence of VDD.
  7. Pins with two supplies: VSW supply for enabled TAMP_INx additional function, VDD supply for GPIO and other alternate function.

4.2 Ball description

Table 10. Legend/abbreviations used in the ballout table DNU (do not use) Represent a pin/ball that must be left unconnected (open) at application level unless otherwise noted.

  1. The related I/O structures in table below are TT_f, TT_a and TT_af.

Note: Alternate functions listed in following tables may be absent in some devices or packages (see Section 2 for details).

Table 11. STM32MP25xA/D ball definitions

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 P17 AC25 U19 DDR_A7 O DDR - - - H18 V22 P19 DDR_A8 O DDR - - - E18 T22 P18 DDR_A9 O DDR - - - G18 R23 N18 DDR_A10 O DDR - - - F18 P24 N17 DDR_A11 O DDR - - - R17 L23 K19 DDR_A12 O DDR - - - J18 K24 K18 DDR_A13 O DDR - - - K18 M24 L18 DDR_A14 O DDR - - - L18 N23 L17 DDR_A15 O DDR - - - M18 J23 J18 DDR_A16 O DDR - - - N18 H24 H18 DDR_A17 O DDR - - - P18 G23 H19 DDR_A18 O DDR - - - - L21 K17 DDR_A19 O DDR - - - E19 J21 G18 DDR_A20 O DDR - - - F19 H22 J19 DDR_A21 O DDR - - - G19 F22 H17 DDR_A22 O DDR - - - H19 E23 J17 DDR_A23 O DDR - - - H17 W21 R17 DDR_A25 O DDR - - - K19 AB24 R19 DDR_A26 O DDR - - - L19 AA23 R18 DDR_A27 O DDR - - - M19 AC23 M18 DDR_A28 O DDR - - - N19 Y22 T19 DDR_A29 O DDR - - - P19 AA21 P17 DDR_A30 O DDR - - - R19 W23 P16 DDR_A31 O DDR - - - T17 AB25 W21 DDR_DQM0 O DDR - - - C19 U26 P20 DDR_DQM1 O DDR - - - - G27 E21 DDR_DQM2 O DDR - - - DS14285 - Rev 2page 54/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 - M25 H20 DDR_DQM3 O DDR - - - V18 AA26 W20 DDR_DQS0N I/O DDR - - - B18 R25 N21 DDR_DQS1N I/O DDR - - - - F26 D22 DDR_DQS2N I/O DDR - - - - L27 H21 DDR_DQS3N I/O DDR - - - V19 AA25 V20 DDR_DQS0P I/O DDR - - - B19 T25 N20 DDR_DQS1P I/O DDR - - - - F27 D21 DDR_DQS2P I/O DDR - - - - L26 H22 DDR_DQS3P I/O DDR - - - V17 AB27 Y22 DDR_DQ2 I/O DDR - - - U17 AC27 AA22 DDR_DQ3 I/O DDR - - - W17 AC26 Y21 DDR_DQ1 I/O DDR - - - W18 AB26 W22 DDR_DQ0 I/O DDR - - - U18 Y25 U20 DDR_DQ7 I/O DDR - - - U19 W26 U21 DDR_DQ6 I/O DDR - - - T19 W25 T21 DDR_DQ4 I/O DDR - - - T18 W27 T20 DDR_DQ5 I/O DDR - - - D19 V26 T22 DDR_DQ12 I/O DDR - - - C18 U25 R22 DDR_DQ15 I/O DDR - - - D17 V25 R21 DDR_DQ14 I/O DDR - - - D18 V27 R20 DDR_DQ13 I/O DDR - - - A18 R26 M22 DDR_DQ9 I/O DDR - - - C17 R27 M21 DDR_DQ8 I/O DDR - - - A17 P26 L22 DDR_DQ11 I/O DDR - - - B17 P27 L21 DDR_DQ10 I/O DDR - - - - J25 F20 DDR_DQ20 I/O DDR - - - - H25 F19 DDR_DQ21 I/O DDR - - - DS14285 - Rev 2page 55/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 - G25 E20 DDR_DQ23 I/O DDR - - - - G26 E19 DDR_DQ22 I/O DDR - - - - E25 B22 DDR_DQ19 I/O DDR - - - - F25 D20 DDR_DQ16 I/O DDR - - - - F24 C21 DDR_DQ18 I/O DDR - - - - E26 C22 DDR_DQ17 I/O DDR - - - - P25 L19 DDR_DQ31 I/O DDR - - - - N26 K20 DDR_DQ30 I/O DDR - - - - L25 J21 DDR_DQ28 I/O DDR - - - - N25 J20 DDR_DQ29 I/O DDR - - - - K25 G22 DDR_DQ25 I/O DDR - - - - K26 G21 DDR_DQ26 I/O DDR - - - - K27 G20 DDR_DQ27 I/O DDR - - - - J26 G19 DDR_DQ24 I/O DDR - - - K17 G21 L20 DDR_VREF A A - - - E17 E21 F18 DDR_RESETN O DDR - - - G16 K22 K16 DDR_ZQ A A - - - A4 C8 B8 DSI_CKN A A - - - B4 C7 A8 DSI_CKP A A - - - A5 C9 B9 DSI_D0N A A - - - B5 B9 C9 DSI_D0P A A - - - A6 A10 E9 DSI_D1N A A - - - B6 B10 D9 DSI_D1P A A - - - B3 A7 D8 DSI_D2N A A - - - A3 B7 C8 DSI_D2P A A - - - B2 B6 B7 DSI_D3N A A - - - A2 A6 A7 DSI_D3P A A - - - DS14285 - Rev 2page 56/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 C4 D6 E8 DSI_REXT A A - - - W4 AA5 AA1 JTCK-SWCLK I TTD (1) - - W3 AE3 AB2 JTDI I TTU (1) - - V1 AC2 W1 JTDO-TRACESWO O TTU (1) - - W2 AE2 Y1 JTMS-SWDIO I/O TTU (1) - - F1 G3 D3 LVDS1_D0N A A (2) - - F2 G2 D4 LVDS1_D0P A A (2) - - F3 H4 D1 LVDS1_D1N A A (2) - - F4 H3 D2 LVDS1_D1P A A (2) - - G3 J2 E4 LVDS1_D2N A A (2) - - G4 J1 E3 LVDS1_D2P A A (2) - - J2 L3 F3 LVDS1_D3N A A (2) - - J3 L2 F2 LVDS1_D3P A A (2) - - H3 K2 F5 LVDS1_D4N A A (2) - - H4 K1 F4 LVDS1_D4P A A (2) - - - B2 B4 LVDS2_D0N A A (2) - - - B1 A4 LVDS2_D0P A A (2) - - - C3 A3 LVDS2_D1N A A (2) - - - C2 A2 LVDS2_D1P A A (2) - - - D3 B3 LVDS2_D2N A A (2) - - - E3 C3 LVDS2_D2P A A (2) - - - E2 C2 LVDS2_D3N A A (2) - - - E1 C1 LVDS2_D3P A A (2) - - - F2 B2 LVDS2_D4N A A (2) - - - F1 B1 LVDS2_D4P A A (2) - - V2 AF3 AA2 NJTRST I TTU (1) - - DS14285 - Rev 2page 57/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 N2 AE1 U3 NRST I/O RST (1) - - T1 W3 T3 NRSTC1MS O TT (3) - - P15 AF5 Y2 PA0 I/O TT_a (1) LPTIM1_CH2, SPI5_RDY, UART8_CTS, SAI2_MCLK_B, UART5_TX(boot), USART3_TX, TIM3_ETR, TIM5_CH2, ETH2_MII_RXD2, FMC_NL, DCMI_D9/PSSI_D9/DCMIPP_D9, EVENTOUT WKUP1 N15 AC19 V15 PA1 I/O TT_af (1) SPI6_MISO, SAI3_SD_A, USART1_RTS/USART1_DE, USART6_CK, TIM4_CH2, I2C4_SDA, I2C6_SDA, LCD_R3, DCMI_D5/PSSI_D5/DCMIPP_D5, ETH3_PHY_INTN, EVENTOUT N12 AF17 W13 PA2 I/O TT_af (1) LPTIM2_IN1, SPI7_MISO, MDF1_SDI7, USART1_RX, I3C1_SDA, I2C1_SDA, LCD_B0, DCMI_D3/PSSI_D3/ DCMIPP_D3, ETH3_RGMII_RX_CTL/ETH3_RMII_CRS_DV, EVENTOUT R12 AD18 T14 PA3 I/O TT_af (1) LPTIM2_ETR, SPI7_MOSI, MDF1_CKI7, USART1_TX, I3C1_SCL, I2C7_SMBA, I2C1_SCL, LCD_B1, DCMI_D2/ PSSI_D2/DCMIPP_D2, ETH3_RGMII_TX_CTL/ ETH3_RMII_TX_EN, EVENTOUT P12 AG17 Y15 PA4 I/O TT_a (1) USART2_TX(boot), FDCAN2_TX, TIM2_CH1, LCD_R1, ETH1_PTP_AUX_TS, ETH3_PPS_OUT, EVENTOUT - J12 AE17 Y13 PA5 I/O TT (1) SPI4_MOSI, SAI2_MCLK_B, SAI2_SD_B, USART2_RTS/ USART2_DE, FDCAN2_RX, TIM2_CH4, LCD_G0, FMC_A0, DCMI_D13/PSSI_D13/DCMIPP_D13, ETH3_RGMII_RX_CLK/ ETH3_RMII_REF_CLK, EVENTOUT M14 AF18 V14 PA6 I/O TT (1) SPI4_SCK, SAI2_FS_B, MDF1_SDI6, USART2_CK, TIM13_CH1, TIM2_ETR, LCD_G4, FMC_NE1, DCMI_D12/ PSSI_D12/DCMIPP_D12, ETH3_RGMII_TXD0/ ETH3_RMII_TXD0, EVENTOUT K15 AE18 Y14 PA7 I/O TT (1) AUDIOCLK, SPI6_RDY, PCIE_CLKREQN, MDF1_CCK0, USART1_CTS/USART1_NSS, TIM4_ETR, I2C2_SMBA, I2C6_SMBA, LCD_B5, I2C3_SMBA, I2C4_SMBA, DCMI_D6/ PSSI_D6/DCMIPP_D6, ETH3_RGMII_TXD1/ ETH3_RMII_TXD1, EVENTOUT K9 AA17 W15 PA8 I/O TT_f (1) LPTIM2_CH2, SPI7_NSS, SAI1_FS_B, USART1_CK, USART2_RX(boot), I2C5_SCL, LCD_B2, DCMI_D4/PSSI_D4/ DCMIPP_D4, EVENTOUT DS14285 - Rev 2page 58/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 K12 AF15 T12 PA9 I/O TT (1) SPI4_NSS, SAI2_SCK_B, USART2_CTS/USART2_NSS, LPTIM5_ETR, TIM2_CH3, ETH1_MDC, LCD_G7, PSSI_D14/ DCMIPP_D14, ETH3_RGMII_RXD0/ETH3_RMII_RXD0, EVENTOUT M15 AE15 U13 PA10 I/O TT (1) SPI4_MISO, SAI2_SD_B, USART2_RX, LPTIM5_IN1, TIM2_CH2, ETH1_MDIO, LCD_R6, PSSI_D15/DCMIPP_D15, ETH3_RGMII_RXD1/ETH3_RMII_RXD1, EVENTOUT R9 AD12 W12 PA11 I/O TT (1) SPI8_SCK, LPTIM2_CH1, SAI4_SD_B, MDF1_SDI4, ETH1_MII_RX_DV/ETH1_RGMII_RX_CTL/ ETH1_RMII_CRS_DV, EVENTOUT R8 AC13 U12 PA12 I/O TT_f (1) SPI6_MOSI, SAI3_FS_A, TIM4_CH1, I2C4_SCL, I2C6_SCL, ETH1_PHY_INTN, EVENTOUT - W9 AD14 Y12 PA13 I/O TT (1) SPI8_RDY, I2S3_MCK, LPTIM2_ETR, MDF1_CKI3, USART2_CTS/USART2_NSS, I2C7_SMBA, ETH1_MII_TX_EN/ ETH1_RGMII_TX_CTL/ETH1_RMII_TX_EN, EVENTOUT T8 AB12 U10 PA14 I/O TT (1) SPI8_NSS, LPTIM2_CH2, SAI4_FS_B, MDF1_CCK1, ETH1_MII_RX_CLK/ETH1_RGMII_RX_CLK/ ETH1_RMII_REF_CLK, EVENTOUT T10 AE13 T10 PA15 I/O TT_f (1) SPI3_MISO/I2S3_SDI, USART2_RX, I2C7_SDA, ETH1_MII_TXD0/ETH1_RGMII_TXD0/ETH1_RMII_TXD0, EVENTOUT B8 B13 C11 PB0 I/O TT (4) SPI2_SCK/I2S2_CK, USART1_CK, TIM16_CH1, TIM20_CH4N, OCTOSPIM_P2_IO0(boot), EVENTOUT - D9 C12 D11 PB1 I/O TT (4) SPI3_NSS/I2S3_WS, TIM16_CH1N, TIM20_CH3N, OCTOSPIM_P2_IO1(boot), FMC_NCE4, EVENTOUT - E9 A14 C10 PB2 I/O TT (4) SPI2_MOSI/I2S2_SDO, MDF1_CKI3, TIM17_BKIN, TIM16_BKIN, TIM20_CH2N, OCTOSPIM_P2_IO2(boot), EVENTOUT A9 B14 E10 PB3 I/O TT (4) SPI2_NSS/I2S2_WS, MDF1_SDI3, TIM20_CH3, OCTOSPIM_P2_IO3(boot), FMC_NCE3, EVENTOUT - C9 B15 D10 PB4 I/O TT_f (4) SPI2_RDY, UART4_CTS, SAI4_FS_B, MDF1_SDI4, TIM14_CH1, TIM20_CH2, I2C2_SDA, OCTOSPIM_P2_IO4(boot), I3C2_SDA, EVENTOUT B9 C14 B11 PB5 I/O TT_f (4) I2S2_MCK, UART4_RTS/UART4_DE, SAI4_SD_B, MDF1_CKI4, TIM20_CH1, I2C2_SCL, OCTOSPIM_P2_IO5(boot), FMC_AD8/FMC_D8(boot), I3C2_SCL, SDMMC3_D123DIR, EVENTOUT DS14285 - Rev 2page 59/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 C8 C13 C12 PB6 I/O TT (4) SPI2_MISO/I2S2_SDI, UART4_RX, SAI4_SCK_B, TIM20_CH1N, OCTOSPIM_P2_IO6(boot), FMC_AD9/ FMC_D9(boot), SDMMC3_D0DIR, EVENTOUT D7 C11 D12 PB7 I/O TT (4) SPI3_SCK/I2S3_CK, UART4_TX, SAI4_MCLK_B, TIM20_ETR, TIM12_CH1, OCTOSPIM_P2_IO7(boot), FMC_AD10/ FMC_D10(boot), SDMMC3_CDIR, EVENTOUT A7 D8 G11 PB8 I/O TT (4) SPI3_MOSI/I2S3_SDO, PCIE_CLKREQN, USART1_TX, TIM17_CH1, TIM20_CH4, OCTOSPIM_P2_NCS1(boot), FMC_AD12/FMC_D12(boot), EVENTOUT A8 F10 A12 PB9 I/O TT (4) SPI3_RDY, USART1_RTS/USART1_DE, FDCAN1_TX, TIM20_BKIN, TIM10_CH1, OCTOSPIM_P2_DQS(boot), OCTOSPIM_P2_NCS2, FMC_AD13/FMC_D13(boot), EVENTOUT E12 B11 A11 PB10 I/O TT (4) SPI3_MISO/I2S3_SDI, USART1_RX, TIM17_CH1N, OCTOSPIM_P2_CLK(boot), FMC_AD15/FMC_D15(boot), EVENTOUT B7 A11 B12 PB11 I/O TT (4) I2S3_MCK, USART1_CTS/USART1_NSS, FDCAN1_RX, TIM20_BKIN2, TIM12_CH2, OCTOSPIM_P2_NCLK(boot), OCTOSPIM_P2_NCS2, FMC_AD14/FMC_D14(boot), OCTOSPIM_P1_NCS2, EVENTOUT E14 C26 B20 PB12 I/O TT_a (1) UART8_CTS, TIM13_CH1, DSI_TE, SDMMC3_D2, FMC_NWAIT, DCMI_D12/PSSI_D12/DCMIPP_D12, EVENTOUT G15 A26 D19 PB13 I/O TT_a (1) SPI7_SCK, SAI1_SD_B, UART8_RX, SDMMC3_CK, FMC_AD5/FMC_D5(boot), FMC_AD0/FMC_D0, EVENTOUT - H15 C27 C20 PB14 I/O TT (1) SPI2_SCK/I2S2_CK, MDF1_CKI7, UART9_RX(boot), TIM4_CH2, SDMMC3_D0, FMC_AD7/FMC_D7(boot), FMC_AD2/FMC_D2, EVENTOUT J15 AE6 AB4 PB15 I/O TT_a (1) LPTIM1_IN2, SPI5_SCK, UART8_RTS/UART8_DE, SAI2_SD_B, UART5_RX(boot), TIM3_CH2, TIM5_CH1, ETH1_PPS_OUT, FMC_A18, LCD_R4, DCMI_D8/PSSI_D8/ DCMIPP_D8, EVENTOUT ADC1_INP15, ADC3_INP5 V13 AE26 AA18 PCIE_CLKINN A - - - - U13 AE25 Y18 PCIE_CLKINP A - - - - V14 AG26 AB21 PCIE_CLKOUTN A - - - - U14 AF26 AA21 PCIE_CLKOUTP A - - - - DS14285 - Rev 2page 60/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 V9 AB14 AA12 PC0 I/O TT (1) LPTIM1_CH1, SPI6_SCK, SAI3_MCLK_B, USART6_TX, DCMI_D0/PSSI_D0/DCMIPP_D0, ETH2_MII_RX_CLK/ ETH2_RMII_REF_CLK, ETH1_MII_TX_CLK, ETH1_RGMII_GTX_CLK, LCD_G7, EVENTOUT V10 AG14 V11 PC1 I/O TT_f (1) SPI3_MOSI/I2S3_SDO, USART2_TX, I2C7_SCL, ETH1_MII_TXD1/ETH1_RGMII_TXD1/ETH1_RMII_TXD1, EVENTOUT T9 AE12 Y11 PC2 I/O TT (1) SPI8_MOSI, LPTIM2_IN1, SAI4_MCLK_B, MDF1_SDI3, USART2_RTS/USART2_DE, ETH1_MII_RXD1/ ETH1_RGMII_RXD1/ETH1_RMII_RXD1, EVENTOUT U4 AA9 W9 PC3 I/O TT_a (5) LPTIM1_IN2, SPI3_NSS/I2S3_WS, SPI6_RDY, USART6_RTS/ USART6_DE, FDCAN2_TX, ETH2_MII_RX_DV/ ETH2_RGMII_RX_CTL/ETH2_RMII_CRS_DV, ETH1_MII_RX_ER, LCD_G6, DCMI_D3/PSSI_D3/DCMIPP_D3, EVENTOUT ADC1_INP12, ADC1_INN10, ADC2_INP12, ADC2_INN10, ADC3_INP12, ADC3_INN10, TAMP_IN3 V3 AC9 V9 PC4 I/O TT (5) SPI6_MISO, SAI3_FS_B, ETH2_MII_TX_EN/ ETH2_RGMII_TX_CTL/ETH2_RMII_TX_EN, ETH1_RGMII_CLK125, LCD_R0, EVENTOUT TAMP_IN1 T7 AD10 U9 PC5 I/O TT_af (5) SPDIFRX1_IN1, MDF1_SDI1, TIM8_CH1N, I2C4_SDA, ETH2_MDIO, ETH1_MII_COL, FMC_A25, ETH1_PPS_OUT, LCD_DE, EVENTOUT ADC1_INP10, ADC2_INP10, ADC3_INP10, TAMP_IN6 R7 AB10 AA10 PC6 I/O TT_af (1) RTC_REFIN, SPDIFRX1_IN0, MDF1_CKI1, TIM8_CH1, I2C4_SCL, ETH2_MDC, ETH1_MII_CRS, FMC_A24, ETH1_PHY_INTN, LCD_CLK, EVENTOUT ADC1_INP9, ADC1_INN5, ADC2_INP9, ADC2_INN5 W5 AF9 Y8 PC7 I/O TT_a (1) SPI6_MOSI, SAI3_SD_B, TIM8_CH2N, ETH2_MII_TXD0/ ETH2_RGMII_TXD0/ETH2_RMII_TXD0, ETH1_MII_TXD2, LCD_B4, DCMI_D1/PSSI_D1/DCMIPP_D1, EVENTOUT ADC3_INP9, ADC3_INN5 U6 AG9 V8 PC8 I/O TT_a (1) LPTIM1_ETR, SPI6_NSS, SAI3_SCK_B, USART6_CTS/ USART6_NSS, TIM8_CH2, ETH2_MII_TXD1/ ETH2_RGMII_TXD1/ETH2_RMII_TXD1, ETH1_MII_TXD3, LCD_B3, DCMI_D2/PSSI_D2/DCMIPP_D2, EVENTOUT V6 AE9 U8 PC9 I/O TT_a (1) MCO1, SPI3_MISO/I2S3_SDI, SAI2_SCK_A, TIM13_CH1, TIM8_CH4N, USBH_HS_OVRCUR, ETH2_MII_TXD2/ ETH2_RGMII_TXD2, USB3DR_OVRCUR, FMC_A22, LCD_G2, DCMI_D7/PSSI_D7/DCMIPP_D7, EVENTOUT ADC1_INP8, ADC1_INN4, ADC2_INP8, ADC2_INN4 DS14285 - Rev 2page 61/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 W6 AG10 T8 PC10 I/O TT_a (1) SPI3_MOSI/I2S3_SDO, LPTIM4_ETR, TIM8_CH4, USBH_HS_VBUSEN, ETH2_MII_TXD3/ETH2_RGMII_TXD3, USB3DR_VBUSEN, FMC_A23, LCD_G3, DCMI_D6/PSSI_D6/ DCMIPP_D6, EVENTOUT ADC1_INP5, ADC2_INP5 V5 AD8 AB7 PC11 I/O TT_a (1) LPTIM1_CH1, SPI5_NSS, SAI2_MCLK_A, UART5_RTS/ UART5_DE, USART3_RTS/USART3_DE, TIM3_CH1, TIM5_ETR, ETH2_MII_RXD3/ETH2_RGMII_RXD3, FMC_NBL1, LCD_R2, DCMI_D10/PSSI_D10/DCMIPP_D10, EVENTOUT ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3, ADC3_INP7, ADC3_INN3 V4 AE7 Y7 PC12 I/O TT_af (1) LPTIM1_CH2, I3C3_SCL, MDF1_CKI2, TIM8_CH3, I2C3_SCL, ETH2_MII_RXD1/ETH2_RGMII_RXD1/ETH2_RMII_RXD1, ETH1_MII_RXD3, LCD_G1, DCMI_D5/PSSI_D5/DCMIPP_D5, EVENTOUT ADC1_INP17 P4 W7 P6 PC13 I/O TT (6) EVENTOUT RTC_OUT1/ RTC_LSCO/RTC_TS, TAMP_OUT1 M2 AA2 R1 OSC32_IN I A (7) - OSC32_IN M1 AA1 R2 OSC32_OUT O A (8) - OSC32_OUT N1 W2 T7 PDR_ON I - (9) - - C11 B17 D14 PD0 I/O TT (10) TRACECLK, HDP0, SPI7_RDY, SAI1_D2, SAI4_FS_A, UART7_RX, TIM15_CH2, SDVSEL1, OCTOSPIM_P1_CLK(boot), DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK, EVENTOUT F9 A19 E15 PD1 I/O TT (10) HDP1, SPI1_MISO/I2S1_SDI, SAI1_CK2, SAI4_SD_A, UART7_RTS/UART7_DE, TIM15_CH1, TIM1_BKIN, FDCAN3_RX, OCTOSPIM_P1_NCLK(boot), OCTOSPIM_P1_NCS2, OCTOSPIM_P2_NCS2, DCMI_HSYNC/PSSI_DE/DCMIPP_HSYNC, EVENTOUT A10 D12 E14 PD2 I/O TT (10) HDP2, SPI1_NSS/I2S1_WS, SAI1_CK1, SAI4_SCK_A, UART7_CTS, TIM15_BKIN, TIM1_ETR, FDCAN3_TX, OCTOSPIM_P1_DQS(boot), OCTOSPIM_P1_NCS2, DCMI_VSYNC/PSSI_RDY/DCMIPP_VSYNC, EVENTOUT D8 G13 C15 PD3 I/O TT (10) SAI1_MCLK_A, SPI2_SCK/I2S2_CK, SAI1_D1, SAI4_MCLK_A, UART7_TX, TIM15_CH1N, TIM1_BKIN2, SDVSEL2, OCTOSPIM_P1_NCS1(boot), PSSI_D15/DCMIPP_D15, EVENTOUT DS14285 - Rev 2page 62/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 C12 C18 C14 PD4 I/O TT (10) TRACED0, SPI4_MISO, HDP3, SAI1_D3, SAI1_SD_B, TIM1_CH4N, TIM4_CH1, OCTOSPIM_P1_IO0(boot), PSSI_D14/DCMIPP_D14, EVENTOUT B12 B18 B15 PD5 I/O TT (10) TRACED1, SPI4_NSS, HDP4, SAI1_D4, SAI1_FS_B, TIM1_CH3N, TIM4_CH2, OCTOSPIM_P1_IO1(boot), DCMI_D13/PSSI_D13/DCMIPP_D13, EVENTOUT A12 A18 A15 PD6 I/O TT (10) TRACED2, SPI4_MOSI, HDP5, SAI1_SCK_B, MDF1_SDI2, TIM1_CH2N, TIM4_CH3, OCTOSPIM_P1_IO2(boot), DCMI_D12/PSSI_D12/DCMIPP_D12, EVENTOUT D12 D20 D15 PD7 I/O TT (10) TRACED3, SPI4_SCK, SPI1_RDY, SAI1_MCLK_B, MDF1_CKI2, TIM1_CH1N, TIM4_CH4, OCTOSPIM_P1_IO3(boot), DCMI_D11/PSSI_D11/ DCMIPP_D11, EVENTOUT E11 C16 C13 PD8 I/O TT (10) TRACED4, SPI4_RDY, I2S1_MCK, SAI1_FS_A, UART4_CTS, MDF1_SDI1, TIM1_CH4, TIM4_ETR, OCTOSPIM_P1_IO4(boot), SDMMC1_D7, SDMMC1_D123DIR, DCMI_D10/PSSI_D10/DCMIPP_D10, EVENTOUT C10 C15 B13 PD9 I/O TT (10) TRACED5, HDP6, SPI1_MOSI/I2S1_SDO, SAI1_SD_A, UART4_RTS/UART4_DE, MDF1_CKI1, TIM1_CH3, OCTOSPIM_P1_IO5(boot), SDMMC1_D6, SDMMC1_D0DIR, DCMI_D9/PSSI_D9/DCMIPP_D9, EVENTOUT D11 C17 D13 PD10 I/O TT_f (10) TRACED6, HDP7, SAI1_SCK_A, UART4_RX, MDF1_SDI0, I2C4_SDA, TIM1_CH2, TIM14_CH1, OCTOSPIM_P1_IO6(boot), SDMMC1_D5, SDMMC1_CDIR, DCMI_D8/PSSI_D8/DCMIPP_D8, EVENTOUT B10 A15 E13 PD11 I/O TT_f (10) TRACED7, SPI1_SCK/I2S1_CK, SAI1_MCLK_A, UART4_TX, MDF1_CKI0, I2C4_SCL, TIM1_CH1, SDVSEL1, OCTOSPIM_P1_IO7(boot), SDMMC1_D4, SDMMC1_CKIN, DCMI_D7/PSSI_D7/DCMIPP_D7, EVENTOUT H14 B26 A21 PD12 I/O TT_a (1) SPI7_MISO, SPI2_MISO/I2S2_SDI, SPDIFRX1_IN2, UART8_RTS/UART8_DE, TIM4_ETR, SDMMC3_CMD, FMC_AD6/FMC_D6(boot), FMC_AD1/FMC_D1, EVENTOUT G9 D25 B21 PD13 I/O TT_a (1) SPI2_NSS/I2S2_WS, MDF1_SDI7, UART9_TX(boot), TIM4_CH4, SDMMC3_D1, FMC_AD11/FMC_D11(boot), FMC_NWE, EVENTOUT A13 E19 G15 PD14 I/O TT_af (1) I2S1_MCK, FDCAN1_RX, TIM11_CH1, I2C7_SDA, FMC_AD4/ FMC_D4(boot), SDMMC3_D3, DCMI_D1/PSSI_D1/ DCMIPP_D1, EVENTOUT DS14285 - Rev 2page 63/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 A11 E15 F16 PD15 I/O TT_af (1) SPI1_RDY, DSI_TE, I2C5_SDA, FDCAN1_TX, TIM1_BKIN2, TIM5_ETR, I2C7_SCL, FMC_AD3/FMC_D3(boot), SDMMC3_CKIN, DCMI_D0/PSSI_D0/DCMIPP_D0, EVENTOUT B13 B19 A16 PE0 I/O TT (11) TRACED2, LPTIM2_CH1, SPI1_SCK/I2S1_CK, SPI3_RDY, USART3_CK, SDMMC1_D2, EVENTOUT - C13 C19 B16 PE1 I/O TT (11) TRACED3, LPTIM2_CH2, I2S1_MCK, I2S3_MCK, USART3_RX, SDMMC1_D3, EVENTOUT - A14 C20 C16 PE2 I/O TT (11) LPTIM2_ETR, SPI1_MISO/I2S1_SDI, SPI3_MOSI/I2S3_SDO, SAI1_SCK_B, TIM10_CH1, SDMMC1_CMD(boot), EVENTOUT - A15 C21 D16 PE3 I/O TT (11) TRACECLK, SPI1_RDY, SPI3_SCK/I2S3_CK, SAI1_MCLK_B, USART3_TX, TIM11_CH1, SDMMC1_CK(boot), EVENTOUT - B14 B21 B17 PE4 I/O TT (11) TRACED0, LPTIM2_IN1, SPI1_MOSI/I2S1_SDO, SPI3_MISO/ I2S3_SDI, SAI1_SD_B, USART3_CTS/USART3_NSS, FDCAN1_TX, SDMMC1_D0(boot), EVENTOUT C14 C22 C17 PE5 I/O TT (11) TRACED1, LPTIM2_IN2, SPI1_NSS/I2S1_WS, SPI3_NSS/ I2S3_WS, SAI1_FS_B, USART3_RTS/USART3_DE, FDCAN1_RX, SDMMC1_D1, EVENTOUT F14 A22 E16 PE6 I/O TT (12) SPI4_RDY, SPDIFRX1_IN2, USART1_TX, TIM1_ETR, FMC_AD1/FMC_D1(boot), SDMMC2_D6, SDMMC2_D0DIR, EVENTOUT C15 B22 D17 PE7 I/O TT (12) SAI4_D4, SPDIFRX1_IN3, USART1_RX, TIM1_CH4N, TIM14_CH1, FMC_AD2/FMC_D2(boot), SDMMC2_D7, SDMMC2_D123DIR, EVENTOUT B15 C23 C18 PE8 I/O TT (12) SPI4_MOSI, SAI4_CK1, SAI4_MCLK_A, MDF1_CKI0, TIM1_CH1, FMC_A17/FMC_ALE(boot), SDMMC2_D2, EVENTOUT F15 A23 D18 PE9 I/O TT (12) SPI4_MISO, SAI4_D2, SAI4_FS_A, USART1_CK, TIM1_CH4, FMC_AD0/FMC_D0(boot), SDMMC2_D5, SDMMC2_CDIR, EVENTOUT D15 D22 A19 PE10 I/O TT (12) SPI4_SCK, SAI4_D1, SAI4_SD_A, USART1_CTS/ USART1_NSS, TIM1_CH3, FMC_NE3, FMC_NCE2, SDMMC2_D4, SDMMC2_CKIN, EVENTOUT B16 B23 E17 PE11 I/O TT (12) SPI7_SCK, SAI4_D3, SAI1_FS_A, TIM15_CH2, TIM1_CH3N, FMC_A16/FMC_CLE(boot), SDMMC2_D1, EVENTOUT - DS14285 - Rev 2page 64/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 C16 C25 C19 PE12 I/O TT (12) SPI4_NSS, SAI4_CK2, SAI4_SCK_A, MDF1_SDI0, USART1_RTS/USART1_DE, TIM1_CH2, FMC_NE2, FMC_NCE1(boot), SDMMC2_D3, EVENTOUT A16 C24 B19 PE13 I/O TT (12) SPI7_MISO, SAI1_SD_A, TIM15_CH1, TIM1_CH2N, FMC_RNB(boot), SDMMC2_D0(boot), EVENTOUT - G14 B25 A20 PE14 I/O TT (12) SPI7_NSS, SAI1_MCLK_A, MDF1_CKI6, TIM15_BKIN, TIM1_BKIN, FMC_NWE(boot), SDMMC2_CK(boot), EVENTOUT D14 D24 F17 PE15 I/O TT (12) SPI7_MOSI, SAI1_SCK_A, MDF1_SDI6, TIM15_CH1N, TIM1_CH1N, FMC_NOE(boot), SDMMC2_CMD(boot), EVENTOUT N9 AA15 V12 PF0 I/O TT_af (1) SPI3_SCK/I2S3_CK, FDCAN2_RX, TIM12_CH2, I2C2_SDA, ETH1_MDC, ETH2_MII_CRS, I3C2_SDA, EVENTOUT ADC1_INP11, ADC2_INP11, ADC3_INP11 U8 AE11 W11 PF1 I/O TT (1) SPI8_MISO, LPTIM2_IN2, SAI4_SCK_B, MDF1_CKI4, USART2_CK, ETH1_MII_RXD0/ETH1_RGMII_RXD0/ ETH1_RMII_RXD0, EVENTOUT P9 AC15 V10 PF2 I/O TT_af (1) SPI3_RDY, I2C4_SMBA, TIM12_CH1, I2C2_SCL, ETH1_MDIO, ETH2_MII_COL, FMC_NE4, I3C2_SCL, EVENTOUT ADC1_INP13, ADC1_INN11, ADC2_INP13, ADC2_INN11, ADC3_INP13, ADC3_INN11 W10 AF11 W10 PF3 I/O TT_a (1) UART8_RX(boot), SAI2_SCK_B, MDF1_CCK0, TIM3_CH4, TIM8_BKIN2, ETH1_CLK, ETH2_PPS_OUT, FMC_A20, LCD_R6, DCMI_HSYNC/PSSI_DE/DCMIPP_HSYNC, EVENTOUT ADC1_INP16, ADC1_INN15 W7 AF10 Y10 PF4 I/O TT (1) RTC_OUT2, SPI6_NSS, SAI3_SCK_A, USART6_RX(boot), TIM4_CH4, ETH1_MDC, ETH2_CLK, ETH2_PPS_OUT, ETH1_PPS_OUT, LCD_B7, EVENTOUT P7 AA11 Y9 PF5 I/O TT (1) SPI6_SCK, SAI3_MCLK_A, USART6_TX(boot), TIM4_CH3, ETH1_MDIO, ETH1_CLK, ETH2_PHY_INTN, ETH1_PHY_INTN, LCD_B6, EVENTOUT U5 AC7 AB8 PF6 I/O TT (5) RTC_OUT2, SAI3_MCLK_B, USART6_CK, TIM12_CH1, I2C3_SMBA, ETH2_MII_RX_CLK/ETH2_RGMII_RX_CLK/ ETH2_RMII_REF_CLK, LCD_B0, EVENTOUT TAMP_IN5 DS14285 - Rev 2page 65/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 V7 AB8 T9 PF7 I/O TT (5) SPDIFRX1_IN1, SPI6_SCK, SAI3_SD_A, TIM2_ETR, ETH2_RGMII_GTX_CLK, ETH2_MII_TX_CLK, LCD_R1, EVENTOUT TAMP_IN2 U7 AE10 AA8 PF8 I/O TT (1) RTC_REFIN, SAI3_SCK_B, USART3_RX, TIM12_CH2, ETH1_CLK, ETH2_RGMII_CLK125, ETH2_MII_RX_ER, ETH2_MII_RX_DV/ETH2_RMII_CRS_DV, LCD_G0, EVENTOUT T6 AE8 AA7 PF9 I/O TT (1) SAI3_SD_B, SAI2_SD_A, MDF1_SDI5, UART8_RTS/ UART8_DE, TIM2_CH2, ETH2_MII_RXD2/ ETH2_RGMII_RXD2, ETH2_MDIO, EVENTOUT L9 AE5 AA6 PF10 I/O TT_a (1) MCO2, SPI3_RDY, SAI2_MCLK_A, MDF1_CKI6, UART8_TX, TIM2_CH3, ETH2_MII_TXD2, EVENTOUT ADC3_INP2 T4 AE4 Y6 PF11 I/O TT_a (1) MCO1, SPDIFRX1_IN0, SPI6_RDY, SAI2_SCK_A, MDF1_SDI6, UART8_RX, TIM2_CH4, ETH2_MII_TXD3, EVENTOUT ADC3_INP6, ADC3_INN2 L7 P4 K3 PF12 I/O TT (1) TRACECLK, SPI5_MISO, SPI1_MISO/I2S1_SDI, UART9_RTS/ UART9_DE, TIM5_CH1, LCD_CLK, DCMI_D0/PSSI_D0/ DCMIPP_D0, EVENTOUT H2 P2 L4 PF13 I/O TT (1) TRACED0, HDP0, AUDIOCLK, USART6_TX, SPI2_NSS/ I2S2_WS, MDF1_CKI7, USART3_CTS/USART3_NSS, FDCAN3_TX, TIM3_CH3, LCD_R2, EVENTOUT G7 P3 H1 PF14 I/O TT (1) TRACED1, HDP1, USART6_RX, MDF1_SDI7, USART3_RTS/ USART3_DE, FDCAN3_RX, TIM3_CH4, LCD_R3, EVENTOUT - G5 R2 L7 PF15 I/O TT (1) TRACED2, HDP2, SPI2_RDY, USART6_CTS/USART6_NSS, SPI2_SCK/I2S2_CK, USART3_CK, TIM2_CH2, TIM3_ETR, I2C6_SMBA, LCD_R4, EVENTOUT T5 AF7 W7 PG0 I/O TT_af (1) LPTIM1_IN1, I3C3_SDA, MDF1_SDI2, TIM8_CH3N, I2C3_SDA, ETH2_MII_RXD0/ETH2_RGMII_RXD0/ ETH2_RMII_RXD0, ETH1_MII_RXD2, LCD_G5, DCMI_D4/ PSSI_D4/DCMIPP_D4, EVENTOUT ADC1_INP18, ADC1_INN17 R4 AD4 W6 PG1 I/O TT_af (5) LPTIM1_IN1, I2S3_MCK, I3C3_SCL, SAI2_SD_A, UART5_CTS, USART3_CTS/USART3_NSS, TIM5_CH4, I2C3_SCL, ETH2_MII_RX_ER, ETH2_MII_RXD3, FMC_NBL0, LCD_VSYNC, DCMI_D11/PSSI_D11/DCMIPP_D11, EVENTOUT WKUP3, ADC1_INP6, ADC1_INN2, ADC2_INP6, ADC2_INN2, TAMP_IN4 DS14285 - Rev 2page 66/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 M7 AG5 Y4 PG2 I/O TT_af (1) RTC_REFIN, I2S3_MCK, I3C3_SDA, SAI2_FS_A, USART3_CK, TIM5_CH3, I2C3_SDA, ETH2_MII_TX_CLK, ETH2_RGMII_CLK125, FMC_CLK, LCD_HSYNC, EVENTOUT WKUP5, ADC1_INP2, ADC2_INP2 H12 AA7 W4 PG3 I/O TT_a (5) LPTIM1_ETR, SPI5_MOSI, UART8_TX(boot), SAI2_FS_B, TIM3_CH3, TIM8_ETR, ETH2_CLK, ETH2_PHY_INTN, FMC_A19, LCD_R5, DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK, EVENTOUT WKUP6, ADC1_INP3, ADC2_INP3, ADC3_INP3, TAMP_IN7 N7 AD6 AA4 PG4 I/O TT_a (1) SPI5_MISO, SAI3_FS_B, LPTIM4_IN1, TIM8_BKIN, ETH2_PPS_OUT, ETH2_MDC, FMC_A21, LCD_R7, DCMI_VSYNC/PSSI_RDY/DCMIPP_VSYNC, EVENTOUT PVD_IN, ADC1_INP4, ADC2_INP4 K1 R3 L1 PG5 I/O TT_f (1) TRACED3, HDP3, USART6_RTS/USART6_DE, TIM2_CH3, I2C6_SDA, LCD_R5, DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK, EVENTOUT K2 T3 H2 PG6 I/O TT_f (1) TRACED4, HDP4, SPI5_SCK, SPI1_SCK/I2S1_CK, TIM2_CH4, I2C6_SCL, LCD_R6, DCMI_HSYNC/PSSI_DE/ DCMIPP_HSYNC, EVENTOUT E7 U2 K4 PG7 I/O TT (1) TRACED5, HDP5, SPI5_NSS, SPI1_NSS/I2S1_WS, UART9_CTS, TIM5_ETR, LCD_R7, DCMI_VSYNC/PSSI_RDY/ DCMIPP_VSYNC, EVENTOUT E5 L5 L5 PG8 I/O TT (1) TRACED6, HDP6, SPI5_RDY, SPI1_RDY, USART6_CK, UART5_RTS/UART5_DE, UART9_TX, TIM5_CH3, LCD_G2, DCMI_D2/PSSI_D2/DCMIPP_D2, EVENTOUT G2 M3 G3 PG9 I/O TT (1) TRACED7, UART5_TX, TIM5_CH4, LCD_G3, DCMI_D3/ PSSI_D3/DCMIPP_D3, EVENTOUT - F5 M4 H3 PG10 I/O TT (1) TRACED8, HDP0, UART5_RX, TIM8_CH4N, LCD_G4, DCMI_D4/PSSI_D4/DCMIPP_D4, EVENTOUT - F7 N2 J4 PG11 I/O TT (1) TRACED9, HDP1, SPI7_MOSI, FDCAN1_TX, TIM8_CH4, LCD_G5, DCMI_D5/PSSI_D5/DCMIPP_D5, EVENTOUT - H7 N3 J3 PG12 I/O TT (1) TRACED10, HDP2, SPI7_MISO, FDCAN1_RX, TIM8_CH1N, LCD_G6, DCMI_D6/PSSI_D6/DCMIPP_D6, EVENTOUT - J7 P1 K5 PG13 I/O TT_f (1) TRACED11, HDP3, SPI7_SCK, MDF1_CKI6, TIM8_CH2N, I2C1_SCL, I3C1_SCL, LCD_G7, DCMI_D7/PSSI_D7/ DCMIPP_D7, EVENTOUT H5 N1 G4 PG14 I/O TT (1) TRACED12, HDP4, SPI7_RDY, MDF1_CKI5, USART1_TX, TIM8_BKIN2, LCD_B1, DCMI_D9/PSSI_D9/DCMIPP_D9, EVENTOUT DS14285 - Rev 2page 67/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 E4 K6 H4 PG15 I/O TT (1) TRACED13, HDP5, LPTIM1_CH2, MDF1_SDI5, USART1_RX, TIM8_ETR, LCD_B2, DCMI_D10/PSSI_D10/DCMIPP_D10, EVENTOUT R1 AG2 V3 OSC_IN I A (13) - OSC_IN R2 AF2 V2 OSC_OUT I/O A (14) - OSC_OUT L14 AC17 V13 PH2 I/O TT_f (1) LPTIM2_CH1, SPI7_RDY, SPDIFRX1_IN3, SAI1_SCK_B, I3C3_SDA, TIM16_CH1, I2C5_SDA, I2C3_SDA, ETH3_RGMII_GTX_CLK, EVENTOUT K14 AE19 W14 PH3 I/O TT_f (1) SPI1_NSS/I2S1_WS, UART7_RX, TIM17_CH1N, TIM5_CH3, I2C7_SCL, ETH3_RGMII_TXD3, EVENTOUT - G12 AB16 AB15 PH4 I/O TT (1) UART7_TX, TIM17_BKIN, TIM5_CH2, LCD_R0, USB3DR_OVRCUR, USBH_HS_OVRCUR, ETH1_PTP_AUX_TS, ETH3_PPS_OUT, EVENTOUT BOOTFAILN M9 AG18 AA15 PH5 I/O TT (1) SAI2_FS_A, UART8_CTS, TIM2_CH1, UART7_RX, LCD_G1, USB3DR_VBUSEN, USBH_HS_VBUSEN, ETH2_PTP_AUX_TS, EVENTOUT WKUP2 L15 AF19 AA14 PH6 I/O TT_f (1) LPTIM2_IN2, SAI1_MCLK_B, I3C3_SCL, TIM16_CH1N, I2C5_SCL, I2C3_SCL, I2C1_SMBA, ETH3_RGMII_TXD2, EVENTOUT L12 AE16 T13 PH7 I/O TT_f (1) SPI1_MOSI/I2S1_SDO, UART4_TX, UART7_RTS/UART7_DE, TIM17_CH1, TIM5_CH4, I2C7_SDA, ETH3_RGMII_RXD2, EVENTOUT M12 AD16 U14 PH8 I/O TT (1) SPI1_MISO/I2S1_SDI, SPDIFRX1_IN3, UART4_RX, UART7_CTS, TIM5_CH1, I2C3_SMBA, I2C5_SMBA, ETH3_RGMII_RXD3, EVENTOUT W8 AA13 AB12 PH9 I/O TT_a (1) SPI6_NSS, SAI3_MCLK_A, USART6_RX, TIM15_CH1N, ETH1_RGMII_CLK125, ETH1_MII_RX_ER, EVENTOUT ADC3_INP4 U10 AF14 U11 PH10 I/O TT_a (1) SPI1_SCK/I2S1_CK, SPI6_MOSI, SAI3_SCK_A, TIM15_CH1, ETH2_MDC, ETH1_MII_TXD2/ETH1_RGMII_TXD2, EVENTOUT ADC3_INP8, ADC3_INN4 T11 AE14 T11 PH11 I/O TT_a (1) SPI6_MISO, SAI3_FS_A, TIM15_CH2, ETH2_MDIO, ETH1_MII_TXD3/ETH1_RGMII_TXD3, EVENTOUT - V8 AF13 AA11 PH12 I/O TT (1) SPI3_NSS/I2S3_WS, SPI6_MISO, TIM10_CH1, ETH1_MII_RXD2/ETH1_RGMII_RXD2, EVENTOUT - DS14285 - Rev 2page 68/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 U9 AG13 AB11 PH13 I/O TT (1) SPI3_SCK/I2S3_CK, SPI6_MOSI, TIM15_BKIN, TIM11_CH1, ETH1_MII_RXD3/ETH1_RGMII_RXD3, EVENTOUT - H1 L7 G5 PI0 I/O TT (1) TRACED14, HDP6, LPTIM1_IN1, SAI4_MCLK_B, USART1_CK, TIM8_BKIN, LCD_B3, DCMI_D11/PSSI_D11/ DCMIPP_D11, EVENTOUT J9 M6 H6 PI1 I/O TT_f (1) TRACED15, HDP7, SPI7_NSS, MDF1_SDI6, TIM8_CH3N, I2C1_SDA, I3C1_SDA, LCD_B4, DCMI_D8/PSSI_D8/ DCMIPP_D8, EVENTOUT J5 N5 J5 PI2 I/O TT (1) LPTIM1_ETR, SAI4_SCK_B, USART1_RTS/USART1_DE, TIM8_CH1, LCD_B5, DCMI_D13/PSSI_D13/DCMIPP_D13, EVENTOUT H9 N7 J6 PI3 I/O TT (1) LPTIM1_IN2, SAI4_SD_B, USART1_CTS/USART1_NSS, TIM8_CH2, LCD_B6, PSSI_D14/DCMIPP_D14, EVENTOUT - G1 P6 K6 PI4 I/O TT (1) LPTIM1_CH1, SAI4_FS_B, TIM8_CH3, LCD_B7, PSSI_D15/ DCMIPP_D15, EVENTOUT - K7 K4 H5 PI5 I/O TT (1) SPI5_MOSI, SPI1_MOSI/I2S1_SDO, UART5_CTS, UART9_RX, TIM5_CH2, LCD_DE, DCMI_D1/PSSI_D1/ DCMIPP_D1, EVENTOUT D4 J3 J7 PI6 I/O TT (1) MCO1, USART3_TX, TIM2_ETR, TIM3_CH1, LCD_VSYNC, EVENTOUT WKUP4 D5 J5 L6 PI7 I/O TT (1) USART3_RX, TIM2_CH1, TIM3_CH2, LCD_HSYNC, EVENTOUT - N4 U5 M6 PI8 I/O TT (6) EVENTOUT RTC_OUT2/ RTC_LSCO, TAMP_IN1/ TAMP_OUT2 K6 U1 K7 PI9 I/O TT (1) SPI7_MOSI, SPI2_MOSI/I2S2_SDO, FDCAN2_TX, UART9_CTS, TIM16_BKIN, SDVSEL2, FMC_NWAIT, DSI_TE, LCD_B0, EVENTOUT B11 D16 G16 PI10 I/O TT (1) SAI1_SCK_A, SPI1_SCK/I2S1_CK, SPDIFRX1_IN0, FDCAN2_RX, MDF1_CCK0, TIM4_CH1, SDVSEL1, FMC_AD12/FMC_D12, DSI_TE, EVENTOUT F12 B27 E18 PI11 I/O TT (1) I2S2_MCK, UART8_TX, UART9_RTS/UART9_DE, TIM4_CH3, SDMMC3_D3, FMC_AD15/FMC_D15, EVENTOUT - - - G1 PI12 I/O TT (1) SPI4_NSS, FDCAN3_RX, TIM11_CH1, FMC_A2, LCD_G0, EVENTOUT - DS14285 - Rev 2page 69/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 - - G2 PI13 I/O TT (1) SPI4_MOSI, FDCAN2_RX, TIM10_CH1, FMC_A3, LCD_G1, EVENTOUT - - - G13 PI14 I/O TT (1) SPI2_NSS/I2S2_WS, MDF1_SDI1, TIM20_CH3, TIM1_CH3N, FMC_NWAIT, FMC_AD10/FMC_D10, DCMI_D4/PSSI_D4/ DCMIPP_D4, EVENTOUT - - E11 PI15 I/O TT (1) I2S2_MCK, UART4_RX, MDF1_CKI2, TIM20_BKIN2, TIM1_BKIN2, SDVSEL1, SDMMC3_CDIR, DCMI_D9/PSSI_D9/ DCMIPP_D9, EVENTOUT - - U15 PJ0 I/O TT (1) SPI5_MOSI, PCIE_CLKREQN, SAI4_D2, USART6_CTS/ USART6_NSS, USBH_HS_VBUSEN, ETH2_PTP_AUX_TS, FMC_A11, ETH3_PPS_OUT, EVENTOUT - - Y3 PJ1 I/O TT_f (1) USART6_RX, TIM8_CH1N, I2C1_SCL, I3C1_SCL, FMC_A7, DCMI_VSYNC/PSSI_RDY/DCMIPP_VSYNC, EVENTOUT - - - AB3 PJ2 I/O TT (1) SAI2_SD_B, UART9_RTS/UART9_DE, TIM8_CH4N, USBH_HS_OVRCUR, FMC_A14, EVENTOUT - - - AA3 PJ3 I/O TT (1) SPI5_NSS, SAI2_FS_A, SAI4_D1, USART6_RTS/ USART6_DE, TIM8_CH3, FMC_A10, EVENTOUT - - - W3 PJ4 I/O TT (1) SAI2_FS_B, MDF1_CCK1, USART6_CK, TIM8_CH4, I2C2_SMBA, I2C5_SMBA, EVENTOUT - - - V4 PJ5 I/O TT (1) SPI5_MISO, SAI2_SCK_B, SAI4_CK1, USART6_TX, TIM8_CH1, FMC_A8, EVENTOUT - - - U5 PJ6 I/O TT (1) SPI7_MOSI, SAI4_SD_A, USART2_CK, TIM20_CH1N, TIM1_CH1, I2C6_SMBA, DCMI_D7/PSSI_D7/DCMIPP_D7, EVENTOUT - - W2 PJ7 I/O TT (1) SPI5_MISO, SAI2_MCLK_B, SAI4_D3, USART6_CK, TIM8_CH2N, I2C1_SMBA, FMC_A12, DCMI_D0/PSSI_D0/ DCMIPP_D0, EVENTOUT - - M2 PJ8 I/O TT (1) SPI5_SCK, SAI4_CK2, USART6_RX, TIM8_CH2, FMC_A9, PSSI_D14/DCMIPP_D14, EVENTOUT - - - M1 PJ9 I/O TT (1) SPI4_RDY, TIM12_CH1, TIM8_BKIN, FMC_A5, DCMI_PIXCLK/ PSSI_PDCK/DCMIPP_PIXCLK, EVENTOUT - - - M3 PJ10 I/O TT_f (1) TIM12_CH2, TIM8_ETR, I2C1_SDA, I3C1_SDA, FMC_A6, DCMI_HSYNC/PSSI_DE/DCMIPP_HSYNC, EVENTOUT - DS14285 - Rev 2page 70/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 - - M5 PJ11 I/O TT (1) SPI5_RDY, SAI2_SCK_A, SAI4_D4, UART9_CTS, TIM8_CH3N, FMC_A13, DCMI_D12/PSSI_D12/DCMIPP_D12, EVENTOUT - - L2 PJ12 I/O TT_f (1) SAI2_SD_A, UART9_RX, FDCAN1_TX, TIM8_BKIN2, I2C2_SCL, I3C2_SCL, FMC_A15, DCMI_D13/PSSI_D13/ DCMIPP_D13, EVENTOUT - - M4 PJ13 I/O TT_f (1) SAI2_MCLK_A, UART9_TX, FDCAN1_RX, TIM10_CH1, I2C2_SDA, I3C2_SDA, PSSI_D15/DCMIPP_D15, EVENTOUT - - - L3 PJ14 I/O TT (1) SPI4_SCK, FDCAN3_TX, FMC_A1, LCD_R0, EVENTOUT - - - K2 PJ15 I/O TT (1) TRACED7, HDP7, SPI4_MISO, FDCAN2_TX, TIM11_CH1, FMC_A4, LCD_R1, EVENTOUT - - - F12 PK0 I/O TT (1) SPI2_MISO/I2S2_SDI, SPDIFRX1_IN2, MDF1_CCK0, TIM20_ETR, TIM1_ETR, SDMMC3_D123DIR, FMC_AD11/ FMC_D11, DCMI_D11/PSSI_D11/DCMIPP_D11, EVENTOUT - - E12 PK1 I/O TT (1) SPI2_MOSI/I2S2_SDO, MDF1_SDI2, TIM20_BKIN, TIM1_BKIN, SDVSEL2, SDMMC3_D0DIR, FMC_AD13/ FMC_D13, DCMI_D10/PSSI_D10/DCMIPP_D10, EVENTOUT - - F13 PK2 I/O TT_f (1) SPI7_NSS, SAI4_SCK_A, USART1_RTS/USART1_DE, TIM20_CH2, TIM1_CH2N, I2C6_SDA, FMC_NCE3, DCMI_D6/ PSSI_D6/DCMIPP_D6, EVENTOUT - - F15 PK3 I/O TT (1) SPI7_RDY, MDF1_CKI1, TIM20_CH3N, TIM1_CH3, FMC_AD8/ FMC_D8, DCMI_D3/PSSI_D3/DCMIPP_D3, FMC_NCE4, EVENTOUT - - F11 PK4 I/O TT (1) SPI7_MISO, UART4_TX, SAI4_FS_A, TIM20_CH1, TIM1_CH1N, SDMMC3_CKIN, FMC_AD9/FMC_D9, DCMI_D8/ PSSI_D8/DCMIPP_D8, EVENTOUT - - F14 PK5 I/O TT_f (1) SPI2_RDY, MDF1_CKI0, USART1_TX, TIM20_CH4N, TIM1_CH4, I2C5_SCL, FMC_AD5/FMC_D5, DCMI_D1/ PSSI_D1/DCMIPP_D1, EVENTOUT - - G12 PK6 I/O TT_f (1) SPI7_SCK, SAI4_MCLK_A, USART1_CTS/USART1_NSS, TIM20_CH2N, TIM1_CH2, I2C6_SCL, FMC_AD14/FMC_D14, FMC_AD7/FMC_D7, DCMI_D5/PSSI_D5/DCMIPP_D5, EVENTOUT - - G14 PK7 I/O TT_f (1) MDF1_SDI0, USART1_RX, TIM20_CH4, TIM1_CH4N, I2C5_SDA, FMC_NCE4, FMC_AD6/FMC_D6, DCMI_D2/ PSSI_D2/DCMIPP_D2, EVENTOUT DS14285 - Rev 2page 71/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 P2 AB4 T6 PWR_CPU_ON O TT (1) - - P1 AF1 U4 PWR_LP O TT (1) - - U3 AD3 T5 PWR_ON O TT (1) - - L5 T4 N5 PZ0 I/O TT_f (15) LPTIM3_IN1, SPI8_MOSI, TIM8_CH1, LPUART1_TX, LPTIM5_OUT, I2C8_SDA, LPTIM3_CH2, I3C4_SDA, EVENTOUT CPU3_SWDIO, TAMP_OUT3 M4 U7 N6 PZ1 I/O TT_f (15) LPTIM3_CH1, SPI8_MISO, TIM8_CH2, LPUART1_RX, LPTIM5_ETR, I2C8_SCL, I2C8_SMBA, I3C4_SCL, EVENTOUT CPU3_SWCLK, TAMP_OUT5 M3 W5 P4 PZ2 I/O TT_f (15) LPTIM3_CH1, SPI8_SCK, ADF1_CCK0, LPUART1_RTS/ LPUART1_DE, LPTIM4_ETR, I2C8_SCL, I3C4_SCL, EVENTOUT TAMP_IN3/ TAMP_OUT7 M5 Y6 N4 PZ3 I/O TT_f (15) DBTRGI, DBTRGO, LPTIM3_ETR, SPI8_NSS, MDF1_SDI5, ADF1_SDI0, LPUART1_CTS, LPTIM4_IN1, I2C8_SDA, LPTIM4_CH2, I3C4_SDA, EVENTOUT TAMP_OUT4 L4 V3 R5 PZ4 I/O TT_f (15) DBTRGI, DBTRGO, MCO2, SPI8_RDY, MDF1_CCK1, ADF1_CCK1, LPUART1_RX, LPTIM4_CH1, I2C8_SCL, I3C4_SCL, EVENTOUT TAMP_IN5/ TAMP_OUT6 N3 R5 P5 PZ5 I/O TT (15) MCO1, LPTIM3_ETR, SPI8_SCK, ADF1_CCK0, LPUART1_RTS/LPUART1_DE, LPTIM5_IN1, LPTIM4_CH2, EVENTOUT TAMP_OUT8 K3 V4 R6 PZ6 I/O TT (15) DBTRGI, DBTRGO, SPI8_NSS, TIM8_CH3, ADF1_SDI0, LPUART1_CTS, LPTIM5_OUT, LPTIM4_CH2, EVENTOUT TAMP_IN8 L1 V2 P2 PZ7 I/O TT (1) SPI8_MOSI, MDF1_CCK1, ADF1_CCK1, LPUART1_TX, LPTIM5_IN1, LPTIM3_CH2, EVENTOUT - L3 V1 P3 PZ8 I/O TT (1) LPTIM3_IN1, SPI8_MISO, MDF1_SDI5, ADF1_SDI0, LPUART1_RX, LPTIM4_CH1, I2C8_SMBA, LPTIM5_ETR, EVENTOUT L2 U3 N3 PZ9 I/O TT_f (1) MCO2, SPI8_RDY, MDF1_CKI5, LPUART1_TX, LPTIM4_ETR, I2C8_SDA, LPTIM3_CH2, I3C4_SDA, EVENTOUT - V11 AG21 AB16 USBH_HS_DM A A - - - V12 AG22 Y17 USB3DR_DM A A - - - W11 AF21 AA16 USBH_HS_DP A A - - - W12 AF22 W17 USB3DR_DP A A - - - DS14285 - Rev 2page 72/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 T15 AE20 V16 USBH_HS_TXRTU NE A A - - - R15 AF23 V17 USB3DR_TXRTUN E A A - - - T12 AD20 U16 DNU A A - - - W15 AF27 Y20 COMBOPHY_REXT A A - - - V16 AF25 AB20 COMBOPHY_RX1N A A - - - U16 AG25 AA20 COMBOPHY_RX1P A A - - - V15 AD24 AB19 COMBOPHY_TX1N A A - - - U15 AE24 AA19 COMBOPHY_TX1P A A - - - U1 AF6 W5 VREF- A A - - - U2 AG6 Y5 VREF+ A A - - - R6 T6 P7 VBAT S - - - - H8 1L1 M9 VDD S - - - - K8 1L3 N8 VDD S - - - - L6 1L5 P9 VDD S - - - - - 1M2 P11 VDD S - - - - - 1M4 R8 VDD S - - - - N6 AB6 V7 VDDA18ADC S - - - - D3 G7 F6 VDDA18CSI S - - - - D16 F20 J16 VDDA18DDR S - - - - C5 G9 C7 VDDA18DSI S - - - - J4 G5 C4 VDDA18LVDS S - (2) - - E15 G19 G17 VDDA18PLL1 S - - - - H6 1E1 L8 VDDA18PLL3 S - - - - G6 H6 K8 VDDA18PLL2 S - - - - DS14285 - Rev 2page 73/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 R13 AE23 W18 VDDA18COMBOPH Y S - - - - T13 AD22 U17 VDDA18USB S - - - - G10 1C1 H7 VDDCORE S - - - - H11 1C3 H9 VDDCORE S - - - - J10 1C5 J8 VDDCORE S - - - - K11 1D2 J10 VDDCORE S - - - - L10 1D4 K9 VDDCORE S - - - - N8 1E3 K11 VDDCORE S - - - - N10 1E5 L10 VDDCORE S - - - - - 1F2 - VDDCORE S - - - - - 1F4 - VDDCORE S - - - - E13 F18 H11 VDDCPU S - - - - G13 G15 H13 VDDCPU S - - - - J13 G17 H15 VDDCPU S - - - - L13 1C7 J12 VDDCPU S - - - - M13 1C9 J14 VDDCPU S - - - - - 1D6 K13 VDDCPU S - - - - - 1D8 L12 VDDCPU S - - - - - 1D10 - VDDCPU S - - - - F16 1C11 K15 VDDQDDR S - - - - J16 1D12 L14 VDDQDDR S - - - - L16 1E11 L16 VDDQDDR S - - - - M16 M22 M15 VDDQDDR S - - - - P16 1F12 N14 VDDQDDR S - - - - T16 N21 P15 VDDQDDR S - - - - - R21 R14 VDDQDDR S - - - - - 1L11 R16 VDDQDDR S - - - - DS14285 - Rev 2page 74/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 - 1M12 - VDDQDDR S - - - - F8 D18 F10 VDDIO2 S - - - - - E17 - VDDIO2 S - - - - M11 1G7 M11 VDDGPU S - (2) - - N14 1G9 M13 VDDGPU S - (2) - - P11 1H6 N10 VDDGPU S - (2) - - P13 1H8 N12 VDDGPU S - (2) - - R10 1H10 P13 VDDGPU S - (2) - - - 1L7 R12 VDDGPU S - (2) - - - 1L9 - VDDGPU S - (2) - - - 1M6 - VDDGPU S - (2) - - - 1M8 - VDDGPU S - (2) - - - 1M10 - VDDGPU S - (2) - - E10 D10 F8 VDDIO3 S - - - - F10 E11 F9 VDDIO3 S - - - - D6 E9 G8 VDDIO4 S - - - - E6 G11 G9 VDDIO4 S - - - - D10 D14 G10 VDDIO1 S - - - - - E13 - VDDIO1 S - - - - U11 AE22 T16 VDD33UCPD S - - - - B1 E5 D5 VDDCSI S - - - - C6 F8 F7 VDDDSI S - - - - J1 F4 G7 VDDLVDS S - (2) - - U12 AC21 V18 VDDPCIECLK S - - - - T14 AB20 V19 VDDCOMBOPHY S - - - - W16 AB22 Y19 VDDCOMBOPHYT X S - - - - DS14285 - Rev 2page 75/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 N5 AB3 R7 VDDA18AON S - - - - R14 AE21 Y16 VDD33USB S - - - - A1 A1 AB1 VSS S - - - - A19 A2 AB22 VSS S - - - - C3 A27 A1 VSS S - - - - C7 AC11 A22 VSS S - - - - D13 AG1 E5 VSS S - - - - E8 AG27 G6 VSS S - - - - E16 C6 H8 VSS S - - - - F6 C10 H10 VSS S - - - - F11 E7 H12 VSS S - - - - F13 F3 H14 VSS S - - - - G8 F12 H16 VSS S - - - - G11 F14 J9 VSS S - - - - H10 F16 J11 VSS S - - - - H13 1A1 J13 VSS S - - - - H16 1A3 J15 VSS S - - - - J6 1A5 K10 VSS S - - - - J8 1A7 K12 VSS S - - - - J11 1A9 K14 VSS S - - - - J14 1A11 L9 VSS S - - - - K4 J7 L11 VSS S - - - - K5 1B2 L13 VSS S - - - - K10 1B4 L15 VSS S - - - - K13 1B6 M10 VSS S - - - - K16 1B8 M12 VSS S - - - - L8 1B10 M14 VSS S - - - - DS14285 - Rev 2page 76/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 L11 1B12 M20 VSS S - - - - M10 K3 N7 VSS S - - - - N11 1E7 N9 VSS S - - - - N13 1E9 N11 VSS S - - - - N16 1F6 N13 VSS S - - - - P8 1F8 N15 VSS S - - - - P10 1F10 P8 VSS S - - - - P14 1G1 P10 VSS S - - - - R11 1G3 P12 VSS S - - - - R16 1G5 P14 VSS S - - - - R18 1G11 R9 VSS S - - - - W1 1H2 R11 VSS S - - - - W19 1H4 R13 VSS S - - - - - 1H12 R15 VSS S - - - - - 1J1 T4 VSS S - - - - - 1J3 U6 VSS S - - - - - 1J5 W8 VSS S - - - - - 1J7 W16 VSS S - - - - - 1J9 W19 VSS S - - - - - V6 - VSS S - - - - DS14285 - Rev 2page 77/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Pin name (function after reset) Pin type I/O structur e Notes Alternate functions Additional functions VFBGA361 VFBGA424 TFBGA436 - Y4 - VSS S - - - - P6 AC5 U7 VSSA S - - - - M6 AC3 M7 VSSAON S - - - - M8 R7 M8 V08CAP A - - - - 1. Power supply is VDD. 2. ball is DNU in some part numbers. 3. Power supply is VDD - used in open drain with external pull-up. 4. Power supply is VDDIO4. 5. Power supply is VDD or VSW - input only in VSW. 6. Power supply is VSW. 7. Power supply is VSW - OSC32_IN pin is also used as digital input in LSE bypass mode and tied to GPIO PC14 input (for test purpose only). 8. Power supply is VSW - OSC32_OUT pin is also tied to GPIO PC15 input (for test purpose only). 9. Power supply is VDDA18AON, must be always connected at board level to VDDA18AON. 10. Power supply is VDDIO3. 11. Power supply is VDDIO1. 12. Power supply is VDDIO2. 13. Power supply is VDDA18AON - OSC_IN pin is also used as digital input in HSE bypass mode and tied to GPIO PH0 input (for test purpose only). 14. Power supply is VDDA18AON - OSC_OUT pin is also tied to GPIO PH1 input, used by Boot ROM to autodetect HSE bypass mode. 15. Power supply is VDD or VSW. DS14285 - Rev 2page 78/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

4.3 Alternate functions

Table 12. Alternate functions AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port B PB1 - SPI3_NSS/ I2S3_WS - - - - - TIM16_CH1N PB2 - - SPI2_MOSI/ I2S2_SDO - - MDF1_CKI3 TIM17_BKIN TIM16_BKIN PB3 - - SPI2_NSS/ I2S2_WS - - MDF1_SDI3 - - PB4 - - SPI2_RDY UART4_CTS SAI4_FS_B MDF1_SDI4 TIM14_CH1 - PB5 - - I2S2_MCK UART4_RTS/ UART4_DE SAI4_SD_B MDF1_CKI4 - - PB6 - - SPI2_MISO/ I2S2_SDI UART4_RX SAI4_SCK_B - - - PB7 - SPI3_SCK/ I2S3_CK - UART4_TX SAI4_MCLK_B - - - PB8 - SPI3_MOSI/ I2S3_SDO - - PCIE_CLKREQN - USART1_TX TIM17_CH1 PB9 - SPI3_RDY - - - - USART1_RTS/ USART1_DE FDCAN1_TX PB10 - SPI3_MISO/ I2S3_SDI - - - - USART1_RX TIM17_CH1N PB11 - I2S3_MCK - - - - USART1_CTS/ USART1_NSS FDCAN1_RX PB12 - - - - - UART8_CTS - TIM13_CH1 PB13 - - SPI7_SCK - SAI1_SD_B UART8_RX - - PB14 - - SPI2_SCK/ I2S2_CK - - MDF1_CKI7 UART9_RX - PB15 - LPTIM1_IN2 SPI5_SCK UART8_RTS/ UART8_DE SAI2_SD_B UART5_RX - TIM3_CH2 Port C PC0 - LPTIM1_CH1 - SPI6_SCK SAI3_MCLK_B USART6_TX - - PC1 - - SPI3_MOSI/ I2S3_SDO - - - USART2_TX - DS14285 - Rev 2page 80/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port C PC2 - SPI8_MOSI LPTIM2_IN1 - SAI4_MCLK_B MDF1_SDI3 USART2_RTS/ USART2_DE - PC3 - LPTIM1_IN2 SPI3_NSS/ I2S3_WS SPI6_RDY - - USART6_RTS/ USART6_DE FDCAN2_TX PC4 - - - SPI6_MISO SAI3_FS_B - - - PC5 - - SPDIFRX1_IN1 - - MDF1_SDI1 - - PC6 - RTC_REFIN SPDIFRX1_IN0 - - MDF1_CKI1 - - PC7 - - - SPI6_MOSI SAI3_SD_B - - - PC8 - LPTIM1_ETR - SPI6_NSS SAI3_SCK_B - USART6_CTS/ USART6_NSS - PC9 - MCO1 SPI3_MISO/ I2S3_SDI - SAI2_SCK_A - - TIM13_CH1 PC10 - - SPI3_MOSI/ I2S3_SDO - - - - LPTIM4_ETR PC11 - LPTIM1_CH1 SPI5_NSS - SAI2_MCLK_A UART5_RTS/ UART5_DE USART3_RTS/ USART3_DE TIM3_CH1 PC12 - LPTIM1_CH2 - I3C3_SCL - MDF1_CKI2 - - Port D PD0 TRACECLK HDP0 SPI7_RDY SAI1_D2 - SAI4_FS_A UART7_RX TIM15_CH2 PD1 - HDP1 SPI1_MISO/ I2S1_SDI SAI1_CK2 - SAI4_SD_A UART7_RTS/ UART7_DE TIM15_CH1 PD2 - HDP2 SPI1_NSS/ I2S1_WS SAI1_CK1 - SAI4_SCK_A UART7_CTS TIM15_BKIN PD3 - SAI1_MCLK_A SPI2_SCK/ I2S2_CK SAI1_D1 - SAI4_MCLK_A UART7_TX TIM15_CH1N PD4 TRACED0 SPI4_MISO HDP3 SAI1_D3 SAI1_SD_B - - - PD5 TRACED1 SPI4_NSS HDP4 SAI1_D4 SAI1_FS_B - - - PD6 TRACED2 SPI4_MOSI HDP5 - SAI1_SCK_B MDF1_SDI2 - - PD7 TRACED3 SPI4_SCK SPI1_RDY - SAI1_MCLK_B MDF1_CKI2 - - DS14285 - Rev 2page 81/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port D PD8 TRACED4 SPI4_RDY I2S1_MCK SAI1_FS_A UART4_CTS MDF1_SDI1 - - PD9 TRACED5 HDP6 SPI1_MOSI/ I2S1_SDO SAI1_SD_A UART4_RTS/ UART4_DE MDF1_CKI1 - - PD10 TRACED6 HDP7 - SAI1_SCK_A UART4_RX MDF1_SDI0 I2C4_SDA - PD11 TRACED7 - SPI1_SCK/ I2S1_CK SAI1_MCLK_A UART4_TX MDF1_CKI0 I2C4_SCL - PD12 - SPI7_MISO SPI2_MISO/ I2S2_SDI SPDIFRX1_IN2 - UART8_RTS/ UART8_DE - - PD13 - - SPI2_NSS/ I2S2_WS - - MDF1_SDI7 UART9_TX - PD14 - - I2S1_MCK - - - - FDCAN1_RX PD15 - SPI1_RDY - - - DSI_TE I2C5_SDA FDCAN1_TX Port E PE0 TRACED2 LPTIM2_CH1 SPI1_SCK/ I2S1_CK SPI3_RDY - - USART3_CK - PE1 TRACED3 LPTIM2_CH2 I2S1_MCK I2S3_MCK - - USART3_RX - PE2 - LPTIM2_ETR SPI1_MISO/ I2S1_SDI SPI3_MOSI/ I2S3_SDO SAI1_SCK_B - - - PE3 TRACECLK - SPI1_RDY SPI3_SCK/ I2S3_CK SAI1_MCLK_B - USART3_TX - PE4 TRACED0 LPTIM2_IN1 SPI1_MOSI/ I2S1_SDO SPI3_MISO/ I2S3_SDI SAI1_SD_B - USART3_CTS/ USART3_NSS FDCAN1_TX PE5 TRACED1 LPTIM2_IN2 SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS SAI1_FS_B - USART3_RTS/ USART3_DE FDCAN1_RX PE6 - SPI4_RDY - - SPDIFRX1_IN2 - USART1_TX - PE7 - - - SAI4_D4 SPDIFRX1_IN3 - USART1_RX - PE8 - SPI4_MOSI - SAI4_CK1 SAI4_MCLK_A MDF1_CKI0 - - PE9 - SPI4_MISO - SAI4_D2 SAI4_FS_A - USART1_CK - PE10 - SPI4_SCK - SAI4_D1 SAI4_SD_A - USART1_CTS/ USART1_NSS - DS14285 - Rev 2page 82/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port E PE11 - - SPI7_SCK SAI4_D3 SAI1_FS_A - - TIM15_CH2 PE12 - SPI4_NSS - SAI4_CK2 SAI4_SCK_A MDF1_SDI0 USART1_RTS/ USART1_DE - PE13 - - SPI7_MISO - SAI1_SD_A - - TIM15_CH1 PE14 - - SPI7_NSS - SAI1_MCLK_A MDF1_CKI6 - TIM15_BKIN PE15 - - SPI7_MOSI - SAI1_SCK_A MDF1_SDI6 - TIM15_CH1N Port F PF0 - - SPI3_SCK/ I2S3_CK - - - - FDCAN2_RX PF1 - SPI8_MISO LPTIM2_IN2 - SAI4_SCK_B MDF1_CKI4 USART2_CK - PF2 - - SPI3_RDY - - - I2C4_SMBA - PF3 - - - UART8_RX SAI2_SCK_B MDF1_CCK0 - TIM3_CH4 PF4 - RTC_OUT2 SPI6_NSS - SAI3_SCK_A - USART6_RX TIM4_CH4 PF5 - - SPI6_SCK - SAI3_MCLK_A - USART6_TX TIM4_CH3 PF6 - RTC_OUT2 - SAI3_MCLK_B - - USART6_CK TIM12_CH1 PF7 - - SPDIFRX1_IN1 SPI6_SCK SAI3_SD_A - - TIM2_ETR PF8 - RTC_REFIN - SAI3_SCK_B - - USART3_RX TIM12_CH2 PF9 - - - SAI3_SD_B SAI2_SD_A MDF1_SDI5 UART8_RTS/ UART8_DE TIM2_CH2 PF10 - MCO2 SPI3_RDY - SAI2_MCLK_A MDF1_CKI6 UART8_TX TIM2_CH3 PF11 - MCO1 SPDIFRX1_IN0 SPI6_RDY SAI2_SCK_A MDF1_SDI6 UART8_RX TIM2_CH4 PF12 TRACECLK - SPI5_MISO SPI1_MISO/ I2S1_SDI - - UART9_RTS/ UART9_DE - PF13 TRACED0 HDP0 AUDIOCLK USART6_TX SPI2_NSS/ I2S2_WS MDF1_CKI7 USART3_CTS/ USART3_NSS FDCAN3_TX PF14 TRACED1 HDP1 - USART6_RX - MDF1_SDI7 USART3_RTS/ USART3_DE FDCAN3_RX PF15 TRACED2 HDP2 SPI2_RDY USART6_CTS/ USART6_NSS SPI2_SCK/ I2S2_CK - USART3_CK TIM2_CH2 DS14285 - Rev 2page 83/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port G PG0 - LPTIM1_IN1 - I3C3_SDA - MDF1_SDI2 - - PG1 - LPTIM1_IN1 I2S3_MCK I3C3_SCL SAI2_SD_A UART5_CTS USART3_CTS/ USART3_NSS - PG2 - RTC_REFIN I2S3_MCK I3C3_SDA SAI2_FS_A - USART3_CK - PG3 - LPTIM1_ETR SPI5_MOSI UART8_TX SAI2_FS_B - - TIM3_CH3 PG4 - - SPI5_MISO SAI3_FS_B - - - LPTIM4_IN1 PG5 TRACED3 HDP3 - USART6_RTS/ USART6_DE - - - TIM2_CH3 PG6 TRACED4 HDP4 SPI5_SCK SPI1_SCK/ I2S1_CK - - - TIM2_CH4 PG7 TRACED5 HDP5 SPI5_NSS SPI1_NSS/ I2S1_WS - - UART9_CTS - PG8 TRACED6 HDP6 SPI5_RDY SPI1_RDY USART6_CK UART5_RTS/ UART5_DE UART9_TX - PG9 TRACED7 - - - - UART5_TX - - PG1

0 TRACED8 HDP0 - - - UART5_RX - -

PG11 TRACED9 HDP1 SPI7_MOSI - - - - FDCAN1_TX PG1

2 TRACED10 HDP2 SPI7_MISO - - - - FDCAN1_RX

3 TRACED11 HDP3 SPI7_SCK - - MDF1_CKI6 - -

4 TRACED12 HDP4 SPI7_RDY - - MDF1_CKI5 USART1_TX -

5 TRACED13 HDP5 - LPTIM1_CH2 - MDF1_SDI5 USART1_RX -

PH2 - LPTIM2_CH1 SPI7_RDY SPDIFRX1_IN3 SAI1_SCK_B I3C3_SDA - TIM16_CH1 PH3 - - SPI1_NSS/ I2S1_WS - - - UART7_RX TIM17_CH1N PH4 - - - - - - UART7_TX TIM17_BKIN DS14285 - Rev 2page 84/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port H PH5 - - - - SAI2_FS_A - UART8_CTS TIM2_CH1 PH6 - LPTIM2_IN2 - - SAI1_MCLK_B I3C3_SCL - TIM16_CH1N PH7 - - SPI1_MOSI/ I2S1_SDO - UART4_TX - UART7_RTS/ UART7_DE TIM17_CH1 PH8 - - SPI1_MISO/ I2S1_SDI SPDIFRX1_IN3 UART4_RX - UART7_CTS - PH9 - - - SPI6_NSS SAI3_MCLK_A - USART6_RX TIM15_CH1N PH10 - - SPI1_SCK/ I2S1_CK SPI6_MOSI SAI3_SCK_A - - TIM15_CH1 PH11 - - - SPI6_MISO SAI3_FS_A - - TIM15_CH2 PH12 - - SPI3_NSS/ I2S3_WS SPI6_MISO - - - - PH13 - - SPI3_SCK/ I2S3_CK SPI6_MOSI - - - TIM15_BKIN Port I PI0 TRACED14 HDP6 - LPTIM1_IN1 SAI4_MCLK_B - USART1_CK - PI1 TRACED15 HDP7 SPI7_NSS - - MDF1_SDI6 - - PI2 - - - LPTIM1_ETR SAI4_SCK_B - USART1_RTS/ USART1_DE - PI3 - - - LPTIM1_IN2 SAI4_SD_B - USART1_CTS/ USART1_NSS - PI4 - - - LPTIM1_CH1 SAI4_FS_B - - - PI5 - - SPI5_MOSI SPI1_MOSI/ I2S1_SDO - UART5_CTS UART9_RX - PI6 - MCO1 - - - - USART3_TX TIM2_ETR PI7 - - - - - - USART3_RX TIM2_CH1 PI9 - SPI7_MOSI SPI2_MOSI/ I2S2_SDO - FDCAN2_TX - UART9_CTS - DS14285 - Rev 2page 85/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port I PI10 - SAI1_SCK_A SPI1_SCK/ I2S1_CK SPDIFRX1_IN0 FDCAN2_RX MDF1_CCK0 - - PI11 - - I2S2_MCK - - UART8_TX UART9_RTS/ UART9_DE - PI12 - - SPI4_NSS - - - - FDCAN3_RX PI13 - - SPI4_MOSI - FDCAN2_RX - - - PI14 - - SPI2_NSS/ I2S2_WS - - MDF1_SDI1 - TIM20_CH3 PI15 - - I2S2_MCK UART4_RX - MDF1_CKI2 - TIM20_BKIN2 Port J PJ0 - - SPI5_MOSI - PCIE_CLKREQN SAI4_D2 USART6_CTS/ USART6_NSS - PJ1 - - - - - - USART6_RX - PJ2 - - - - SAI2_SD_B - UART9_RTS/ UART9_DE - PJ3 - - SPI5_NSS SAI2_FS_A - SAI4_D1 USART6_RTS/ USART6_DE - PJ4 - - - SAI2_FS_B - MDF1_CCK1 USART6_CK - PJ5 - - SPI5_MISO SAI2_SCK_B - SAI4_CK1 USART6_TX - PJ6 - - SPI7_MOSI - SAI4_SD_A - USART2_CK TIM20_CH1N PJ7 - - SPI5_MISO - SAI2_MCLK_B SAI4_D3 USART6_CK - PJ8 - - SPI5_SCK - - SAI4_CK2 USART6_RX - PJ9 - - SPI4_RDY - - - - TIM12_CH1 PJ10 - - - - - - - TIM12_CH2 PJ11 - - SPI5_RDY SAI2_SCK_A - SAI4_D4 UART9_CTS - PJ12 - - - SAI2_SD_A - - UART9_RX FDCAN1_TX PJ13 - - - SAI2_MCLK_A - - UART9_TX FDCAN1_RX PJ14 - - SPI4_SCK - - - - FDCAN3_TX PJ15 TRACED7 HDP7 SPI4_MISO - FDCAN2_TX - - - DS14285 - Rev 2page 86/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 DBG DBG / HDP / LPTIM1/2 / RTC / SAI1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/7/8 / SYS HDP / I2S / LPTIM2/3 / SPDIFRX1 / SPI1 / I2S1 / SPI2 / I2S2 / SPI3 / I2S3 / SPI4/5/6/7 / SYS I3C3 / LPTIM1/2 / SAI1/2/3/4 / SPDIFRX1 / SPI1 / I2S1 / SPI3 / I2S3 / SPI4/6/8 / UART4/8 / USART6 FDCAN2 / MDF1 / PCIE / SAI1/2/3/4 / SPDIFRX1 / SPI2 / I2S2 / TIM8 / UART4 / USART6 ADF1 / DSI / I3C3 / MDF1 / SAI2/4 / UART5/8 / USART1/6 FDCAN3 / I2C4/5 / LPUART1 / TIM14/17 / UART7/8/9 / USART1/2/3/6 FDCAN1/2/3 / LPTIM4/5 / Port K PK0 - - SPI2_MISO/ I2S2_SDI SPDIFRX1_IN2 - MDF1_CCK0 - TIM20_ETR PK1 - - SPI2_MOSI/ I2S2_SDO - - MDF1_SDI2 - TIM20_BKIN PK2 - - SPI7_NSS - SAI4_SCK_A - USART1_RTS/ USART1_DE TIM20_CH2 PK3 - - SPI7_RDY - - MDF1_CKI1 - TIM20_CH3N PK4 - - SPI7_MISO UART4_TX SAI4_FS_A - - TIM20_CH1 PK5 - - SPI2_RDY - - MDF1_CKI0 USART1_TX TIM20_CH4N PK6 - - SPI7_SCK - SAI4_MCLK_A - USART1_CTS/ USART1_NSS TIM20_CH2N PK7 - - - - - MDF1_SDI0 USART1_RX TIM20_CH4 Port Z PZ0 - - LPTIM3_IN1 SPI8_MOSI TIM8_CH1 - LPUART1_TX LPTIM5_OUT PZ1 - - LPTIM3_CH1 SPI8_MISO TIM8_CH2 - LPUART1_RX LPTIM5_ETR PZ2 - - LPTIM3_CH1 SPI8_SCK - ADF1_CCK0 LPUART1_RTS/ LPUART1_DE LPTIM4_ETR PZ3 DBTRGI DBTRGO LPTIM3_ETR SPI8_NSS MDF1_SDI5 ADF1_SDI0 LPUART1_CTS LPTIM4_IN1 PZ4 DBTRGI DBTRGO MCO2 SPI8_RDY MDF1_CCK1 ADF1_CCK1 LPUART1_RX LPTIM4_CH1 PZ5 - MCO1 LPTIM3_ETR SPI8_SCK - ADF1_CCK0 LPUART1_RTS/ LPUART1_DE LPTIM5_IN1 PZ6 DBTRGI DBTRGO - SPI8_NSS TIM8_CH3 ADF1_SDI0 LPUART1_CTS LPTIM5_OUT PZ7 - - - SPI8_MOSI MDF1_CCK1 ADF1_CCK1 LPUART1_TX LPTIM5_IN1 PZ8 - - LPTIM3_IN1 SPI8_MISO MDF1_SDI5 ADF1_SDI0 LPUART1_RX LPTIM4_CH1 PZ9 - MCO2 - SPI8_RDY MDF1_CKI5 - LPUART1_TX LPTIM4_ETR DS14285 - Rev 2page 87/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

Table 13. Alternate functions AF8 to AF15

0 TIM2_CH2 - ETH1_MDIO - LCD_R6 PSSI_D15/DCMIPP_D15 ETH3_RGMII_RXD1/

2 I2C4_SCL I2C6_SCL ETH1_PHY_INTN - - - - EVEN

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port B PB5 TIM20_CH1 I2C2_SCL OCTOSPIM_P2_IO5 - FMC_AD8/FMC_D8 I3C2_SCL SDMMC3_D123DIR EVEN TOUT PB6 TIM20_CH1N - OCTOSPIM_P2_IO6 - FMC_AD9/FMC_D9 - SDMMC3_D0DIR EVEN TOUT PB7 TIM20_ETR TIM12_CH1 OCTOSPIM_P2_IO7 - FMC_AD10/FMC_D10 - SDMMC3_CDIR EVEN TOUT PB8 TIM20_CH4 - OCTOSPIM_P2_NCS1 - FMC_AD12/FMC_D12 - - EVEN TOUT PB9 TIM20_BKIN TIM10_CH1 OCTOSPIM_P2_DQS OCTOSPIM_P2_NCS2 FMC_AD13/FMC_D13 - - EVEN TOUT PB1 0 - - OCTOSPIM_P2_CLK - FMC_AD15/FMC_D15 - - EVEN TOUT PB1

1 TIM20_BKIN2 TIM12_CH2 OCTOSPIM_P2_NCLK OCTOSPIM_P2_NCS2 FMC_AD14/FMC_D14 OCTOSPIM_P1_NCS2 - EVEN

2 - DSI_TE SDMMC3_D2 FMC_NWAIT - - DCMI_D12/PSSI_D12/ DCMIPP_D12 EVEN TOUT PB1 3 - - SDMMC3_CK FMC_AD5/FMC_D5 FMC_AD0/FMC_D0 - - EVEN TOUT PB1 4 - TIM4_CH2 SDMMC3_D0 FMC_AD7/FMC_D7 FMC_AD2/FMC_D2 - - EVEN TOUT PB1

5 TIM5_CH1 - ETH1_PPS_OUT - FMC_A18 LCD_R4 DCMI_D8/PSSI_D8/

DCMIPP_D8 EVEN TOUT Port C PC0 - DCMI_D0/PSSI_D0/ DCMIPP_D0 ETH2_MII_RX_CLK/ETH2_RMII_REF_CLK ETH1_MII_TX_CLK ETH1_RGMII_GTX_CLK LCD_G7 - EVEN TOUT PC1 - I2C7_SCL ETH1_MII_TXD1/ETH1_RGMII_TXD1/ ETH1_RMII_TXD1 - - - - EVEN TOUT PC2 - - ETH1_MII_RXD1/ETH1_RGMII_RXD1/ ETH1_RMII_RXD1 - - - - EVEN TOUT PC3 - - ETH2_MII_RX_DV/ETH2_RGMII_RX_CTL/ ETH2_RMII_CRS_DV ETH1_MII_RX_ER - LCD_G6 DCMI_D3/PSSI_D3/ DCMIPP_D3 EVEN TOUT PC4 - - ETH2_MII_TX_EN/ETH2_RGMII_TX_CTL/ ETH2_RMII_TX_EN - ETH1_RGMII_CLK125 LCD_R0 - EVEN TOUT PC5 TIM8_CH1N I2C4_SDA ETH2_MDIO ETH1_MII_COL FMC_A25 ETH1_PPS_OUT LCD_DE EVEN TOUT PC6 TIM8_CH1 I2C4_SCL ETH2_MDC ETH1_MII_CRS FMC_A24 ETH1_PHY_INTN LCD_CLK EVEN TOUT PC7 TIM8_CH2N - ETH2_MII_TXD0/ETH2_RGMII_TXD0/ ETH2_RMII_TXD0 ETH1_MII_TXD2 - LCD_B4 DCMI_D1/PSSI_D1/ DCMIPP_D1 EVEN TOUT PC8 TIM8_CH2 - ETH2_MII_TXD1/ETH2_RGMII_TXD1/ ETH2_RMII_TXD1 ETH1_MII_TXD3 - LCD_B3 DCMI_D2/PSSI_D2/ DCMIPP_D2 EVEN TOUT PC9 TIM8_CH4N USBH_HS_OVRCU R ETH2_MII_TXD2/ETH2_RGMII_TXD2 USB3DR_OVRCUR FMC_A22 LCD_G2 DCMI_D7/PSSI_D7/ DCMIPP_D7 EVEN TOUT PC1

0 TIM8_CH4 USBH_HS_VBUSEN ETH2_MII_TXD3/ETH2_RGMII_TXD3 USB3DR_VBUSEN FMC_A23 LCD_G3 DCMI_D6/PSSI_D6/

DCMIPP_D6 EVEN TOUT DS14285 - Rev 2page 89/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port C PC1

1 TIM5_ETR - ETH2_MII_RXD3/ETH2_RGMII_RXD3 - FMC_NBL1 LCD_R2 DCMI_D10/PSSI_D10/

DCMIPP_D10 EVEN TOUT PC1

2 TIM8_CH3 I2C3_SCL ETH2_MII_RXD1/ETH2_RGMII_RXD1/

ETH2_RMII_RXD1 ETH1_MII_RXD3 - LCD_G1 DCMI_D5/PSSI_D5/ DCMIPP_D5 EVEN TOUT PC1 TOUT Port D PD0 - SDVSEL1 OCTOSPIM_P1_CLK - - DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK - EVEN TOUT PD1 TIM1_BKIN FDCAN3_RX OCTOSPIM_P1_NCLK OCTOSPIM_P1_NCS2 OCTOSPIM_P2_NCS2 DCMI_HSYNC/PSSI_DE/ DCMIPP_HSYNC - EVEN TOUT PD2 TIM1_ETR FDCAN3_TX OCTOSPIM_P1_DQS OCTOSPIM_P1_NCS2 - DCMI_VSYNC/PSSI_RDY/ DCMIPP_VSYNC - EVEN TOUT PD3 TIM1_BKIN2 SDVSEL2 OCTOSPIM_P1_NCS1 - - PSSI_D15/DCMIPP_D15 - EVEN TOUT PD4 TIM1_CH4N TIM4_CH1 OCTOSPIM_P1_IO0 - - PSSI_D14/DCMIPP_D14 - EVEN TOUT PD5 TIM1_CH3N TIM4_CH2 OCTOSPIM_P1_IO1 - - DCMI_D13/PSSI_D13/ DCMIPP_D13 - EVEN TOUT PD6 TIM1_CH2N TIM4_CH3 OCTOSPIM_P1_IO2 - - DCMI_D12/PSSI_D12/ DCMIPP_D12 - EVEN TOUT PD7 TIM1_CH1N TIM4_CH4 OCTOSPIM_P1_IO3 - - DCMI_D11/PSSI_D11/ DCMIPP_D11 - EVEN TOUT PD8 TIM1_CH4 TIM4_ETR OCTOSPIM_P1_IO4 SDMMC1_D7 SDMMC1_D123DIR DCMI_D10/PSSI_D10/ DCMIPP_D10 - EVEN TOUT PD9 TIM1_CH3 - OCTOSPIM_P1_IO5 SDMMC1_D6 SDMMC1_D0DIR DCMI_D9/PSSI_D9/ DCMIPP_D9 - EVEN TOUT PD1

0 TIM1_CH2 TIM14_CH1 OCTOSPIM_P1_IO6 SDMMC1_D5 SDMMC1_CDIR DCMI_D8/PSSI_D8/

DCMIPP_D8 - EVEN TOUT PD1

1 TIM1_CH1 SDVSEL1 OCTOSPIM_P1_IO7 SDMMC1_D4 SDMMC1_CKIN DCMI_D7/PSSI_D7/

DCMIPP_D7 - EVEN TOUT PD1 2 - TIM4_ETR SDMMC3_CMD FMC_AD6/FMC_D6 FMC_AD1/FMC_D1 - - EVEN TOUT PD1 3 - TIM4_CH4 SDMMC3_D1 FMC_AD11/FMC_D11 FMC_NWE - - EVEN TOUT PD1

4 TIM11_CH1 - I2C7_SDA FMC_AD4/FMC_D4 SDMMC3_D3 DCMI_D1/PSSI_D1/

DCMIPP_D1 - EVEN TOUT PD1

5 TIM1_BKIN2 TIM5_ETR I2C7_SCL FMC_AD3/FMC_D3 SDMMC3_CKIN DCMI_D0/PSSI_D0/

DCMIPP_D0 - EVEN TOUT Port E PE0 - - SDMMC1_D2 - - - - EVEN TOUT PE1 - - SDMMC1_D3 - - - - EVEN TOUT PE2 TIM10_CH1 - SDMMC1_CMD - - - - EVEN TOUT DS14285 - Rev 2page 90/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port E PE3 TIM11_CH1 - SDMMC1_CK - - - - EVEN TOUT PE4 - - SDMMC1_D0 - - - - EVEN TOUT PE5 - - SDMMC1_D1 - - - - EVEN TOUT PE6 TIM1_ETR - - FMC_AD1/FMC_D1 SDMMC2_D6 SDMMC2_D0DIR - EVEN TOUT PE7 TIM1_CH4N - TIM14_CH1 FMC_AD2/FMC_D2 SDMMC2_D7 SDMMC2_D123DIR - EVEN TOUT PE8 TIM1_CH1 - - FMC_A17/FMC_ALE SDMMC2_D2 - - EVEN TOUT PE9 TIM1_CH4 - - FMC_AD0/FMC_D0 SDMMC2_D5 SDMMC2_CDIR - EVEN TOUT PE1

0 TIM1_CH3 - FMC_NE3 FMC_NCE2 SDMMC2_D4 SDMMC2_CKIN - EVEN

1 TIM1_CH3N - - FMC_A16/FMC_CLE SDMMC2_D1 - - EVEN

2 TIM1_CH2 - FMC_NE2 FMC_NCE1 SDMMC2_D3 - - EVEN

3 TIM1_CH2N - - FMC_RNB SDMMC2_D0 - - EVEN

4 TIM1_BKIN - - FMC_NWE SDMMC2_CK - - EVEN

5 TIM1_CH1N - - FMC_NOE SDMMC2_CMD - - EVEN

PF0 TIM12_CH2 I2C2_SDA ETH1_MDC ETH2_MII_CRS - I3C2_SDA - EVEN TOUT PF1 - - ETH1_MII_RXD0/ETH1_RGMII_RXD0/ ETH1_RMII_RXD0 - - - - EVEN TOUT PF2 TIM12_CH1 I2C2_SCL ETH1_MDIO ETH2_MII_COL FMC_NE4 I3C2_SCL - EVEN TOUT PF3 TIM8_BKIN2 ETH1_CLK ETH2_PPS_OUT - FMC_A20 LCD_R6 DCMI_HSYNC/PSSI_DE/ DCMIPP_HSYNC EVEN TOUT PF4 ETH1_MDC ETH2_CLK ETH2_PPS_OUT ETH1_PPS_OUT - LCD_B7 - EVEN TOUT PF5 ETH1_MDIO ETH1_CLK ETH2_PHY_INTN ETH1_PHY_INTN - LCD_B6 - EVEN TOUT PF6 - I2C3_SMBA ETH2_MII_RX_CLK/ETH2_RGMII_RX_CLK/ ETH2_RMII_REF_CLK - - LCD_B0 - EVEN TOUT PF7 - - ETH2_RGMII_GTX_CLK ETH2_MII_TX_CLK - LCD_R1 - EVEN TOUT PF8 - ETH1_CLK ETH2_RGMII_CLK125 ETH2_MII_RX_ER ETH2_MII_RX_DV/ETH2_RMII_CRS_DV LCD_G0 - EVEN TOUT DS14285 - Rev 2page 91/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port F PF9 - - ETH2_MII_RXD2/ETH2_RGMII_RXD2 ETH2_MDIO - - - EVEN TOUT PF1 0 - - ETH2_MII_TXD2 - - - - EVEN TOUT PF11 - - ETH2_MII_TXD3 - - - - EVEN TOUT PF1

2 TIM5_CH1 - - - - LCD_CLK DCMI_D0/PSSI_D0/

DCMIPP_D0 EVEN TOUT PF1

3 TIM3_CH3 - - - - LCD_R2 - EVEN

4 TIM3_CH4 - - - - LCD_R3 - EVEN

5 TIM3_ETR I2C6_SMBA - - - LCD_R4 - EVEN

PG0 TIM8_CH3N I2C3_SDA ETH2_MII_RXD0/ETH2_RGMII_RXD0/ ETH2_RMII_RXD0 ETH1_MII_RXD2 - LCD_G5 DCMI_D4/PSSI_D4/ DCMIPP_D4 EVEN TOUT PG1 TIM5_CH4 I2C3_SCL ETH2_MII_RX_ER ETH2_MII_RXD3 FMC_NBL0 LCD_VSYNC DCMI_D11/PSSI_D11/ DCMIPP_D11 EVEN TOUT PG2 TIM5_CH3 I2C3_SDA ETH2_MII_TX_CLK ETH2_RGMII_CLK125 FMC_CLK LCD_HSYNC - EVEN TOUT PG3 TIM8_ETR ETH2_CLK ETH2_PHY_INTN - FMC_A19 LCD_R5 DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK EVEN TOUT PG4 TIM8_BKIN - ETH2_PPS_OUT ETH2_MDC FMC_A21 LCD_R7 DCMI_VSYNC/PSSI_RDY/ DCMIPP_VSYNC EVEN TOUT PG5 - I2C6_SDA - - - LCD_R5 DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK EVEN TOUT PG6 - I2C6_SCL - - - LCD_R6 DCMI_HSYNC/PSSI_DE/ DCMIPP_HSYNC EVEN TOUT PG7 TIM5_ETR - - - - LCD_R7 DCMI_VSYNC/PSSI_RDY/ DCMIPP_VSYNC EVEN TOUT PG8 TIM5_CH3 - - - - LCD_G2 DCMI_D2/PSSI_D2/ DCMIPP_D2 EVEN TOUT PG9 TIM5_CH4 - - - - LCD_G3 DCMI_D3/PSSI_D3/ DCMIPP_D3 EVEN TOUT PG1

0 TIM8_CH4N - - - - LCD_G4 DCMI_D4/PSSI_D4/

DCMIPP_D4 EVEN TOUT PG1

1 TIM8_CH4 - - - - LCD_G5 DCMI_D5/PSSI_D5/

DCMIPP_D5 EVEN TOUT PG1

2 TIM8_CH1N - - - - LCD_G6 DCMI_D6/PSSI_D6/

DCMIPP_D6 EVEN TOUT PG1

3 TIM8_CH2N I2C1_SCL I3C1_SCL - - LCD_G7 DCMI_D7/PSSI_D7/

DCMIPP_D7 EVEN TOUT PG1

4 TIM8_BKIN2 - - - - LCD_B1 DCMI_D9/PSSI_D9/

DCMIPP_D9 EVEN TOUT DS14285 - Rev 2page 92/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port G PG1

5 TIM8_ETR - - - - LCD_B2 DCMI_D10/PSSI_D10/

DCMIPP_D10 EVEN TOUT Port H PH2 I2C5_SDA I2C3_SDA - - - - ETH3_RGMII_GTX_CLK EVEN TOUT PH3 - TIM5_CH3 I2C7_SCL - - - ETH3_RGMII_TXD3 EVEN TOUT PH4 - TIM5_CH2 LCD_R0 USB3DR_OVRCUR USBH_HS_OVRCUR ETH1_PTP_AUX_TS ETH3_PPS_OUT EVEN TOUT PH5 UART7_RX - LCD_G1 USB3DR_VBUSEN USBH_HS_VBUSEN ETH2_PTP_AUX_TS - EVEN TOUT PH6 I2C5_SCL I2C3_SCL I2C1_SMBA - - - ETH3_RGMII_TXD2 EVEN TOUT PH7 - TIM5_CH4 I2C7_SDA - - - ETH3_RGMII_RXD2 EVEN TOUT PH8 - TIM5_CH1 I2C3_SMBA I2C5_SMBA - - ETH3_RGMII_RXD3 EVEN TOUT PH9 - - ETH1_RGMII_CLK125 ETH1_MII_RX_ER - - - EVEN TOUT PH1 0 - ETH2_MDC ETH1_MII_TXD2/ETH1_RGMII_TXD2 - - - - EVEN TOUT PH1 1 - ETH2_MDIO ETH1_MII_TXD3/ETH1_RGMII_TXD3 - - - - EVEN TOUT PH1

2 TIM10_CH1 - ETH1_MII_RXD2/ETH1_RGMII_RXD2 - - - - EVEN

3 TIM11_CH1 - ETH1_MII_RXD3/ETH1_RGMII_RXD3 - - - - EVEN

PI0 TIM8_BKIN - - - - LCD_B3 DCMI_D11/PSSI_D11/ DCMIPP_D11 EVEN TOUT PI1 TIM8_CH3N I2C1_SDA I3C1_SDA - - LCD_B4 DCMI_D8/PSSI_D8/ DCMIPP_D8 EVEN TOUT PI2 TIM8_CH1 - - - - LCD_B5 DCMI_D13/PSSI_D13/ DCMIPP_D13 EVEN TOUT PI3 TIM8_CH2 - - - - LCD_B6 PSSI_D14/DCMIPP_D14 EVEN TOUT PI4 TIM8_CH3 - - - - LCD_B7 PSSI_D15/DCMIPP_D15 EVEN TOUT PI5 TIM5_CH2 - - - - LCD_DE DCMI_D1/PSSI_D1/ DCMIPP_D1 EVEN TOUT PI6 TIM3_CH1 - - - - LCD_VSYNC - EVEN TOUT PI7 TIM3_CH2 - - - - LCD_HSYNC - EVEN TOUT DS14285 - Rev 2page 93/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port I PI8 - - - - - - - EVEN TOUT PI9 TIM16_BKIN SDVSEL2 FMC_NWAIT - DSI_TE LCD_B0 - EVEN TOUT PI10 TIM4_CH1 SDVSEL1 - - FMC_AD12/FMC_D12 DSI_TE - EVEN TOUT PI11 - TIM4_CH3 SDMMC3_D3 FMC_AD15/FMC_D15 - - - EVEN TOUT PI12 TIM11_CH1 - - - FMC_A2 LCD_G0 - EVEN TOUT PI13 TIM10_CH1 - - - FMC_A3 LCD_G1 - EVEN TOUT PI14 TIM1_CH3N - FMC_NWAIT - FMC_AD10/FMC_D10 DCMI_D4/PSSI_D4/ DCMIPP_D4 - EVEN TOUT PI15 TIM1_BKIN2 SDVSEL1 SDMMC3_CDIR - - DCMI_D9/PSSI_D9/ DCMIPP_D9 - EVEN TOUT Port J PJ0 - USBH_HS_VBUSEN - ETH2_PTP_AUX_TS FMC_A11 ETH3_PPS_OUT - EVEN TOUT PJ1 TIM8_CH1N I2C1_SCL I3C1_SCL - FMC_A7 - DCMI_VSYNC/PSSI_RDY/ DCMIPP_VSYNC EVEN TOUT PJ2 TIM8_CH4N USBH_HS_OVRCU R - - FMC_A14 - - EVEN TOUT PJ3 TIM8_CH3 - - - FMC_A10 - - EVEN TOUT PJ4 TIM8_CH4 I2C2_SMBA I2C5_SMBA - - - - EVEN TOUT PJ5 TIM8_CH1 - - - FMC_A8 - - EVEN TOUT PJ6 TIM1_CH1 I2C6_SMBA - - - DCMI_D7/PSSI_D7/ DCMIPP_D7 - EVEN TOUT PJ7 TIM8_CH2N I2C1_SMBA - - FMC_A12 - DCMI_D0/PSSI_D0/ DCMIPP_D0 EVEN TOUT PJ8 TIM8_CH2 - - - FMC_A9 - PSSI_D14/DCMIPP_D14 EVEN TOUT PJ9 TIM8_BKIN - - - FMC_A5 - DCMI_PIXCLK/PSSI_PDCK/ DCMIPP_PIXCLK EVEN TOUT PJ10 TIM8_ETR I2C1_SDA I3C1_SDA - FMC_A6 - DCMI_HSYNC/PSSI_DE/ DCMIPP_HSYNC EVEN TOUT PJ11 TIM8_CH3N - - - FMC_A13 - DCMI_D12/PSSI_D12/ DCMIPP_D12 EVEN TOUT PJ12 TIM8_BKIN2 I2C2_SCL I3C2_SCL - FMC_A15 - DCMI_D13/PSSI_D13/ DCMIPP_D13 EVEN TOUT PJ13 TIM10_CH1 I2C2_SDA I3C2_SDA - - - PSSI_D15/DCMIPP_D15 EVEN TOUT DS14285 - Rev 2page 94/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ETH1 / I2C2/4/5/8 / I3C1 / 1/12/16/20 / UART7 / USART2 DCMI / PSSI / DCMIPP / DSI / ETH1/2 / FDCAN3 / LPTIM5 / SDMMC1/2 / TIM4/5/10/12/14 / USBH_HS ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / TIM14 ETH1/2 / FMC / I2C3/5 / I3C4 / LCD / OCTOSPIM_P1/2 / SDMMC1 / USB3DR DSI / ETH1/2 / FMC / I2C4 / LCD / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS DCMI / PSSI / DCMIPP / DSI / ETH1/2/3 / I3C2 / LCD / OCTOSPIM_P1 / SDMMC2 DCMI / PSSI / DCMIPP / ETH3 / FMC / LCD / SDMMC3 SYS Port J PJ14 - - - - FMC_A1 LCD_R0 - EVEN TOUT PJ15 TIM11_CH1 - - - FMC_A4 LCD_R1 - EVEN TOUT Port K PK0 TIM1_ETR - SDMMC3_D123DIR - FMC_AD11/FMC_D11 DCMI_D11/PSSI_D11/ DCMIPP_D11 - EVEN TOUT PK1 TIM1_BKIN SDVSEL2 SDMMC3_D0DIR - FMC_AD13/FMC_D13 DCMI_D10/PSSI_D10/ DCMIPP_D10 - EVEN TOUT PK2 TIM1_CH2N I2C6_SDA - - FMC_NCE3 DCMI_D6/PSSI_D6/ DCMIPP_D6 - EVEN TOUT PK3 TIM1_CH3 - - - FMC_AD8/FMC_D8 DCMI_D3/PSSI_D3/ DCMIPP_D3 FMC_NCE4 EVEN TOUT PK4 TIM1_CH1N - SDMMC3_CKIN - FMC_AD9/FMC_D9 DCMI_D8/PSSI_D8/ DCMIPP_D8 - EVEN TOUT PK5 TIM1_CH4 - I2C5_SCL - FMC_AD5/FMC_D5 DCMI_D1/PSSI_D1/ DCMIPP_D1 - EVEN TOUT PK6 TIM1_CH2 I2C6_SCL - FMC_AD14/FMC_D14 FMC_AD7/FMC_D7 DCMI_D5/PSSI_D5/ DCMIPP_D5 - EVEN TOUT PK7 TIM1_CH4N - I2C5_SDA FMC_NCE4 FMC_AD6/FMC_D6 DCMI_D2/PSSI_D2/ DCMIPP_D2 - EVEN TOUT Port Z PZ0 I2C8_SDA - LPTIM3_CH2 I3C4_SDA - - - EVEN TOUT PZ1 I2C8_SCL I2C8_SMBA - I3C4_SCL - - - EVEN TOUT PZ2 I2C8_SCL - - I3C4_SCL - - - EVEN TOUT PZ3 I2C8_SDA - LPTIM4_CH2 I3C4_SDA - - - EVEN TOUT PZ4 I2C8_SCL - - I3C4_SCL - - - EVEN TOUT PZ5 - - LPTIM4_CH2 - - - - EVEN TOUT PZ6 - - LPTIM4_CH2 - - - - EVEN TOUT PZ7 - - LPTIM3_CH2 - - - - EVEN TOUT PZ8 I2C8_SMBA LPTIM5_ETR - - - - - EVEN TOUT PZ9 I2C8_SDA - LPTIM3_CH2 I3C4_SDA - - - EVEN TOUT DS14285 - Rev 2page 95/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Pinouts/ballouts, pin description, and alternate functions Prerelease product(s)

5 Memory mapping

Refer to the product line reference manual (RM0457) for details on the memory mapping as well as the boundary addresses for all peripherals. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Memory mapping DS14285 - Rev 2 page 96/234 Prerelease product(s)

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 ° C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V, VDDCORE = 0.82 V, VDDCPU = 0.8 V, VDDGPU = 0.8 V. They are given only as design guidelines and are not tested in production. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9 .

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10 . Figure 9. Pin loading conditions Figure 10. Pin input voltage

Electrical characteristics

DS14285 - Rev 2 page 97/234 Prerelease product(s)

6.1.6 Power supply scheme

Figure 11. Power supply scheme DS14285 - Rev 2 page 98/234 Prerelease product(s)

Caution: Each power supply pair (VDD/VSS, VDDCORE/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. The number of needed capacitances and their values are provided in AN5489 "Getting started with STM32MP25x lines hardware development" available from the ST website www.st.com.

6.1.7 Current consumption measurement

Figure 12. Current consumption measurement scheme

6.2 Absolute maximum ratings

DS14285 - Rev 2 page 99/234 Prerelease product(s)

Table 14. Voltage characteristics Specified by design, not tested in production.

1.8 V supply voltage (including VDDA18AON, VDDA18PLL1,

  1. VIN maximum must always be respected. Refer to next table for the maximum allowed injected current values.

Table 15. Current characteristics Specified by design, not tested in production.

  1. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the positive and

negative injected currents (instantaneous values). Table 16. Thermal characteristics Specified by design, not tested in production. DS14285 - Rev 2 page 100/234 Prerelease product(s)

6.3 Operating conditions

6.3.1 General operating conditions

Table 17. General operating conditions Voltages in this table represent DC value at ball level. DS14285 - Rev 2 page 101/234 Prerelease product(s)

Symbol Parameter Operating conditions Min Typ Max Unit VDDCPU Cortex-A35 supply voltage Run1, Stop1 or LP- Stop1 mode, Fcpu1_overdrive range(1) 0.87 0.91 0.935 V Run1, Stop1 or LP- Stop1 mode, Fcpu1 range 0.765 0.8 0.842 V LPLV-Stop1 Run2, Stop2, LP- Stop2 , LPLV-Stop2 or Standby1/2 mode 0 0 0.48 V VDDGPU(1) GPU supply voltage Fgpu1_overdrive range 0.86 0.9 0.961 V Fgpu1 range 0.76 0.8 0.839 V VDDA18PLL1, VDDA18PLL2, VDDA18PLL3, VDDA18DSI, VDDA18CSI, VDDA18LVDS, VDDA18COMBOPH Y(8)(10)

1.8 V analog supply for PLLs, DSI/CSI/LVDS PHYs and

COMBOPHY 1.71 1.8 1.89(4) V VDDA18DDR(11) 1.8 V analog supply for DDRPHY 1.71 1.8 1.89 V VDDA18USB(11) 1.8 V analog supply for USBPHY 1.75 1.8 1.89(4) V VDD33USB, VDD33UCPD 3.3V USB supply 3.07 3.3 3.6 V VDDA18ADC ADC operating voltage 1.62 1.8 1.89(4) V VREF+ ADC reference voltage 1.1 - VDDA18ADC V VBAT Backup operating voltage 2.3(12) - 3.6 V VDDQDDR DDR PHY supply voltage(2) DDR3L memory 1.283 1.35 1.45 VDDR4 memory 1.14 1.2 1.26 LPDDR4 memory 1.06 1.1 1.17 V08CAP Backup regulator output voltage(13) 0.72 0.8 0.88 V VIN I/O Input voltage I/O -0.3 - VDDxx + 0.3 (14) V I/O when ADC is used VDDA18ADC + 0.3 ANA0/ANA1 I/O when PVD_IN is used VDDA18AON + 0.3 UCPD IOs VDD3V3_UCPD + 1.935 DDR I/O VDDQDDR TJ Junction temperature range Suffix 3 version -40 - 125 ° C 1. Feature might be limited or absent in some devices or packages. See Table 1 for details. 2. Values depend on the external memory device choice. 3. VDDA18AON and VDD must be present before any other supply. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 102/234 Prerelease product(s)

  1. Static condition. 1.98 V allowed during transients. 5. Requires VDDIOVRSEL = 0. 6. These supplies are independent, that means each one could be in any of the following voltage ranges: 0 V (OFF), 1.8 V, 3 V or 3.3 V. 7. Requires VDDIOxVRSEL = 0 8. All these supplies are usually connected together. 9. This is the max allowed voltage, however LPLV-Stop mode is relevant only to save power, so requires voltage as low as possible (that is external regulator set for typical value, then the maximum voltage is few percent above the typical due to regulator accuracy). 10. The VDDA18PLLx must be connected together. 11. Could be connected to other VDDA18xx supplies if min/max range fullfilled. 12. Except when connected to VDD where lower limit is then 1.71 V. 13. This pin is used only to connect a decoupling capacitor for internal backup regulator, this pin must never be used externally for other purposes. 14. VDDxx stands for VDD, VDDIO1, VDDIO2, VDDIO3 or VDDIO4.

6.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions. Table 18. Operating conditions at power-up / power-down VDDA18AON and VDD must be present before other supplies.

  1. VDDA18AON and VDD must be present before any other supply.

6.3.3 Embedded reset and power control block characteristics

temperature and supply voltage conditions summarized in Table 17. General operating conditions. DS14285 - Rev 2 page 103/234 Prerelease product(s)

Table 19. Embedded reset and power control block characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Guaranteed by test in production.

6.3.4 Embedded reference voltage

VDD supply voltage conditions summarized in Table 17. General operating conditions . DS14285 - Rev 2 page 104/234 Prerelease product(s)

Table 20. Embedded reference voltage characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Guaranteed by test in production.
  2. Specified by design, not tested in production.

Table 21. Embedded reference voltage calibration value

  1. This is BSEC_FVR110 register which is not automatically shadowed with OTP content, so a fuse read sequence must be
  2. Must be read in 32‑bit words and relevant masking and shifting must be performed to isolate the required bits.

6.3.5 Supply current characteristics

location in memory and executed binary code. The current consumption is measured as described in Figure 12. Current consumption measurement scheme.

6.3.5.1 Typical and maximum current consumption

  • All I/O pins are in analog input mode except when explicitly mentioned
  • All peripherals are disabled except when explicitly mentioned
  • RTC/LSE are disabled, unless otherwise specified
  • BKPSRAM, RETRAM, LPSRAM1 backup supplies in low-power modes (such as LPLV-Stop, Standby and VBAT modes) are disabled, unless otherwise specified STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 105/234 Prerelease product(s)

  • Unless otherwise specified, the typical values are obtained for: – VDD / VDDIOx/VBAT = 3.3 V – VDDCORE = 0.82 V – VDDCPU = 0.8 V – VDDGPU = 0.8 V – VDDA18 / VDDA18AON = 1.8 V and the maximum values are obtained for: – VDD / VDDIOx / VBAT = 3.6 V – VDDCORE = 0.842 V – VDDCPU = 0.842 V – VDDGPU = 0.839 V – VDDA18 / VDDA18AON = 1.89 V The parameters given in Table 22 to Table 34 are derived from tests performed under supply voltage conditions summarized in Table 17. General operating conditions . STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 106/234 Prerelease product(s)

Table 22. Current consumption (IDDCORE) in Run modes Evaluated by characterization, not tested in production unless otherwise specified. Prerelease product(s)

  • D1 (CPU1)(1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCORE(7) Supply current in Run mode All peripherals Enabled(4) DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 600 mA600 - - 800 170 240 500 680 1100 IDDCORE(8) Supply current in Run mode All peripherals Enabled(4) DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 170 240 510 680 1100 mA 1200 600 - - - 170 240 500 680 1100 750 600 - - - 170 240 500 680 1100 600 600 - - - 170 240 500 680 1100 IDDCORE(9) Supply current in Run mode All peripherals Enabled(4) DRun (CRun: P0) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 160 230 490 670 1000 mA 1200 600 - - - 160 230 490 670 1000 750 600 - - - 160 230 490 670 1000 600 600 - - - 160 230 490 670 1000 IDDCORE(10) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (CRun) SRun1 (CRun) HSE + HSI + PLL 1500(5) 600 400 200 900(6) 97 160 420 600 940 mA 1200 600 400 200 800 97 160 420 600 940 750 600 400 200 800 96.5 160 420 600 940 600 600 400 200 800 96.5 160 420 600 930 IDDCORE(11) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (CRun) SRun1 (CRun) HSE + HSI + PLL 1500(5) 600 400 200 - 97 160 420 600 930 mA 1200 600 400 200 - 97 160 420 600 930 750 600 400 200 - 96.5 160 420 600 930 600 600 400 200 - 96.5 160 420 600 930 IDDCORE Supply current in Run mode All peripherals Disabled DRun (CRun: P0) Run1 (CRun) SRun1 (CRun) HSE + HSI + PLL 1500(5) 600 400 200 - 97 160 420 600 930 mA 1200 600 400 200 - 97 160 420 600 930 750 600 400 200 - 96.5 160 420 600 930 600 600 400 200 - 96.5 160 420 600 930 IDDCORE(11) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 49.5 100 370 540 870 mA 1200 600 - - - 49 100 370 540 870 750 600 - - - 49 100 360 540 870 600 600 - - - 48.5 100 360 540 870 300 300 - - - 43.5 94 360 530 860 DS14285 - Rev 2page 108/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Prerelease product(s)

  • D1 (CPU1)(1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCORE(11) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 150 mA 150 - - - 41 91 350 530 860 HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850 HSE + HSI HSE HSE 40 - - - 35.5 84 350 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DRun (CRun: P0) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 49 100 370 540 870 mA 1200 600 - - - 49 100 360 540 870 750 600 - - - 48.5 100 360 540 870 600 600 - - - 48.5 100 360 540 870 300 300 - - - 43.5 94 360 530 860 150 150 - - - 41 91 350 530 860 HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850 HSE + HSI HSE HSE 40 - - - 35.5 84 350 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DStop1 (CStop) Run1 (CRun) SRun1 (CStop) HSE + HSI + PLL - HSI 64 400 - - 83 140 400 580 910 mA - HSI 64 200 - - 56 110 370 550 870 - HSI 64 100 - - 43 92 360 530 860 HSI - HSI 64 HSI 64 - - 38.5 89 350 520 850 HSE + HSI - HSI 64 HSE 40 - - 34 82 350 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DStandby(12) (13) (CStandby) Run2 (CRun) SRun1 (CStop) HSE + HSI + PLL - HSI 64 400 - - 83 160 400 580 910 mA - HSI 64 200 - - 56 120 370 550 870 - HSI 64 100 - - 43 95 360 530 860 HSI - HSI 64 HSI 64 - - 38.5 90 350 520 850 HSE + HSI - HSI 64 HSE 40 - - 34 83 350 520 840 IDDCORE Supply current in Run mode All peripherals Disabled DStandby (CStandby)(12) (13) Run2 (CRun) SRun1 (CRun) HSE + HSI + PLL - HSI 64 400 200 - 85 170 410 580 910 mA - HSI 64 200 100 - 57.5 120 370 550 870 DS14285 - Rev 2page 109/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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  • D1 (CPU1)(1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCORE Supply current in Run mode All peripherals Disabled DStandby (CStandby)(12) (13) Run2 (CRun) SRun1 (CRun) HSE + HSI + PLL mA HSI 64 100 50 - 43.5 95 360 530 860 HSI - HSI 64 HSI HSI 64 - 39 91 350 530 850 HSE + HSI - HSI 64 HSE HSE 40 - 34.5 83 350 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DRun (CSleep) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 49 100 360 540 870 mA 1200 600 - - - 49 100 360 540 870 750 600 - - - 48.5 100 360 540 870 600 600 - - - 48.5 100 360 540 870 300 300 - - - 43.5 94 360 530 860 150 150 - - - 41 91 350 530 860 HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850 HSE + HSI HSE HSE 40 - - - 35.5 84 350 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DRun(14) (eCSleep) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 48.5 99 360 540 870 mA 1200 600 - - - 48.5 99 360 540 870 750 600 - - - 48.5 99 360 540 870 600 600 - - - 48.5 99 360 540 870 300 300 - - - 43.5 94 360 530 860 150 150 - - - 41 91 350 530 860 HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850 HSE + HSI HSE HSE 40 - - - 35.5 84 350 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DStop1 (CStop) Run1 (CSleep) SRun1 (CStop) HSE + HSI + PLL - HSI 64 400 - - 65.5 120 380 560 890 mA - HSI 64 200 - - 47.5 97 360 540 860 - HSI 64 100 - - 38.5 87 350 530 850 HSI - HSI 64 HSI 64 - - 35.5 85 350 520 850 DS14285 - Rev 2page 110/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Prerelease product(s)

  • D1 (CPU1)(1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCORE Supply current in Run mode All peripherals Disabled DStop1 (CStop) Run1 (CSleep) SRun1 (CStop) HSE + HSI mA- HSI 64 HSE 40 - - 32.5 80 340 520 850 IDDCORE Supply current in Run mode All peripherals Disabled DStandby (CStandby)(12) (13) Run2 (CSleep) SRun1 (CStop) HSE + HSI + PLL - HSI 64 400 - - 65.5 130 380 560 880 mA - HSI 64 200 - - 47.5 110 360 540 860 - HSI 64 100 - - 38.5 88 350 530 850 HSI - HSI 64 HSI 64 - - 35.5 86 350 520 850 HSE + HSI - HSI 64 HSE 40 - - 32.5 80 340 520 840 1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software while other core is clock gated (either in WFI or WFE or not present in the device). 2. ck_icn_ddr. 3. Values for STM32MP257x. 4. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of initialized peripherals and their activity. 5. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V. 6. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V. 7. Values for STM32MP255x. 8. Values for STM32MP253x. 9. Values for STM32MP251x. 10. Values for STM32MP257x and STM32MP255x. 11. Not relevant for STM32MP251x. 12. CStandby = CStop and PDDS_D1 = 1. 13. VDDCPU is shutdown.. 14. eCSleep mean CPU1 in enhanced CSleep with PLL1 automatically stopped (RCC_C1SREQSETR.ESLPREQ=1). DS14285 - Rev 2page 111/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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Table 23. Current consumption (IDDCPU) in Run modes Evaluated by characterization, not tested in production unless otherwise specified. Prerelease product(s)

D1 (CPU1) (1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCPU(8) Supply current in Run mode All peripherals Enabled(4) DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 245 290 360 410 530 mA 1200 600 - - - 165 210 270 320 420 750 600 - - - 105 130 200 240 330 600 600 - - - 84 110 170 220 300 IDDCPU(9) Supply current in Run mode All peripherals Enabled(4) DRun (CRun: P0) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 130 160 230 270 380 mA 1200 600 - - - 89.5 120 180 220 310 750 600 - - - 57 73 140 180 270 600 600 - - - 46 61 130 170 260 IDDCPU(3) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (CRun) SRun1 (CRun) HSE + HSI + PLL 1500(5) 600 400 200 900(6) 245 290 360 410 540 mA 1200 600 400 200 800 165 210 270 320 410 750 600 400 200 800 105 130 200 240 330 600 600 400 200 800 84 110 170 220 310 IDDCPU(10) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (CRun) SRun1 (CRun) HSE + HSI + PLL 1500(5) 600 400 200 - 245 290 360 410 510 mA 1200 600 400 200 - 165 210 270 320 410 750 600 400 200 - 105 130 200 240 330 600 600 400 200 - 84 110 170 220 310 IDDCPU(9) Supply current in Run mode All peripherals Disabled DRun (CRun: P0) Run1 (CRun) SRun1 (CRun) HSE + HSI + PLL 1500(5) 600 400 200 - 130 160 230 280 370 mA 1200 600 400 200 - 89.5 120 180 220 310 750 600 400 200 - 57 73 140 190 270 600 600 400 200 - 46 60 130 170 260 IDDCPU(10) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 245 290 360 410 510 mA 1200 600 - - - 165 210 270 320 410 750 600 - - - 105 130 200 240 330 600 600 - - - 84 110 170 220 310 300 300 - - - 43.5 58 120 170 250 150 150 - - - 22.5 34 95 140 230 HSI HSI 64 HSI 64 - - - 11 23 81 130 220 DS14285 - Rev 2page 113/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Prerelease product(s)

D1 (CPU1) (1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCPU(10) Supply current in Run mode All peripherals Disabled DRun (CRun: P0&P1) Run1 (Cstop) SRun1 (CStop) HSE + HSI mAHSE 40 HSE 40 - - - 7.45 16 77 130 210 IDDCPU Supply current in Run mode All peripherals Disabled DRun (CRun: P0) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 130 160 230 280 370 mA 1200 600 - - - 89.5 120 180 220 310 750 600 - - - 57 73 140 180 270 600 600 - - - 46 61 130 170 260 300 300 - - - 24 35 97 150 230 150 150 - - - 13 23 84 130 220 HSI HSI 64 HSI 64 - - - 6.85 17 76 120 210 HSE + HSI HSE 40 HSE 40 - - - 5 14 74 120 210 IDDCPU Supply current in Run mode All peripherals Disabled DStop1 (CStop) Run1 (CRun) SRun1 (CStop) HSE + HSI + PLL - HSI 64 400 - - 2.25 10 71 120 200 mA - HSI 64 200 - - 2.3 9.9 71 120 200 - HSI 64 100 - - 2.25 9.9 71 120 200 - HSI 64 HSI 64 - - 2.25 9.9 71 120 200 - HSI 64 HSE 40 - - 2.25 9.9 71 120 200 IDDCPU Supply current in Run mode All peripherals Disabled DRun (CSleep) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 19 29 93 140 230 mA 1200 600 - - - 13.5 23 84 130 220 750 600 - - - 9.15 18 79 130 210 600 600 - - - 7.75 17 77 130 210 300 300 - - - 5.05 14 74 120 210 150 150 - - - 3.65 12 72 120 210 HSI HSI 64 HSI 64 - - - 2.85 11 71 120 200 HSE + HSI HSE 40 HSE 40 - - - 2.6 11 71 120 200 IDDCPU Supply current in Run mode All peripherals Disabled DRun(11) (eCSleep) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 1500(5) 600 - - - 3.35 12 76 130 210 mA1200 600 - - - 2.85 11 72 120 200 750 600 - - - 2.85 11 72 120 200 DS14285 - Rev 2page 114/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Prerelease product(s)

D1 (CPU1) (1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDCPU Supply current in Run mode All peripherals Disabled DRun(11) (eCSleep) Run1 (Cstop) SRun1 (CStop) HSE + HSI + PLL 600 mA 600 - - - 2.85 11 72 120 200 300 300 - - - 2.85 11 72 120 200 150 150 - - - 2.85 11 72 120 200 HSI HSI 64 HSI 64 - - - 2.8 11 72 120 200 HSE + HSI HSE 40 HSE 40 - - - 2.65 11 71 120 200 IDDCPU Supply current in Run mode All peripherals Disabled DStop1 (CStop) Run1 (CSleep) SRun1 (CStop) HSE + HSI + PLL - HSI 64 400 - - 2.3 9.9 71 120 200 mA - HSI 64 200 - - 2.25 9.9 71 120 200 - HSI 64 100 - - 2.25 9.9 71 120 200 HSI - HSI 64 HSI 64 - - 2.25 9.9 71 120 200 HSE + HSI - HSI 64 HSE 40 - - 2.25 9.9 71 120 200 1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software while other core is clock gated (either in WFI or WFE or not present in the device). 2. ck_icn_ddr. 3. Values for STM32MP257x. 4. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of initialized peripherals and their activity. 5. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V. 6. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V. 7. Values for STM32MP255x. 8. Values for STM32MP253x. 9. Values for STM32MP251x. 10. Not relevant for STM32MP251x. 11. eCSleep mean CPU1 in enhanced CSleep (RCC_C1SREQSETR.ESLPREQ = 1). DS14285 - Rev 2page 115/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Prerelease product(s)

Table 24. Current consumption (IDDGPU) in Run modes Evaluated by characterization, not tested in production unless otherwise specified. Not relevant for STM32MP251x and STM32MP253x. Value are without GPU activity.

  1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software

while other core is clock gated (either in WFI or WFE or not present in the device).

  1. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of initialized

peripherals and their activity.

  1. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V.
  2. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V.

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Table 25. Current consumption (IDD) in Run modes Evaluated by characterization, not tested in production unless otherwise specified. Prerelease product(s)

  1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software while other core is clock gated (either in WFI or WFE or not present in the device). 2. ck_icn_ddr. 3. Typical value given with VDD = 3.3 V, maximum value given with VDD = 3.6 V. 4. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V. 5. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V. 6. Typical value given with VDD = 1.8 V, maximum value given with VDD = 1.89 V. 7. CStandby = CStop and PDDS_D1 = 1. 8. VDDCPU is shutdown. DS14285 - Rev 2page 118/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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Table 26. Current consumption (IDDA18) in Run modes Evaluated by characterization, not tested in production unless otherwise specified.

  1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software

while other core is clock gated (either in WFI or WFE or not present in the device).

  1. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V.
  2. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V.
  3. CStandby = CStop and PDDS_D1 = 1.

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Table 27. Current consumption (IDDA18AON) in Run modes Evaluated by characterization, not tested in production unless otherwise specified. Prerelease product(s)

  • D1 (CPU1)(1) mode (CPU2) mode (CPU3) mode Osc. CPU1 clk (MHz) AXI clk (MHz) (2) CPU2 clk (MHz) CPU3 clk (MHz) GPU clk (MHz) TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDA18AON Supply current in Run mode (VDD = 3.3 V) All peripherals Disabled DStandby (CStandby)(5) (6) Run2 (CRun) SRun1 (CRun) HSI - HSI 64 HSI HSI 64 - 455 530 550 560 600 μA 1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software while other core is clock gated (either in WFI or WFE or not present in the device). 2. ck_icn_ddr. 3. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V. 4. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V. 5. CStandby = CStop and PDDS_D1 = 1. 6. VDDCPU is shutdown.

Table 28. Current consumption (IBAT) in Run modes Evaluated by characterization, not tested in production unless otherwise specified. Prerelease product(s)

Table 29. Current consumption in Stop modes Evaluated by characterization, not tested in production unless otherwise specified.

1.8 V(3) 280 300 305 315 370 370 380 430 μA

3.3 V(2) 250 265 275 285 320 320 340 380 μA

1.8 V(3) 280 295 305 315 370 370 380 430 μA

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UnitD1 (CPU1) mode D2 (CPU2) mode D3 (CPU3) mode CPU3 clk (MHz) VDD voltage TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDGPU(1) Supply current in Stop2 mode DStandby(4) (5) (CStandby) Stop2 (CStop) SRun2 (CRun) MSI 4 - -(6) - IDD VDD = VDD = IDDA18AON VDD = VDD = (CStandby)(4)(5) Stop2 (CStop) SRun2 (CSleep) HSI 64 23 110 185 300 66 290 440 710 mA IDDCPU -(6) - IDDGPU(1) -(6) - IDD VDD = VDD = IDDA18AON VDD = VDD = 23 110 185 300 66 290 440 710 mA IDDCPU -(6) - IDDGPU(1) -(6) - IDD VDD = VDD = DS14285 - Rev 2page 123/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Prerelease product(s)

UnitD1 (CPU1) mode D2 (CPU2) mode D3 (CPU3) mode CPU3 clk (MHz) VDD voltage TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDA18AON Supply current in Stop2 mode DStandby (CStandby)(4)(5) Stop2 (CStop) SRun2 (CSleep) MSI 4 VDD = VDD = (CStandby)(4)(5) Stop2 (CStop) SSTop1 (CStop) - 16.5 105 175 295 58 290 430 700 mA IDDCPU -(6) - IDDGPU(1) -(6) - IDD VDD = VDD = IDDA18AON VDD = VDD =

  1. Not relevant for STM32MP251x. 2. typical values given for VDD = 3.3 V, maximum values for VDD = 3.6 V. 3. typical values given for VDD = 1.8 V, maximum values for VDD = 1.89 V. 4. CStandby = CStop and PDDS_D1 = 1. 5. VDDCPU is shutdown. 6. Supply is OFF. DS14285 - Rev 2page 124/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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Table 30. Current consumption in LPLV-Stop modes Evaluated by characterization, not tested in production unless otherwise specified.

3.3 V(5) 250 270 275 285 580 330 340 650 μA

1.8 V(6) 280 300 305 320 630 370 390 680 μA

3.3 V(5) 250 270 275 285 320 330 340 390 μA

1.8 V(6) 280 300 305 320 370 370 390 460 μA

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UnitD1 (CPU1) mode D2 (CPU2) mode D3 (CPU3) (1) mode CPU3 clk (MHz) VDD voltage TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDGPU(3) Supply current in LPLV-Stop2 mode DStandby (CStandby) LPLV- Stop2(2) (CStop) SRun3 (CRun) LSE 0.032768 - -(4) - IDD VDD = VDD = IDDA18 - -(4) - IDDA18AON VDD =

3.3 V(5) 250 270 275 285 580 330 340 360 μA

VDD =

1.8 V(6) 280 300 305 320 520 370 390 440 μA

(CStandby)(7) LPLV- Stop2(2) (CStop) SRun3 (CSleep) MSI 4 16 110 190 320 63 320 490 810 mA IDDCPU -(4) - IDDGPU(3) -(4) - IDD VDD = VDD = IDDA18 - -(4) - IDDA18AON VDD = VDD = 0.032768 16 110 190 320 110 320 490 820 mA IDDCPU -(4) - IDDGPU(3) -(4) - IDD VDD = VDD = IDDA18 - -(4) - DS14285 - Rev 2page 126/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Prerelease product(s)

UnitD1 (CPU1) mode D2 (CPU2) mode D3 (CPU3) (1) mode CPU3 clk (MHz) VDD voltage TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDA18AON Supply current in LPLV-Stop2 mode DStandby (CStandby)(7) LPLV- Stop2(2) (CStop) SRun3 (CSleep) LSE 0.032768 VDD = VDD =

1.8 V(6) 280 300 305 320 340 370 390 440 μA

(CStandby)(7) LPLV-Stop2 (CStop)(2) SStop2 (CStop) - 16 110 190 315 110 320 490 810 mA IDDCPU -(4) - IDDGPU(3) -(4) - IDD VDD = VDD = IDDA18 - -(4) - IDDA18AON VDD = VDD =

  1. Domain clocked by MSI 4 MHz. 2. Typical value given with VDDCORE = 0.67 V, maximum values given with VDDCORE = 0.71 V. 3. Not relevant for STM32MP251x. 4. Supply is OFF. 5. Typical values given for VDD = 3.3 V, maximum values for VDD = 3.6 V. 6. Typical values given for VDD = 1.8 V, maximum values for VDD = 1.89 V. 7. CStandby = CStop and PDDS_D1 = 1. DS14285 - Rev 2page 127/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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Table 31. Current consumption in Standby1 mode Evaluated by characterization, not tested in production unless otherwise specified. VDDCORE, VDDCPU and VDDGPU are shutdown. Prerelease product(s)

UnitD3 (CPU3) mode CPU3 clk (MHz) VDD voltage TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C IDDA18AON Supply current in Standby1 mode SStop2 (CStop) - VDD = 1.8 V(2) 60 80 80 88 110 150 160 180 μA 1. typical values given for VDD = 3.3 V, maximum values for VDD = 3.6 V. 2. typical values given for VDD = 1.8 V, maximum values for VDD = 1.89 V. 3. Supply is OFF. DS14285 - Rev 2page 129/234 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D Prerelease product(s)

Table 32. Current consumption in Standby2 mode Evaluated by characterization, not tested in production unless otherwise specified. VDDCORE, VDDCPU and VDDGPU are shutdown. D3 (CPU3) in CStop (SStandby).

  1. Typical values given for VDD = 3.3 V, maximum values for VDD = 3.6 V.
  2. LSE is set to medium-high drive.
  3. typical values given for VDD = 1.8 V, maximum values for VDD = 1.89 V.

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Table 33. Current consumption in VBAT1 mode Evaluated by characterization, not tested in production unless otherwise specified.

  1. LSE is set to medium-high drive.

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Table 34. Current consumption in VBAT2 mode Evaluated by characterization, not tested in production unless otherwise specified. D3 (CPU3) in CStop (SStandby).

  1. LSE is set to medium-high drive.

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6.3.5.2 I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

6.3.5.3 I/O static current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 61. I/O static characteristics. be configured as analog inputs. up/down resistors or by configuring the pins in output mode.

6.3.5.4 I/O dynamic current consumption

(internal or external) connected to the pin.

  • ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
  • VDDx is the MCU supply voltage
  • fSW is the I/O switching frequency
  • CL is the total capacitance seen by the I/O pin: C = CINT + CEXT

6.3.6 Wakeup time from low-power modes

  • the CPU1, CPU2 or CPU3 goes in low-power mode after WFI (wait for interrupt) instruction.
  • For CSleep modes: – Interrupt to GIC or NVIC is used to wakeup from low-power modes.
  • For CStop modes (except Standby and VBAT): – For CPU1 and CPU2: EXTI1[x] is used to wakeup from low-power modes. – For CPU3: EXTI2[x] is used to wakeup from low-power modes.
  • For Standby modes: – WKUPx is used to wakeup from low-power modes.
  • For VBAT modes – TAMP_INx is used to wakeup from low-power modes.
  • System mode is equal to D2 domain mode All timings are derived from tests performed under ambient temperature and VDD = 3.3 V. General conditions unless otherwise noted:
  • CPU1 software in SYSRAM
  • CPU2 software in SRAMx
  • CPU3 software in LPSRAMx
  • HSE is 40 MHz
  • When HSI is used, HSIKERON = 0 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 133/234 Prerelease product(s)

  • PWRLP_DLY = 0
  • LPLVDLY_D2 = 187 µs
  • tWUCSleep values are measured with internal interrupt
  • tWUCStop and tWULPLV-Stop values are measured with EXTI pin
  • tWUStandby values are measured with WKUP pin through PWR
  • When VDDCORE or VDDCPU are shutdown or reduces, wakeup time value depend on supply characteristics. – Wakeup time in following tables are measured with 200 μs VDDCORE and VDDCPU setup time – Longer VDDCPU or VDDCORE startup time than 200 μs should be added to the wakeup time value – When voltage is reduced, VDDCORE is assumed to be back to nominal value before LPLVDLY_D2 expiration. Otherwise, LPLVDLY_D2 value should be increased accordingly and this directly impact wakeup time value.

Table 35. D1 (CPU1) low-power mode wakeup timings Evaluated by characterization, not tested in production. Unless otherwise noted.

  1. eCSleep mean CPU1 in enhanced CSleep with PLL1 automatically stopped (RCC_C1SREQSETR.ESLPREQ = 1). In this

mode, CPU1 wake on ck_cpu1_ext2f, then CPU1 switch back automatically to PLL1 after PLL lock time.

  1. HSI active (HSIKERON = 1).
  2. CPU1 wake‑up address register points to SYSRAM code.
  3. LPDS_Dx=1 and LVDS_Dx = 1.
  4. Value in parenthesis is for wakeup using WKUP pin through PWR.

Table 36. D2 (CPU2) low-power mode wakeup timings Evaluated by characterization, not tested in production. Unless otherwise noted. DS14285 - Rev 2 page 134/234 Prerelease product(s)

Symbol D1 (CPU1) mode D2 (CPU2) mode D3 (CPU3) mode Conditions for wakeup domain Typ Max Unit tWUCSleep_CPU2(1) DStop1 (CStop) Run1 (CSleep) (Reset) - - 14 CPU2 clock cycles tWUCStop_CPU2 DRun (CRun) Run1 (CStop) (Reset) HSI 64 MHz - 1.2 µs HSE + PLL

400 MHz 180 - µs

DStop1 (CStop)(2) Stop1 (CStop)(2) (Reset) HSI 64 MHz(3) 2.7 6.2 µs HSI 64 MHz 7.6 - µs HSE + PLL tWULPLV-Stop_CPU2 DStop3 (CStop)(2) (4) LPLV-Stop1 (CStop)(2)(4) (Reset) HSI 64 MHz(5) 900 1200 µs HSI 64 MHz(6) 1000 1300 µs DStandby (CStop) (4)(7) LPLV-Stop2 (CStop)(2)(4) (Reset) HSI 64 MHz 1500 (900)(8) - µs tWUStandby_CPU2 DStandby (CStop) (9) Standby2 (CStop)(9) (Reset)(9) HSI 64 MHz, RETRAM 1700 (800)(10) - µs 1. Specified by design, not tested in production. 2. PDDS_Dx = 0. 3. HSI active (HSIKERON = 1). 4. LPDS_Dx = 1 and LVDS_Dx = 1. 5. CPU2TMPSKP = 1 or PWRLP_DLY = 0. 6. CPU2TMPSKP = 0 and PWRLP_DLY = 100 µs. 7. PDDS_Dx = 1 8. Value in parenthesis is for wakeup using WKUP pin through PWR or wakeup using EXTI without simultaneous CPU1 wakeup. 9. PDDS_Dx = 1. 10. Value in parenthesis is for RAMCFG_RETRAMCCR1.CRCBS[2:0] = 0 (only 16 Kbytes RETRAM CRC check). Table 37. Wakeup time using USART/LPUART Specified by design, not tested in production.

6.3.7 External clock source characteristics

6.3.7.1 High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. Digital and analog bypass modes are available. bypass mode the clock can be a sinusoidal waveform. DS14285 - Rev 2 page 135/234 Prerelease product(s)

Table 38. High-speed external (HSE) user clock characteristics (digital bypass) Evaluated by characterization, not tested in production unless otherwise specified. Figure 13. High-speed external clock source AC timing diagram (digital bypass) Table 39. High-speed external (HSE) user clock characteristics (analog bypass) Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.
  2. With a square wave signal (@25 °C, VDDA18AON = 1.8 V / VPP = 400 mV / VDC = 0.8 V) where VDC is the DC component
  3. With a square wave signal (@25 °C, VDDA18AON = 1.71 V / VPP = 200 mV / VDC = 0.8 V) where VDC is the DC component
  4. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VDDA18AON - 0.1 V) where VDC is the DC component of the input
  5. Startup time measured from the moment it is enabled (by software) to a stabilized analog bypass clock interface is reached.
  6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.

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Figure 14. High-speed external clock source AC timing diagram (analog bypass)

6.3.7.2 Low-speed external user clock generated from an external source

in Figure 15 for digital bypass and Figure 16 for analog bypass. Table 40. Low-speed external (LSE) user clock characteristics (digital bypass) Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.
  2. VSW is equal to VDD when present or VBAT otherwise.

Figure 15. Low-speed external clock source AC timing diagram (digital bypass) DS14285 - Rev 2 page 137/234 Prerelease product(s)

Table 41. Low-speed external (LSE) user clock characteristics (analog bypass) Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.
  2. VSW is equal to VDD when present or VBAT otherwise.
  3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VSW - 0.1 V) where VDC is the DC component of the input signal.

Figure 16. Low-speed external clock source AC timing diagram (analog bypass)

6.3.7.3 High-speed external clock generated from a crystal/ceramic resonator

Table 42. High-speed external (HSE) oscillator characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.
  2. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
  3. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

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  1. Measured from the moment it is enabled (by software) to a stabilized 40 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 10 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 17 ). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and pin capacitance must be included (4 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

Figure 17. Typical application with a 40 MHz crystal

40 MHz

6.3.7.4 Low-speed external clock generated from a crystal/ceramic resonator

Table 43. Low-speed external (LSE) oscillator characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.
  2. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com. DS14285 - Rev 2 page 139/234 Prerelease product(s)

Figure 18. Typical application with a 32.768 kHz crystal

  1. Adding an external resistor between OSC32_IN and OSC32_OUT is forbidden.

6.3.8 External clock source security characteristics

Table 44. High-speed external user clock security system (HSE CSS) Evaluated by characterization, not tested in production unless otherwise specified. Table 45. Low-speed external user clock security system (LSE CSS) Evaluated by characterization, not tested in production unless otherwise specified.

6.3.9 Internal clock source characteristics

temperature and supply voltage conditions summarized in Table 17. General operating conditions . Table 46. HSI oscillator characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Guaranteed by test in production.

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6.3.9.2 4/16 MHz low-power internal RC oscillator (MSI) Table 47. MSI oscillator characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Guaranteed by test in production.

Table 48. LSI oscillator characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Guaranteed by test in production.
  2. VSW is equal to VDD when present or VBAT otherwise.

6.3.10 PLL characteristics

Table 49. PLL1 to PLL8 characteristics Specified by design, not tested in production unless otherwise specified. DS14285 - Rev 2 page 141/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit fFOUTPOSTDIV Divided output clock duty cycle Division by 1 48 50 52 %Even Division 48 50 52 Odd Division 47 50 53 fVCO PLL VCO output - 800 - 3200 MHz tLOCK PLL lock time Frequency lock - - 400 1/fPFD cycles fPFD = 40 MHz (fPLL_IN = 40 MHz, FREFDIV = 1) - - 10 μs Jitter RMS period jitter fVCO = 3200 MHz - - 0.26 +/_ps RMS integrated jitter (10 kHz ‑ 20 MHz) fVCO = 3200 MHz, FPFD = 25 MHz Integer divider - ±2.7 ±6.6 ps fracN divider - - ±11.9 IVDDA18PLL(1) PLL supply current on VDDA18PLL (Analog) fVCO = 3200 MHz FBDIV < 256 - 5750 6850 μA FBDIV > 255 - 7050 8450 fVCO = 800 MHz FBDIV < 256 - 715 860 IVDDCORE(PLL) (1) PLL supply current on VDDCORE (Digital) fVCO = 3200 MHz VDDCORE = 0.82 V - 1200 3650 fVCO = 800 MHz - 295 910 1. Evaluated by characterization, not tested in production. Table 50. PLL_USB characteristics Specified by design, not tested in production unless otherwise specified. Table 51. PLL_DSI characteristics Specified by design, not tested in production unless otherwise specified.

  1. Evaluated by characterization, not tested in production.

Table 52. PLL_LVDS characteristics Specified by design, not tested in production unless otherwise specified. DS14285 - Rev 2 page 142/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit fVCO_OUT MHzPLL VCO output - - 1800 2200 3000 tLOCK(1) PLL lock time - - - - 355 μs fMod Modulation frequency - - - 33 - kHz md Modulation depth - - - 0.25 5 % IVDDA18LVDS(1) PLL supply current on VDDA18LVDS - - - 4.9 - mA IVDDLVDS(1) PLL supply current on VDDLVDS - - - 1.4 - mA 1. Evaluated by characterization, not tested in production.

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows the reduction of electromagnetic interferences (see Table 53. PLL2 to PLL8 SSCG parameters constraints Specified by design, not tested in production.

6.3.12 Memory characteristics

6.3.12.1 OTP characteristics

The characteristics are given at TJ = -40 to 125 °C unless otherwise specified. Table 54. OTP characteristics Evaluated by characterization, not tested in production unless otherwise specified.

6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

6.3.13.1 Functional EMS (electromagnetic susceptibility)

  • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
  • FTB: a burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

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The test results are given in Table 55 . They are based on the EMS levels and classes defined in application note AN1709 available from the ST website www.st.com. Table 55. EMS characteristics Evaluated by characterization, not tested in production. pins exposed to noise (connected to tracks longer than 50 mm on PCB).

6.3.13.2 Designing hardened software to avoid noise problems

application and the software in particular. with the EMC level requested for his application.

6.3.13.3 Software recommendations

  • Corrupted program counter
  • Unexpected reset
  • Critical Data corruption (such as control registers) See also application note AN1015.

6.3.13.4 Electromagnetic Interference (EMI)

Table 56. EMI characteristics for fHSE = 40 MHz and FPLL1 = 1200 MHz Evaluated by characterization, not tested in production.

0.1 MHz to 30 MHz 14

30 MHz to 130 MHz 9

130 MHz to 1 GHz 21

1 GHz to 2 GHz 8

  1. Refer to AN1709 "EMI radiated test" section.
  2. Refer to AN1709 "EMI level classification" section.

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Table 57. EMI characteristics for fHSE = 40 MHz and FPLL1 = 1500 MHz Evaluated by characterization, not tested in production.

0.1 MHz to 30 MHz -

30 MHz to 130 MHz -

130 MHz to 1 GHz -

1 GHz to 2 GHz -

  1. Refer to AN1709 "EMI radiated test" section.
  2. Refer to AN1709 "EMI level classification" section.

6.3.14 Absolute maximum ratings (electrical sensitivity)

determine its performance in terms of electrical sensitivity.

6.3.14.1 Electrostatic discharge (ESD)

Table 58. ESD absolute maximum ratings Evaluated by characterization, not tested in production.

6.3.14.2 Static latchup

  • A supply overvoltage is applied to each power supply pin
  • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard.

Table 59. Electrical sensitivities Evaluated by characterization, not tested in production.

6.3.15 I/O current injection characteristics

basis during the device characterization. DS14285 - Rev 2 page 145/234 Prerelease product(s)

6.3.15.1 Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter:

  • ADC error above a certain limit: higher than 5 LSB total unadjusted error (TUE),
  • Out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range)
  • Other functional failure (for example reset, oscillator frequency deviation). The following tables are the compilation of the SIC1/SIC2 and functional ESD results. Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

Table 60. I/O current injection susceptibility Evaluated by characterization, not tested in production unless otherwise specified.

6.3.16 I/O port characteristics

Table 61. I/O static characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 146/234 Prerelease product(s)

Symbol Parameter Condition Min Typ Max Unit RPD Weak pull-down equivalent resistor(3) 2.7 < VDDx < 3.6 V 30 40 50 kΩ 1.71 < VDDx < 1.89 V 30 40 50 kΩ CIO I/O pin capacitance - - 5 - pF 1. Guaranteed by testing. 2. Specified by design, not tested in production. 3. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for TT I/Os is shown in Figure 19 . Figure 19. VIL/VIH for TT I/Os

6.3.16.1 Output driving current

voltage range and temperature).

  • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run mode consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 15 ).
  • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run mode consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 15 ).

6.3.16.2 Output voltage levels

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Table 62. Output voltage characteristics for all I/Os Evaluated by characterization, not tested in production unless otherwise specified.

  1. Maximum current depend on temperature.

6.3.16.3 Output buffer timing characteristics

Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 148/234 Prerelease product(s)

Speed Symbol Parameter Conditions Min Max Unit 0b01 Fmax(1) Maximum frequency C = 20 pF MHz - 100 C = 10 pF - 166 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 8.1 ns C = 40 pF - 6.7 C = 30 pF - 5.2 C = 20 pF - 3.6 C = 10 pF - 2.2 0b10(3) Fmax(1) Maximum frequency C = 50 pF - 60 MHz C = 40 pF - 75 C = 30 pF - 100 C = 20 pF - 133 C = 10 pF - 190 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 6.3 ns C = 40 pF - 5.1 C = 30 pF - 4 C = 20 pF - 2.9 C = 10 pF - 1.8 0b11(3) Fmax(1) Maximum frequency C = 50 pF - 80 MHz C = 40 pF - 100 C = 30 pF - 120 C = 20 pF - 166 C = 10 pF - 220 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 4.4 ns C = 40 pF - 3.7 C = 30 pF - 2.9 C = 20 pF - 2.2 C = 10 pF - 1.5 1. The maximum frequency is defined with the following conditions : (Tr + Tf) ≤ 2/3 T and Skew ≤ 1/20 T and 45% < Duty cycle < 55%. 2. The fall and rise time are defined respectively between 90% and 10%, and between 10% and 90% of the output waveform. 3. IO compensation enabled. Table 64. Output timing characteristics (VDD/VDDIOx = 1.71 - 1.89 V, VDDIOxVRSEL = 1) Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 149/234 Prerelease product(s)

Speed Symbol Parameter Conditions Min Max Unit 0b00 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 30 pF ns - 7 C = 20 pF - 5 C = 10 pF - 3 0b01 Fmax(1) Maximum frequency C = 50 pF - 45 MHz C = 40 pF - 55 C = 30 pF - 70 C = 20 pF - 100 C = 10 pF - 166 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 7.4 ns C = 40 pF - 6.1 C = 30 pF - 4.7 C = 20 pF - 3.4 C = 10 pF - 2.1 0b10(3) Fmax(1) Maximum frequency C = 50 pF - 60 MHz C = 40 pF - 75 C = 30 pF - 100 C = 20 pF - 133 C = 10 pF - 200 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 5.7 ns C = 40 pF - 4.7 C = 30 pF - 3.7 C = 20 pF - 2.7 C = 10 pF - 1.7 0b11(3) Fmax(1) Maximum frequency C = 50 pF - 80 MHz C = 40 pF - 100 C = 30 pF - 120 C = 20 pF - 166 C = 10 pF - 250 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 4.1 ns C = 40 pF - 3.4 C = 30 pF - 2.7 C = 20 pF - 2 C = 10 pF - 1.3 1. The maximum frequency is defined with the following conditions : (Tr + Tf) ≤ 2/3 T and Skew ≤ 1/20 T and 45% < Duty cycle < 55%. 2. The fall and rise time are defined respectively between 90% and 10%, and between 10% and 90% of the output waveform. 3. IO compensation enabled. Table 65. Output timing characteristics (VDD/VDDIOx = 1.71 - 1.89 V, VDDIOxVRSEL = 0 degraded mode) Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 150/234 Prerelease product(s)

Speed Symbol Parameter Conditions Min Max Unit 0b00 Fmax(1) Maximum frequency C = 40 pF MHz - 15 C = 30 pF - 20 C = 20 pF - 33 C = 10 pF - 45 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 30.2 ns C = 40 pF - 24.4 C = 30 pF - 18.7 C = 20 pF - 13 C = 10 pF - 7.4 0b01 Fmax(1) Maximum frequency C = 50 pF - 15 MHz C = 40 pF - 20 C = 30 pF - 25 C = 20 pF - 37 C = 10 pF - 60 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 21.1 ns C = 40 pF - 17.2 C = 30 pF - 13.3 C = 20 pF - 9.4 C = 10 pF - 5.5 0b10(3) Fmax(1) Maximum frequency C = 50 pF - 20 MHz C = 40 pF - 25 C = 30 pF - 30 C = 20 pF - 45 C = 10 pF - 75 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 17 ns C = 40 pF - 13.9 C = 30 pF - 10.8 C = 20 pF - 7.8 C = 10 pF - 4.5 0b11(3) Fmax(1) Maximum frequency C = 50 pF - 30 MHz C = 40 pF - 35 C = 30 pF - 45 C = 20 pF - 60 C = 10 pF - 85 Tr/Tf(2) Output high to low level fall time and output low to high level rise time C = 50 pF - 11.8 ns C = 40 pF - 9.8 C = 30 pF - 7.9 C = 20 pF - 5.8 C = 10 pF - 3.8 1. The maximum frequency is defined with the following conditions : (Tr + Tf) ≤ 2/3 T and Skew ≤ 1/20 T and 45% < Duty cycle < 55%. 2. The fall and rise time are defined respectively between 90% and 10%, and between 10% and 90% of the output waveform. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 151/234 Prerelease product(s)

  1. IO compensation enabled.

Table 66. GPIO advance config delay characteristics Evaluated by characterization, not tested in production unless otherwise specified.

6.3.17 NRST pin characteristics

Table 61. I/O static characteristics). temperature and supply voltage conditions summarized in Table 17. General operating conditions . Table 67. NRST pin characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance must be minimum (~10% order). Figure 20. Recommended NRST pin protection

  1. The reset network protects the device against parasitic resets.
  2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 67 . Otherwise the reset is not taken into account by the device.

6.3.18 DDR IOs characteristics

  • DDR3L: JESD79-3F with addendum JESD79-3-1A
  • DDR4: JESD79-4D
  • LPDDR4: JESD209-4D STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 152/234 Prerelease product(s)

6.3.19 FMC characteristics

Unless otherwise specified, the parameters given in Table 68 to Table 81. NAND flash write timings for the FMC interface are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. General operating conditions , with the following configuration:

  • Output speed is set to OSPEEDRy[1:0] = 11
  • Measurement points are done at CMOS levels: 0.5 × VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

6.3.19.1 Asynchronous waveforms and timings

Figure 21 through Figure 24 represent asynchronous waveforms and Table 68 through Table 75 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

  • AddressSetupTime = 0x1
  • AddressHoldTime = 0x1
  • DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
  • DataHoldTime = 0x1 (1 × Tfmc_ker_ck for read operations and 2 × Tfmc_ker_ck for write operations)
  • ByteLaneSetup = 0x1
  • BusTurnAroundDuration = 0x0
  • Capacitive load CL = 30 pF In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.

Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Evaluated by characterization, not tested in production unless otherwise specified. Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings Evaluated by characterization, not tested in production unless otherwise specified. NWAIT pulse width is equal to 1 clock cycle. DS14285 - Rev 2 page 153/234 Prerelease product(s)

Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

  1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 154/234 Prerelease product(s)

Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings Evaluated by characterization, not tested in production unless otherwise specified. NWAIT pulse width is equal to 1 clock cycle. Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

  1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 72. Asynchronous multiplexed PSRAM/NOR read timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 155/234 Prerelease product(s)

Symbol Parameter Min Typ Max Unit tv(NADV_NE) ns FMC_NEx low to FMC_NADV low 0 - 0.5 tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 - Tfmc_ker_ck + 0.5 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck - 3 - - th(A_NOE) Address hold time after FMC_NOE high Address held until next read operation tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck + 14 - - tsu(Data_NOE) Data to FMC_NOE high setup time 15 - - th(Data_NE) Data hold time after FMC_NEx high 0 - - th(Data_NOE) Data hold time after FMC_NOE high 0 - - Table 73. Asynchronous multiplexed PSRAM/NOR read - NWAIT timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 156/234 Prerelease product(s)

Figure 23. Asynchronous multiplexed PSRAM/NOR read waveforms Table 74. Asynchronous multiplexed PSRAM/NOR write timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 157/234 Prerelease product(s)

Table 75. Asynchronous multiplexed PSRAM/NOR write - NWAIT timings Evaluated by characterization, not tested in production unless otherwise specified. Figure 24. Asynchronous multiplexed PSRAM/NOR write waveforms

6.3.19.2 Synchronous waveforms and timings

  • BurstAccessMode = FMC_BurstAccessMode_Enable
  • MemoryType = FMC_MemoryType_CRAM
  • WriteBurst = FMC_WriteBurst_Enable
  • CLKDivision = 1
  • DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values:
  • For 3.0 V < VDD < 3.6 V, FMC_CLK = 70 MHz at 20 pF STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 158/234 Prerelease product(s)

  • For 1.71 V < VDD < 1.89 V, FMC_CLK = 70 MHz at 20 pF

Table 76. Synchronous non-multiplexed NOR/PSRAM read timings Evaluated by characterization, not tested in production unless otherwise specified.

  1. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

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Figure 25. Synchronous non-multiplexed NOR/PSRAM read timings Table 77. Synchronous non-multiplexed PSRAM write timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 160/234 Prerelease product(s)

Symbol Parameter Min Typ Max Unit th(CLKH‑NWAIT) nsFMC_NWAIT valid after FMC_CLK high 1 - - 1. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). Figure 26. Synchronous non-multiplexed PSRAM write timings Table 78. Synchronous multiplexed NOR/PSRAM read timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 161/234 Prerelease product(s)

Symbol Parameter Min Typ Max Unit th(CLKH‑NWAIT) nsFMC_NWAIT valid after FMC_CLK high 1 - - 1. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). Figure 27. Synchronous multiplexed NOR/PSRAM read timings Table 79. Synchronous multiplexed PSRAM write timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 162/234 Prerelease product(s)

Symbol Parameter Min Typ Max Unit td(CLKL‑ADIV) ns FMC_CLK low to FMC_AD[15:0] invalid 0.5 - - td(CLKL‑DATA) FMC_A/D[15:0] valid data after FMC_CLK low - - 3 td(CLKL‑NBLL) FMC_CLK low to FMC_NBL low 0 - - td(CLKH‑NBLH) FMC_CLK high to FMC_NBL high R × Tfmc_ker_ck / 2 + 2(1) - - tsu(NWAIT‑CLKH) FMC_NWAIT valid before FMC_CLK high 4 - - th(CLKH‑NWAIT) FMC_NWAIT valid after FMC_CLK high 1 - - 1. Clock ratio R = ( FMC_CLK period / fmc_ker_ck period). Figure 28. Synchronous multiplexed PSRAM write timings

6.3.19.3 NAND controller waveforms and timings

  • FMC_SetupTime = 0x01
  • FMC_WaitSetupTime = 0x03
  • FMC_HoldSetupTime = 0x02
  • FMC_HiZSetupTime = 0x01
  • Bank = FMC_Bank_NAND
  • MemoryDataWidth = FMC_MemoryDataWidth_16b
  • ECC = FMC_ECC_Enable
  • ECCPageSize = FMC_ECCPageSize_512Bytes
  • TCLRSetupTime = 0
  • TARSetupTime = 0 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 163/234 Prerelease product(s)

  • CL = 30‑pF In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.

Table 80. NAND flash read timings Evaluated by characterization, not tested in production unless otherwise specified. Figure 29. NAND controller waveforms for read access

  1. y = 7 or 15 depending on the NAND flash memory interface.

Table 81. NAND flash write timings Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 164/234 Prerelease product(s)

Figure 30. NAND controller waveforms for write access

  1. y = 7 or 15 depending on the NAND flash memory interface.

6.3.20 OCTOSPI interface characteristics

Table 17. General operating conditions , with the following configuration:

  • Output speed is set to OSPEEDRy[1:0] = 11
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • IO compensation cell activated
  • VDDIOxVRSEL = 1 for VDDIOx < 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics.

Table 82. OCTOSPI characteristics in SDR mode Evaluated by characterization, not tested in production unless otherwise specified. Values in the table applies to octal and quad SPI mode. DS14285 - Rev 2 page 165/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit ts(IN) ns Data input setup time - 2.5 - - th(IN) Data input hold time - 1.5 - - tv(OUT) Data output valid time - - 0.5 1 th(OUT) Data output hold time - 0 - - Figure 31. OCTOSPI timing diagram - SDR mode Table 83. OCTOSPI characteristics in DTR mode (without DQS) Evaluated by characterization, not tested in production unless otherwise specified. Values in the table applies to octal and quad SPI mode.

  1. When PRESCALER = 0 the DLL must be used for TX delay.

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Figure 32. OCTOSPI timing diagram - DTR mode Table 84. OCTOSPI characteristics in DTR mode (with DQS or HyperBus) Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 167/234 Prerelease product(s)

Figure 35. OCTOSPI HyperBus read with double latency Figure 36. OCTOSPI HyperBus write Host drives DQ[7:0] and the memory drives RWDS. Host drives DQ[7:0] and RWDS.

6.3.21 Delay block (DLYB) characteristics

under the ambient temperature and VDD supply voltage summarized in Table 17. General operating conditions . Table 85. DLYB characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 169/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit t∆ Unit delay Lock mode -1 - +15 % 1. T is the period of the DLL clock. 6.3.22 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 86. ADC characteristics are derived from tests performed under the ambient temperature, frequency and VDDA supply voltage conditions summarized in Table 17. General operating conditions. Table 86. ADC characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.
  2. All analog inputs must be between VSSA and VDDA18ADC.

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Table 87. ADC accuracy Evaluated by characterization, not tested in production unless otherwise specified.

  1. Value measured with a -0.5dBFS input signal and then extrapolated to full scale.

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Figure 37. ADC accuracy characteristics

1 LSB ideal

  1. Refer to Table 88 for the values of RAIN, RADC and CADC.
  2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad

accuracy. To remedy this, fADC should be reduced.

  1. Refer to Table 61. I/O static characteristics for value of Ilkg.
  2. Refer to Figure 11. Power supply scheme .

Table 88. Minimum sampling time versus RAIN Specified by design, not tested in production. DS14285 - Rev 2 page 172/234 Prerelease product(s)

Symbol Parameter Conditions (Resolution / RAIN in ohms) Min Typ Max Unit ts_min Minimum sampling time 10 bits 1500 ns 55 - - 2200 71 - - 3300 97 - - 4700 133 - - 6800(1) 238 - - ts_min Minimum sampling time 8 bits 47 17 - - ns 68 17 - - 100 18 - - 150 19 - - 220 20 - - 330 22 - - 470 25 - - 680 28 - - 1000 34 - - 1500 42 - - 2200 53 - - 3300 70 - - 4700 94 - - 6800 128 - - 10000 183 - - 15000 277 - - 22000(1) 435 - - 1. Maximum external input impedance value authorized for the given Resolution. Figure 38. Typical connection diagram using the ADC with TT pins featuring analog switch function

6.3.22.1 General PCB design guidelines

available from the ST website www.st.com. DS14285 - Rev 2 page 173/234 Prerelease product(s)

6.3.23 Voltage reference buffer (VREFBUF) characteristics

Table 89. VREFBUF characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Static condition. 1.98 V allowed during transients.

6.3.24 Digital Temperature Sensor (DTS) characteristics

Table 90. DTS characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 174/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit TA Accuracy From -40° C to -20 °C °C- - 6 G G constant Refer to reference manual for the formula 59.7 °C H H constant Refer to reference manual for the formula 204.4 °C J J constant Refer to reference manual for the formula -0.16 °C / MHz Cal5 Cal5 constant Refer to reference manual for the formula 4094 - TSloc Sensor location TS0 sensor Inside padring(2) - TS1 sensor Inside device logic(2) - IDTS(VDDA18AON) DTS supply current on VDDA18AON fDTS = 8 MHz, continuous measurements, single sensor - 120 160 μAAt 1 measurement/s - - 1 fDTS clock stopped - - 1 IDTS(VDDCORE) DTS supply current on VDDCORE fDTS = 8 MHz - - 15 μA 1. Guaranteed by test in production. 2. Temperature in padring sensor (side of the silicon die) is usually slightly lower than device logic sensor as most heat is generated inside device logic.

6.3.25 VBAT, VDDCPU, VDDCORE, VDDGPU ADC measurement characteristics

Table 91. VBAT, VDDCPU, VDDCORE, VDDGPU ADC measurement characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Specified by design, not tested in production.

6.3.26 Temperature and VBAT monitoring characteristic for tamper detection

Table 92. TEMP and VBAT Monitoring characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. V08CAP is an internal regulator supplied by VSW. VSW is equal to VDD when present or VBAT otherwise.

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6.3.27 Voltage monitoring characteristics

Table 93. Voltage monitoring characteristics (VDDCORE, VDDCPU, VDDGPU, PVD_IN, VDDA18ADC, VDDIO1/2/3/4, Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 176/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit IRDY_VDDA18ADC Supply current on VDDA18ADC AVMEN = 1 - 1 - μA VDDIO1 monitoring VRDY_VDDIO1 Threshold on rising edge - - - 1.55(1) V Vhyst_VDDIO1 Hysteresis on monitoring - - 40 - mV IRDY_VDDIO1(VDDA18AON) Supply current on VDDA18AON VDDIO1VMEN = 1 - 0.75 - μA IRDY_VDDIO1 Supply current on VDDIO1 Always ON VDDIO1 = 1.8 V - 0.5 - μA VDDIO1 = 3.3 V - 1 - VDDIO2 monitoring VRDY_VDDIO2 Threshold on rising edge - - - 1.55(1) V Vhyst_VDDIO2 Hysteresis on monitoring - - 40 - mV IRDY_VDDIO2(VDDA18AON) Supply current on VDDA18AON VDDIO2VMEN = 1 - 0.75 - μA IRDY_VDDIO2 Supply current on VDDIO2 Always ON VDDIO2 = 1.8 V - 0.5 - μA VDDIO2 = 3.3 V - 1 - VDDIO3 monitoring VRDY_VDDIO3 Threshold on rising edge - - - 1.55(1) V Vhyst_VDDIO3 Hysteresis on monitoring - - 40 - mV IRDY_VDDIO3(VDDA18AON) Supply current on VDDA18AON VDDIO3VMEN = 1 - 0.75 - μA IRDY_VDDIO3 Supply current on VDDIO3 Always ON VDDIO3 = 1.8 V - 0.5 - μA VDDIO3 = 3.3 V - 1 - VDDIO4 monitoring VRDY_VDDIO4 Threshold on rising edge - - - 1.55(1) V Vhyst_VDDIO4 Hysteresis on monitoring - - 40 - mV IRDY_VDDIO4(VDDA18AON) Supply current on VDDA18AON VDDIO4VMEN = 1 - 0.75 - μA IRDY_VDDIO4 Supply current on VDDIO4 Always ON VDDIO4 = 1.8 V - 0.5 - μA VDDIO4 = 3.3 V - 1 - VDD33USB monitoring VRDY_VDD33USB Threshold on rising edge - - - 1.55(1) V Vhyst_VDD33USB Hysteresis on monitoring - - 40 - mV IRDY_VDD33USB(VDDA18AON) Supply current on VDDA18AON USB33VMEN = 1 - 0.75 - μA IRDY_VDD33USB Supply current on VDD33USB Always ON - 1 - μA STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 177/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit VDD33UCPD monitoring VRDY_VDD33UCPD Threshold on rising edge - - - 1.55(1) V Vhyst_VDD33UCPD Hysteresis on monitoring - - 40 - mV IRDY_VDD33UCPD(VDDA18AON) Supply current on VDDA18AON UCPDVMEN = 1 - 0.75 - μA IRDY_VDD33UCPD Supply current on VDD33UCPD Always ON - 1 - μA 1. Guaranteed by test in production.

6.3.28 Compensation cell characteristics

Table 94. Compensation cell characteristics Evaluated by characterization, not tested in production unless otherwise specified.

6.3.29 Multi-function digital filter (MDF) characteristics

  • Capacitive load CL = 30 pF
  • Measurement points done at CMOS levels: 0.5 × VDD
  • I/O compensation cell activated
  • VDDxVRSEL activated when VDDx ≤ 2.7 V

Table 95. MDF characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 178/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit tHCCKO tLCCKO ns MDF_CCK[1:0] output clock high and low time In MASTER SPI mode 2 × Tmdf_proc_ck(1) - - tHCCKOLF tLCCKOLF MDF_CCK[1:0] output clock high and low time In LF_MASTER SPI mode Tmdf_proc_ck(1) - - tSUCKI Data setup time with respect to MDF_CKIx input In SLAVE SPI mode, measured on rising and falling edge 7.5 - - tHDCKI Data hold time with respect to MDF_CKIx input 0.5 - - tSUCCKI Data setup time with respect to MDF_CCK[1:0] input In SLAVE SPI mode: MDF_CCK[1:0] configured in input, measured on rising and falling edge 8.5 - - tHDCCKI Data hold time with respect to MDF_CCK[1:0] input 0.5 - - tSUCCKO Data setup time with respect to MDF_CCK[1:0] output In MASTER SPI mode: MDF_CCK[1:0] configured in output, measured on rising and falling edge 8.5 - - tHDCCKO Data hold time with respect to MDF_CCK[1:0] output 0.5 - - tSUCCKOLF Data setup time with respect to MDF_CCK[1:0] output In LF_MASTER SPI mode, MDF_CCK[1:0] configured in output, measured on rising and falling edge 14.5 - - tHDCCKOLF Data hold time with respect to MDF_CCK[1:0] output 0.5 - - 1. Tmdf_proc_ck is the period of the MDF processing clock. Figure 39. MDF timing diagram

6.3.30 Audio digital filter (ADF) characteristics

  • Capacitive load CL = 30 pF
  • Measurement points done at CMOS levels: 0.5 × VDD
  • I/O compensation cell activated
  • VDDxVRSEL activated when VDDx ≤ 2.7 V

Table 96. ADF characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 179/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit fCCKOLF MHz Output clock frequency in LF_MASTER SPI mode - - - 5 fSYMB Input symbol rate in Manchester mode - - - 20 tHCCKI tLCCKI ADF_CCK[1:0] input clock high and low time In SLAVE SPI mode 2 × Tadf_proc_ck(1) - - ns tHCCKO tLCCKO ADF_CCK[1:0] output clock high and low time In MASTER SPI mode 2 × Tadf_proc_ck(1) - - tHCCKOLF tLCCKOLF ADF_CCK[1:0] output clock high and low time In LF_MASTER SPI mode Tadf_proc_ck(1) - - tSUCCKI Data setup time with respect to ADF_CCK[1:0] input In SLAVE SPI mode: ADF_CCK[1:0] configured in input, measured on rising and falling edge 2.5 - - tHDCCKI Data hold time with respect to ADF_CCK[1:0] input 0.5 - - tSUCCKO Data setup time with respect to ADF_CCK[1:0] output In MASTER SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge 2 - - tHDCCKO Data hold time with respect to ADF_CCK[1:0] output 1 - - tSUCCKOLF Data setup time with respect to ADF_CCK[1:0] output In LF_MASTER SPI mode, ADF_CCK[1:0] configured in output, measured on rising and falling edge 7 - - tHDCCKOLF Data hold time with respect to ADF_CCK[1:0] output 0.5 - - 1. Tadf_proc_ck is the period of the ADF processing clock. Figure 40. ADF timing diagram

6.3.31 Camera interface (DCMI) characteristics

  • DCMI_PIXCLK polarity: falling
  • DCMI_VSYNC and DCMI_HSYNC polarity: high
  • Data formats: 14 bits
  • Capacitive load CL = 30 pF
  • Measurement points done at CMOS levels: 0.5 × VDD
  • I/O compensation cell activated
  • VDDxVRSEL activated when VDDx ≤ 2.7 V STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 180/234 Prerelease product(s)

Table 97. DCMI characteristics Evaluated by characterization, not tested in production unless otherwise specified. Figure 41. DCMI timing diagram

6.3.32 Camera interface (DCMIPP) characteristics

  • DCMIPP_PIXCLK polarity: falling (refer to AN5489 "Getting started with STM32MP25xx lines hardware development") available from the ST website www.st.com.
  • DCMIPP_VSYNC and DCMIPP_HSYNC polarity: high
  • Data formats: 16 bits
  • Capacitive load C = 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell activated
  • VDDxVRSEL activated when VDDx ≤ 2.7 V STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 181/234 Prerelease product(s)

Table 98. DCMIPP characteristics Evaluated by characterization, not tested in production unless otherwise specified. Figure 42. DCMIPP timing diagram

6.3.33 Parallel interface (PSSI) characteristics

  • PSSI_PDCK polarity: falling
  • PSSI_RDY and PSSI_DE polarity: low
  • Bus width: 16 lines
  • Data width: 32 bits
  • Capacitive load CL = 30 pF
  • Measurement points done at CMOS levels: 0.5 × VDD
  • I/O compensation cell activated
  • VDDxVRSEL activated when VDDx ≤ 2.7 V

Table 99. PSSI transmit characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 182/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit tOV(DE) ns DE output valid time - - 10 tOH(DE) DE output hold time 6.5 - - tSU(RDY) RDY input setup time 0 - - tH(RDY) RDY input hold time 5.5 - - 1. This maximal frequency does not consider receiver setup and hold timings. Figure 43. PSSI transmit timing diagram Table 100. PSSI receive characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 183/234 Prerelease product(s)

Figure 44. PSSI receive timing diagram

6.3.34 LCD-TFT controller (LTDC) characteristics

Table 17. General operating conditions, with the following configuration:

  • LCD_CLK polarity: low (signals change on CLK rising edge)
  • LCD_DE polarity: low
  • LCD_VSYNC and LCD_HSYNC polarity: high
  • Pixel formats: 24 bits
  • Output speed is set to: – LTDC Clock: OSPEEDRy[1:0] = 11 – Other LTDC signals: OSPEEDRy[1:0] = 01
  • Advanced I/O configurations: – LTDC Clock: RET = 0, INVCLK = 0, DE = 0, DLYPATH = 0 – Other LTDC signals: RET = 1, INVCLK = 0, DE = 0, DLYPATH = 0
  • Capacitive load C = 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V

Table 101. LTDC characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 184/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit tw(CLKH), tw(CLKL) Clock high time, low time - tw(CLK) / 2 - 0.5 - tw(CLK) / 2 + 0.5 ns tv(DATA) Data output valid time - - - 4 th(DATA) Data output hold time - 1 - - tv(HSYNC), tv(VSYNC), tv(DE) HSYNC/VSYNC/DE output valid time - - - 3.5 th(HSYNC), th(VSYNC), th(DE) HSYNC / VSYNC / DE output hold time - 0.5 - - Figure 45. LCD-TFT horizontal timing diagram DS14285 - Rev 2 page 185/234 Prerelease product(s)

Figure 46. LCD-TFT vertical timing diagram

6.3.35 Timer characteristics

The parameters given in Table 102 are specified by design, not tested in production. (output compare, input capture, external clock, PWM output). Table 102. TIMx characteristics TIMx is used as a general term to refer to the TIM1 to TIM20 timers. Specified by design, not tested in production. Table 103. LPTIMx characteristics LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers. Specified by design, not tested in production. DS14285 - Rev 2 page 186/234 Prerelease product(s)

6.3.36 Communications interfaces

6.3.36.1 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification for:

  • Standard-mode (Sm): with a bit rate up to 100 kbit/s
  • Fast-mode (Fm): with a bit rate up to 400 kbit/s.
  • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are specified by design, not tested in production, when the I2C peripheral is properly configured (refer to product reference manual): The SDA and SCL I/O requirements are met with the following restriction:
  • The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 104. I2C analog filter characteristics for the analog filter characteristics:

Table 104. I2C analog filter characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Spikes with widths below tAF(min) are filtered. At TJ = -40 °C, the guaranteed minimum is 40 ns.
  2. Spikes with widths above tAF(max) are not filtered.

6.3.36.2 I3C interface characteristics

  • I3C SDR-only as controller
  • I3C SDR-only as target
  • I3C SCL bus clock frequency up to 12.5 MHz Unless otherwise specified, the parameters given in Table 105 for the I3C interface are derived from tests performed under the ambient temperature, frequency and supply voltage conditions summarized in
  • Output speed is set to OSPEEDRy[1:0] = 11
  • Capacitive load C = 30 pF
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V

Table 105. I3C specific timings Evaluated by characterization, not tested in production unless otherwise specified. Table 106. I3C pin characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 187/234 Prerelease product(s)

Symbol Parameter Min Typ Max Unit RHK(I3C) I3C high keeper (weak pull‑up) 125 160 195 kΩ

6.3.36.3 SPI interface characteristics

Unless otherwise specified, the parameters given in Table 107 for the SPI interface are derived from tests performed under the ambient temperature, frequency and supply voltage conditions summarized in

  • Output speed is set to OSPEEDRy[1:0] = 11
  • Capacitive load C = 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 107. SPI characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

having tsu(MI) = 0 while Duty(SCK) = 50%. DS14285 - Rev 2 page 188/234 Prerelease product(s)

Figure 49. SPI timing diagram - slave mode and CPHA = 1

6.3.36.4 I2S interface characteristics

  • Output speed is set to OSPEEDRy[1:0] = 01
  • Capacitive load C= 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS).

Table 108. I2S characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 190/234 Prerelease product(s)

6.3.36.5 SAI interface characteristics

Unless otherwise specified, the parameters given in Table 109 for SAI are derived from tests performed under the ambient temperature, frequency and supply voltage conditions summarized in Table 17. General operating conditions , with the following configuration:

  • Output speed is set to OSPEEDRy[1:0] = 10
  • Capacitive load C = 30 pF
  • Measurement points are performed at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS).

Table 109. SAI characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. APB clock frequency must be at least twice SAI clock frequency.

DS14285 - Rev 2 page 192/234 Prerelease product(s)

Figure 52. SAI master timing waveforms Figure 53. SAI slave timing waveforms

6.3.36.6 SD/SDIO MMC card host interface (SDMMC) characteristics

  • Output speed is set as table below
  • Capacitive load C = 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Table 110. SDMMC GPIO OSPEEDR settings for timing measurements DS14285 - Rev 2 page 193/234 Prerelease product(s)

Voltage range (V) Max clock frequency (MHz) OSPEEDRy[1:0] Clock Data 1.71 - 1.89 and 2.7 - 3.6 52/50 01 00 DDR 52/50 01 01 100 01 00 2.7 - 3.6 120 11 10 1.71 - 1.89 166 11 10 Table 111. SDMMC characteristics for SD-Card or SDIO usage Evaluated by characterization, not tested in production unless otherwise specified.

  1. SD-Card 3 V / 1.8 V support on SDMMC3 requires an external voltage translator for which timings should be taken into
  2. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 112. SDMMC characteristics for e•MMC usage Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 194/234 Prerelease product(s)

6.3.36.7 FDCAN (controller area network) interface

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX).

6.3.36.8 Ethernet (ETH) characteristics

Unless otherwise specified, the parameters given in Table 113, Table 114 and Table 115 for ETH interface are derived from tests performed under the ambient temperature, frequency and supply voltage conditions summarized in Table 17. General operating conditions, with the following configuration:

  • Output speed is set to OSPEEDRy[1:0] = 00 (MII or RMII timings), 11 (MDIO/SMA, RGMII or RGMII-ID timings)
  • Capacitive load C = 20 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Table 113. Ethernet MAC timings for MDIO/SMA Evaluated by characterization, not tested in production unless otherwise specified. Figure 57. Ethernet MDIO/SMA timing diagram Table 114. Ethernet MAC timings for RMII Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 196/234 Prerelease product(s)

Figure 58. Ethernet RMII timing diagram Table 115. Ethernet MAC timings for MII Evaluated by characterization, not tested in production unless otherwise specified. Figure 59. Ethernet MII timing diagram

6.3.36.9 USART (SPI mode) interface characteristics

  • Output speed is set to OSPEEDRy[1:0] = 11 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 197/234 Prerelease product(s)

  • Capacitive load C = 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART).

Table 116. USART (SPI mode) characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. tker is the usart_ker_ck_pres clock period defined in the product reference manual.

Figure 60. USART timing diagram in SPI master mode DS14285 - Rev 2 page 198/234 Prerelease product(s)

Figure 61. USART timing diagram in SPI slave mode

6.3.37 Embedded PHYs characteristics

6.3.37.1 DDR PHY characteristics

Table 117. DDR PHY characteristics Specified by design, not tested in production unless otherwise specified. DS14285 - Rev 2 page 199/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit DDR4, 2400 Mbps, 16‑bit, 10 ACx4, 1 Rank, DBI off IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Read - 93.5 160 mA Write - 115 190 Idle - 65 125 DFI_LP - 22 70 Inactive - 3.65 70 Retention(2) OFF IVDDA18DDR(1) Supply current on VDDA18DDR Read - 4.3 - mA Write - 4.3 - Idle - 4.3 - DFI_LP - 4.3 - Inactive - 0.12 0.16 Retention(2) OFF IVDDQDDR(1) Supply current on VDDQDDR Read - 235 275 mA Write - 180 215 Idle - 37 43 DFI_LP - 1.9 3.6 Inactive - 0.12 1.35 Retention(2) - 0.017 1.2 DDR3L, 2133 Mbps, 32‑bit, 10 ACx4, 1 Rank IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Read - 130 210 mA Write - 170 275 Idle - 76.5 150 DFI_LP - 25 86.5 Inactive - 3.6 60 Retention(2) OFF IVDDA18DDR(1) Supply current on VDDA18DDR Read - 4.3 - mA Write - 4.3 - Idle - 4.3 - DFI_LP - 4.3 - Inactive - 0.12 0.16 Retention(2) OFF IVDDQDDR(1) Supply current on VDDQDDR Read - 420 475 mA Write - 475 530 Idle - 71.5 79.5 DFI_LP - 3.25 5.85 Inactive - 0.135 2 Retention(2) - 0.0225 1.75 DDR3L, 2133 Mbps, 16‑bit, 10 ACx4, 1 Rank IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Read - 88.5 145 mAWrite - 110 175 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 200/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Idle mA - 62.5 115 DFI_LP - 21 62.5 Inactive - 3.6 60 Retention(2) OFF IVDDA18DDR(1) Supply current on VDDA18DDR Read - 4.3 - mA Write - 4.3 - Idle - 4.3 - DFI_LP - 4.3 - Inactive - 0.12 0.16 Retention(2) OFF IVDDQDDR(1) Supply current on VDDQDDR Read - 245 275 mA Write - 270 305 Idle - 39.5 44.5 DFI_LP - 2.15 3.85 Inactive - 0.135 1.4 Retention(2) - 0.0225 1.2 LPDDR4, 2400 Mbps, 32‑bit, 10 ACx4, 1 Rank, DBI off IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Read - 140 245 mA Write - 165 285 Idle - 73 160 DFI_LP - 25 99 Inactive - 3.65 70.5 Retention(2) OFF IVDDA18DDR(1) Supply current on VDDA18DDR Read - 4.3 - mA Write - 4.3 - Idle - 4.3 - DFI_LP - 4.3 - Inactive - 0.12 0.16 Retention(2) OFF IVDDQDDR(1) Supply current on VDDQDDR Read - 125 150 mA Write - 480 545 Idle - 49.5 57.5 DFI_LP - 2.6 4.85 Inactive - 0.11 1.75 Retention(2) - 0.0185 1.55 LPDDR4, 2400 Mbps, 16‑bit, 10 ACx4, 1 Rank, DBI off IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Read - 91 160 mA Write - 110 185 Idle - 59.5 120 DFI_LP - 22 70 Inactive - 3.65 70.5 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 201/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Retention(2) mAOFF IVDDA18DDR(1) Supply current on VDDA18DDR Read - 4.3 - mA Write - 4.3 - Idle - 4.3 - DFI_LP - 4.3 - Inactive - 0.12 0.16 Retention(2) OFF IVDDQDDR(1) Supply current on VDDQDDR Read - 110 125 mA Write - 285 325 Idle - 48.5 56 DFI_LP - 1.7 3.2 Inactive - 0.11 1.25 Retention(2) - 0.0185 1.1 Low power exit latency tEXIT Exit latency from DFI_LP state - - 2 - DFI_ CLK Exit latency from inactive state DDR3L, DDR4 - 3 - μs LPDDR4 - 3 + 2560 DDR_CL K Exit latency from retention state after supplies restored DDR3L, DDR4 - 3 - LPDDR4 - 3 + 2560 DDR_CL K 1. Evaluated by characterization, not tested in production. 2. VDDCORE OFF, VDDA18DDR OFF.

6.3.37.2 DSI PHY Characteristics

Table 118. DSI PHY characteristics Specified by design, not tested in production unless otherwise specified. DS14285 - Rev 2 page 202/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit IVDDA18DSI Supply current on VDDA18DSI(2) High-Speed Transmit(3) 4 lanes - 5.35 9.55 mALP Transmit Lane 0 @10 Mbps, PLL @2.5 Gbps - 3.85 5.05 ULPS Transmit PLL disabled - 0.0155 0.0385 IVDDDSI Supply current on VDDDSI High-Speed Transmit(3) 4 lanes @1Gbps - 14.5 19 mA 4 lanes @1.5 Gbps - 17 23 4 lanes @2 Gbps - 19.5 26.5 4 lanes @2.5 Gbps - 22.5 30 LP Transmit Lane 0 @10 Mbps, PLL @2.5 Gbps - 7.45 10.5 ULPS Transmit PLL disabled - 0.0505 0.805 1. Evaluated by characterization, not tested in production. 2. values includes PLL power consumption. 3. HS mode: assume PRBS9 pattern on data lanes and 100% occupation; that is, continuous HS.

6.3.37.3 CSI PHY Characteristics

Table 119. CSI PHY characteristics Specified by design, not tested in production unless otherwise specified.

  1. Evaluated by characterization, not tested in production.
  2. HS mode: assume PRBS9 pattern on data lanes and 100% occupation; that is, continuous HS.

DS14285 - Rev 2 page 203/234 Prerelease product(s)

6.3.37.4 LVDS PHY Characteristics

Table 120. LVDS PHY characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Steady state (~ DC level) @ lowest possible data rate (2 Mbps) with both voltage and current driver enabled.
  2. At maximum speed with both voltage and current driver enabled.
  3. Loading conditions are: two 50Ω resistors, two 2.5 pF caps at each output, one 2.5 pF cap at middle point.
  4. Specification for default configuration (no pre-emphasis).

6.3.37.5 USB2PHY Characteristics

Table 121. USB high-speed PHY characteristics Specified by design, not tested in production unless otherwise specified. DS14285 - Rev 2 page 204/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit IVDDCORE(USB2 PHY)(1) Supply current on VDDCORE Battery charging VDATDETENB = 0, VDATSRCENB = 1(9) mA - 2.4 11.5 VDATDETENB = 1, VDATSRCENB = 1 - 4.75 15.5 IVDDA18USB(1) Supply current on VDDA1V8USB HS transmit, maximum transition density(2) - 16.5 18.5 mA HS transmit, minimum transition density(3) - 14.5 15.5 HS idle(4) - 4.9 5.85 FS transmit, maximum transition density(5) - 4.9 5.9 LS transmit, maximum transition density(6) - 5.1 6.15 Suspend(7) - 0.024 0.0945 Sleep(8) - 0.031 0.0945 Battery charging VDATDETENB = 0, VDATSRCENB = 1(9) - 3.55 4.55 VDATDETENB = 1, VDATSRCENB = 1 - 4.3 5.4 IVDD33USB(1) Supply current on VDD33USB HS transmit, maximum transition density(2) - 3.05 3.2 mA HS transmit, minimum transition density(3) - 2.2 2.55 HS idle(4) - 2.1 2.4 FS transmit, maximum transition density(5) - 12.5 16 LS transmit, maximum transition density(6) - 12 16.5 Suspend(7) - 0.029 0.0785 Sleep(8) - 0.067 0.115 Battery charging VDATDETENB = 0, VDATSRCENB = 1(9) - 2.1 2.4 VDATDETENB = 1, VDATSRCENB = 1 - 2.1 2.4 1. Evaluated by characterization, not tested in production. 2. Packet transmission by one transceiver operating in device mode while driving all 0s data (constant JKJK on DP/DM). Loading of 10 pF. Transfers do not include any interpacket delay. 3. Packet transmission by one transceiver operating in device mode while driving all 1s data (alternating 7-bit strings of J, then K on DP/DM). Loading of 10 pF. Transfers do not include any interpacket delay. 4. HS receive mode with no traffic on the line. 5. Packet transmission by one transceiver operating in device mode while driving all 0s data (constant JKJK on DP/DM). Loading of 50 pF. Transfers do not include any interpacket delay. 6. Packet transmission by one transceiver operating in host mode while driving all 0s data (constant JKJK on DP/DM). Loading of 600 pF. Transfers do not include any interpacket delay. 7. Suspend when operating in device mode with no far-side host termination on DP/DM during measurements. Measurements taken when COMMONONN (SYSCFG_USB2PHYxCR.USB2PHYxCMN) is deasserted. 8. Sleep mode when operating in device mode with no far-side host termination on DP/DM during measurements. 9. PHY is in suspend (with clocks turned OFF), non-driving mode and operating as a portable device in the 'dead battery' condition.

6.3.37.6 COMBOPHY Characteristics

Table 122. COMBOPHY characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 205/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit IVDDCOMBOPHY Supply current on VDDCOMBOPHY P0 mode 5 Gbps - 23.5 38 mA 2.5 Gbps - 14 37.5 P0s mode 5 Gbps - 16.5 33

2.5 Gbps - 13 28

5 Gbps - 9.7 24.5 2.5 Gbps - 9.7 24.5 P1.CPM - - 1.45 14.5 P1.2 - - 0 12 P2 - - 9.6 15 P2.CPM - - 1.2 14 Power down - - 0.15 13 IVDDCOMBOPHYTX Supply current on VDDCOMBOPHYTX P0 mode

5 Gbps - 11 14

2.5 Gbps - 6.4 8.9 P0s mode 5 Gbps - 1.4 2.4 2.5 Gbps - 1.4 2.4 P1 mode 5 Gbps - 1.4 2.4 2.5 Gbps - 1.4 2.4 P1.1 - - 1.45 2.4 P1.2 - - 0.005 0.405 P2 - - 1.45 1.9 P2.CPM - - 0.005 0.41 Power down - - 0.01 0.425 IVDDA18COMBOPHY Supply current on VDDA18COMBOPHY P0 mode

5 Gbps - 25 29

2.5 Gbps - 17.5 24 P0s mode 5 Gbps - 14.5 20.5 2.5 Gbps - 14 19.5 P1 mode 5 Gbps - 8.4 11.5 2.5 Gbps - 8.4 11.5 P1.CPM - - 2.35 2.75 P1.1 - - 2.2 2.55 P1.2 - - 0.375 0.785 P2 - - 14 16.5 P2.CPM - - 0.54 0.985 Power down - - 0.01 0.0305 NFTS(1) Minimum number of FTS ordered sets that must be sent for retraining when transitioning from P0s to P0 48 - - FTS tP0s_to_P0 Time from pipe powerdown change to P0

5 Gbps - - 48

2.5 Gbps - - 96

tP1_to_P0 Time from pipe powerdown change to P0 5 Gbps - - 0.9 μs 2.5 Gbps - - 1.8 STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 206/234 Prerelease product(s)

Symbol Parameter Conditions Min Typ Max Unit tP2_to_P0 Time from pipe powerdown change to P0 100 MHz reference clock - - 260 μs tP0_to_P2 Time from pipe powerdown change to P2 - - - 250 ns tP2_to_P1 Time from pipe powerdown change to P1 100 MHz reference clock - - 255 μs tReset_to_ready Time from pipe reset de-assertion to PHY acknowledgment

100 MHz

tMPLL_lock Time from phy_mpll_en assertion to when phy_mpll_state is high reference clock - - 15 μs tResistor_tuning Time to complete a resistor tune - - - 8 - tCommon_mode Time to establish Common mode when exiting reset or P2 state - - 240 μs tP1.1_to_P1 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion - - 15 - tP1.2_to_P1 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion - - 15 μs tP1.2_to_P1_to_P0 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion and pipeN_powerdown request to P0 until PHY acknowledgment - - 16.8 - tP1.CPM_to_P1 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion - - 15 μs tCOMMON_MODE_REC Time for the Common mode voltage to be reached on pins while transmitting in Recovery mode. This parameter applies to an exit from P1.2 through P1 to P0 (Recovery) and represents the extra time in which the MAC is required to send TS1 ordered sets. - - 55 μs 1. Specified by design, not tested in production. Table 123. PCIE REFCLKGEN characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 207/234 Prerelease product(s)

Symbol(1) Parameter Conditions Min Typ Max Unit VSWING Singled ended swing in % of VDDPCIECLK IMP_CTRL[4:3] = 0b10010 - 87 - IMP_CTRL[4:3] = 0b11010 - 100 - IMP_CTRL[4:3] = 0b00011 - 70 - IMP_CTRL[4:3] = 0b01011 - 90 - IMP_CTRL[4:3] = 0b10011 - 80 - IMP_CTRL[4:3] = 0b11011 (default) - 100 - IMP_CTRL[4:3] = 0b00100 - 58 - IMP_CTRL[4:3] = 0b01100 - 70 - IMP_CTRL[4:3] = 0b10100 - 85 - IMP_CTRL[4:3] = 0b11100 - 100 - IMP_CTRL[4:3] = 0b00101 - 68 - IMP_CTRL[4:3] = 0b01101 - 79 - IMP_CTRL[4:3] = 0b10101 - 90 - IMP_CTRL[4:3] = 0b11101 - 100 - IMP_CTRL[4:3] = 0b00110 - 64 - IMP_CTRL[4:3] = 0b01110 - 76 - IMP_CTRL[4:3] = 0b10110 - 88 - IMP_CTRL[4:3] = 0b11110 - 100 - IMP_CTRL[4:3] = 0b00111 - 71 - IMP_CTRL[4:3] = 0b01111 - 80 - IMP_CTRL[4:3] = 0b10111 - 90 - IMP_CTRL[4:3] = 0b11111 - 100 - tr/tf Rise and Fall time(2) (3) (4) 0.6 - 4 V/ns ∆VCROSS Variation of VCROSS over all rising clock edges(5)(6)(8) - - 140 mV Duty_Cycle Duty cycle(2) 40 50 60 % Matching Rising edge rate to falling edge rate matching(5)(9) - - 20 % 2. PCIE_CLKOUTP and PCIE_CLKOUTN are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL = 2 pF. 3. Measured from -150 mV to +150 mV on the differential waveform (derived from PCIE_CLKOUTP minus PCIE_CLKOUTN). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. 4. Measurement taken from differential waveform. 5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 6. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIE_CLKOUTP equals the falling edge of PCIE_CLKOUTN. 7. Measurement taken from single ended waveform. 8. Defined as the total variation of all crossing voltages of rising PCIE_CLKOUTP and falling PCIE_CLKOUTN. This is the maximum allowed variance in VCROSS for any particular system. 9. Matching applies to rising edge rate for PCIE_CLKOUTP and falling edge rate for PCIE_CLKOUTN. It is measured using a ± 75 mV window centered on the median cross point where PCIE_CLKOUTP rising meets PCIE_CLKOUTN falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of PCIE_CLKOUTP should be compared to the fall edge rate of PCIE_CLKOUTN, the maximum allowed difference should not exceed 20% of the slowest edge rate. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D DS14285 - Rev 2 page 208/234 Prerelease product(s)

6.3.37.7 UCPDPHY Characteristics

Table 124. UCPDPHY characteristics Evaluated by characterization, not tested in production unless otherwise specified.

  1. Refer to the "USB Power Delivery (PD) Specification" Revision 3.1, Version 1.8.
  2. BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of
  3. Does not include pull-up or pull-down resistance from cable detect. Transmitter is Hi‑Z.

6.3.38 JTAG/SWD interface characteristics

  • Output speed is set to OSPEEDRy[1:0] = 01
  • Capacitive load C = 30 pF
  • Measurement points are done at CMOS levels: 0.5 × VDD
  • I/O compensation cell enabled
  • VDDxVRSEL activated when VDDx ≤ 2.7 V Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 209/234 Prerelease product(s)

Table 125. JTAG dynamic characteristics Evaluated by characterization, not tested in production unless otherwise specified. Figure 62. JTAG timing diagram Table 126. SWD dynamic characteristics Evaluated by characterization, not tested in production unless otherwise specified. DS14285 - Rev 2 page 210/234 Prerelease product(s)

Figure 63. SWD timing diagram DS14285 - Rev 2 page 211/234 Prerelease product(s)

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors" (TN1433 ) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1. Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

7.2 VFBGA361 package information (B09U)

This VFBGA is a 361-ball, 10 x 10 mm, very thin fine pitch ball grid array package. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Package information

DS14285 - Rev 2 page 212/234 Prerelease product(s)

Figure 64. VFBGA361 - Outline DS14285 - Rev 2 page 213/234 Prerelease product(s)

Table 127. VFBGA361 - Mechanical data

  1. Values in inches are converted from mm and rounded to 4 decimal digits.
  2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
  3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
  4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum C.
  5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to form
  6. e(x) represents the solder ball grid pitch(es).
  7. N represents the total number of balls on the BGA.
  8. Basic dimensions SD(x) & SE(y) are defined with respect to datums A and B. They define the position of the centre ball(s) of
  9. Tolerance of form and position drawing.

7.3 VFBGA424 package information (B0MP)

This VFBGA is a 424-ball, 14 x 14 mm, very thin fine pitch ball grid array package. DS14285 - Rev 2 page 214/234 Prerelease product(s)

Figure 65. VFBGA424 - Outline

  1. Primary datum C is defined by the plane established by the contact points of three or more solder balls that

support the device when it is placed on top of a planar surface. DS14285 - Rev 2 page 215/234 Prerelease product(s)

  1. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heat slug. A distinguish feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

Table 128. VFBGA424 - Mechanical data

  1. Values in inches are converted from mm and rounded to 4 decimal digits.
  2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
  3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
  4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum C.
  5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to form
  6. e(x) represents the solder ball grid pitch(es).
  7. N represents the total number of balls on the BGA.
  8. Basic dimensions SD(x) & SE(y) are defined with respect to datums A and B. They define the position of the centre ball(s) of
  9. Tolerance of form and position drawing.

7.4 TFBGA436 package information (B0MS)

This TFBGA is a 436-ball, 18 x 18 mm, thin fine pitch ball grid array package. DS14285 - Rev 2 page 216/234 Prerelease product(s)

Figure 66. TFBGA436 - Outline

  1. Primary datum C is defined by the plane established by the contact points of three or more solder balls that

support the device when it is placed on top of a planar surface.

  1. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer,

DS14285 - Rev 2 page 217/234 Prerelease product(s)

Table 129. TFBGA436 - Mechanical data

  1. Values in inches are converted from mm and rounded to 4 decimal digits.
  2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
  3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
  4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum C.
  5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to form
  6. e(x) represents the solder ball grid pitch(es).
  7. N represents the total number of balls on the BGA.
  8. Basic dimensions SD(x) & SE(y) are defined with respect to datums A and B. They define the position of the centre ball(s) of
  9. Tolerance of form and position drawing.

Figure 67. TFBGA436 - Footprint example DS14285 - Rev 2 page 218/234 Prerelease product(s)

Table 130. TFBGA436 - Example of PCB design rules

7.5 Package thermal characteristics

  • TA max is the maximum ambient temperature in °C.
  • ΘJA is the package junction-to-ambient thermal resistance in °C/W.
  • PD max is the sum of PINT max and PI/O max: P D max = P I NT max + P I / O max
  • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins: P I / O max = V OL × I OL + V DDI O x − V OH × I OH taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.

Table 131. Package thermal characteristics

7.5.1 Reference documents

  • JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) available on www.jedec.org.
  • For information on thermal management, refer to application note "Guidelines for thermal management on STM32 applications" (AN5036) available on www.st.com. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

DS14285 - Rev 2 page 219/234 Prerelease product(s)

8 Ordering information

Example: STM32 MP 257 D AI 3 ␣ T Device family STM32 = Arm® -based 32- or 64-bit processor Product type MP = MPU product Device subfamily 251 = STM32MP251 line 253 = STM32MP253 line 255 = STM32MP255 line 257 = STM32MP257 line Security option A = Basic security, 1.2 GHz CPU1, 800 MHz GPU (1) D = Basic security, 1.5 GHz CPU1, 900 MHz GPU (1) Package and ball count AL = VFBGA361 10x10, 361 balls pitch 0.5 mm AK = VFBGA424 14x14, 424 balls pitch 0.5 mm AI = TFBGA436 18x18, 436 balls pitch 0.8 mm Junction temperature range Options ␣ (absent) = no options Packing T = Tape and reel No character = tray or tube 1. GPU is absent in some devices (see Section 2 for details). Note: For a list of available options (such as speed and package) or for further information on any aspect of this device, contact your nearest ST sales office. STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Ordering information

DS14285 - Rev 2 page 220/234 Prerelease product(s)

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

  • ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
  • Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
  • Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
  • While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
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Revision history

Table 132. Document revision history 19-Mar-2024 1 Initial release. per packages and Figure 1. STM32MP25xA/D block diagram. Updated Section 3.4: Graphic processing unit (GPU). Updated Section 3.7: DDR3L/DDR4/LPDDR4 controller (DDRCTRL). Updated Table 5. Boot sources. Updated Section 3.34: Digital camera interface with pixel processing (DCMIPP). Updated Section 3.36: LCD-TFT display controller (LTDC). Updated Section 3.38: LVDS display interface (LVDS). Updated Table 8. USART/UART features. Updated Table 19. Embedded reset and power control block characteristics. Updated Table 20. Embedded reference voltage characteristics. Updated Table 21. Embedded reference voltage calibration value. Updated Table 35. D1 (CPU1) low-power mode wakeup timings. Updated Table 36. D2 (CPU2) low-power mode wakeup timings. Updated Table 43. Low-speed external (LSE) oscillator characteristics. Updated Table 47. MSI oscillator characteristics. Updated Table 48. LSI oscillator characteristics. Updated Table 49. PLL1 to PLL8 characteristics. Updated Table 62. Output voltage characteristics for all I/Os. Updated Table 79. Synchronous multiplexed PSRAM write timings. Updated Figure 29. NAND controller waveforms for read access. Updated Figure 30. NAND controller waveforms for write access. Updated Table 86. ADC characteristics. Updated Table 87. ADC accuracy. Updated Table 89. VREFBUF characteristics. VDDGPU, PVD_IN, VDDA18ADC, VDDIO1/2/3/4, VDD33USB, VDD33UCPD). Updated Table 94. Compensation cell characteristics. Table 95. MDF characteristics. Table 96. ADF characteristics.

Table 97. DCMI characteristics. Updated Section 6.3.32: Camera interface (DCMIPP) characteristics. Table 99. PSSI transmit characteristics and Table 100. PSSI receive analog filter characteristics. Table 113. Ethernet MAC timings for MDIO/SMA, Table 114. Ethernet MAC timings for RMII, Table 115. Ethernet MAC timings for MII. Table 116. USART (SPI mode) characteristics. Updated Section 6.3.37.2: DSI PHY Characteristics. Updated Section 6.3.37.4: LVDS PHY Characteristics. Updated Table 121. USB high-speed PHY characteristics. Updated Table 122. COMBOPHY characteristics. Table 125. JTAG dynamic characteristics and Table 126. SWD dynamic Updated Section 7.5: Package thermal characteristics.

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Contents

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3.53 Serial peripheral interface (SPI1/2/3/4/5 /6/7/8) inter-integrated sound interfaces

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Table 93. Voltage monitoring characteristics (VDDCORE, VDDCPU, VDDGPU, PVD_IN, VDDA18ADC, VDDIO1/2/3/4, VDD33USB,

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