TFBGA243

SAM9X75-SIP MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 36

Technical content

Features

• CPU Running up to 800 MHz – ARM926EJ-S Arm Thumb ® processor – 32-Kbyte data cache, 32-Kbyte instruction cache, Memory Management Unit (MMU)
• Memories – One 176-Kbyte internal ROM
• 80-Kbyte internal ROM embedding a secure bootloader program supporting boot on NAND Flash, SD Card, SPI or QSPI Flash; bootloader features selectable by OTP bits
• 96-Kbyte ROM for NAND Flash BCH ECC table – One 64-Kbyte internal SRAM (SRAM0), single cycle access at system speed – Internal DDR3L SDRAM running at up to 266 MHz – External Bus Interface (EBI) supporting:
• 8-bit NAND Flash with up to 24-bit programmable multi-bit error correcting code – One 10-Kbyte OTP memory for secure key storage with Emulation mode (OTP bits are emulated by a 4-Kbyte SRAM (SRAM1))
• System Running up to 266 MHz SAM9X75 System-in-Package (SiP) MPU with 1‑Gbit or 2‑Gbit DDR3L SDRAM SAM9X75 SiP

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 2 – Power-on reset cells, reset controller, shutdown controller, periodic interval timer, watchdog timer running on internal slow RC oscillator (32 kHz typical) and real-time clock running on slow crystal oscillator (32.768 kHz) – Two internal trimmed RC oscillators with typical values: 32 kHz (slow) and 12 MHz (fast) – Two crystal oscillators: 32.768 kHz (slow) and 20 to 50 MHz (fast) – One PLL for the system and one PLL optimized for USB high-speed operation (480 MHz)

• One PLL for audio operations, with dedicated output clock
• One PLL in LVDS I/F (LVDS usage only)
• One PLL in MIPI DPHY (MIPI DSI usage only) – One dual-port 16-channel DMA controller – Advanced interrupt controller and debug unit – JTAG port with disable bit in OTP memory – Two programmable clock output signals
• Low-Power Modes – Backup mode with RTC, eight 32-bit general purpose backup registers, and shutdown controller to control the external power supply – Clock generator and power management controller – Software-programmable ultra-low power modes: very slow clock operating mode (ULP0) and no-clock operating mode (ULP1) with fast wake-up capabilities – Software programmable power optimization capabilities
• Peripherals – LCD controller with overlay, alpha blending, rotation, scaling and color conversion; up to 720p resolution
• RGB, LVDS, MIPI-DSI interfaces – 2D graphics controller supporting fill BLT, copy BLT, transparent BLT, blend/alpha BLT, ROP4 BLT (raster operations) and command ring buffer – Image sensor controller with ITU-R BT; 601/656/1120 video interface support up to 5 Mpixels; support of raw Bayer 12, YCbCr, monochrome and JPEG compressed sensors up to 12 bits
• MIPI CSI2 I/F support
• 12-bit parallel I/F support – One high-speed USB device, three high-speed USB hosts with dedicated on-chip transceivers – One 10/100/1000 Mbps Ethernet Mac controller with IEEE-1588 and TSN support, RGMII and RMII support – Two 4-bit secure digital multimedia card controllers – Two CAN FD controllers with timestamping – One Quad/Octal SPI controller – Two 3-channel 32-bit timers/counters – Two high-resolution (64-bit) periodic interval timers – One synchronous serial controller – One inter-IC sound multi-channel controller with TDM support – One audio class D controller with single-ended or bridge-tied load connection to power stage – One 4-channel 16-bit PWM controller – Thirteen FLEXCOMs (USART, SPI and TWI/I2C) – One 8-channel, 12-bit, analog-to-digital converter with 4/5 wires resistive touchscreen support

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 3

• Hardware Cryptography – SHA (SHA1, SHA224, SHA256, SHA384, SHA512) and HMAC compliant with FIPS PUB 180 – AES: 256-, 192-, 128-bit key algorithms compliant with FIPS PUB 197 – AES/SHA tight coupling for IPsec hardware acceleration – TDES: 2-key or 3-key algorithms compliant with FIPS PUB 46 – True random number generator compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3 – Key bus providing private key transfers between AES, TDES, TRNG, OTPC – Physical Unclonable Function (PUF) including NIST SP 800-90B (DRNG) and embedding four Kbytes of SRAM (PUFSRAM)
• I/O Ports – Four 32-bit parallel input/output controllers – Up to 106 programmable I/O lines multiplexed with up to four peripheral I/Os – Input change interrupt capability on each I/O line, optional Schmitt trigger input – Individually programmable open-drain, pull-up and pull-down resistors, synchronous output – General-purpose analog and digital inputs tolerant to positive and negative current injection
• Package – 16x16 mm 2, 0.8-mm pitch, 243-ball BGA optimized for standard class PCB layout (down to four layers)
• Design for low ElectroMagnetic Interference (EMI) – Slewrate-controlled I/Os – DDR PHY with impedance-calibrated drivers – Spread spectrum PLLs – BGA power/ground ball assignment to provide optimum decoupling capacitors placement
• Operating Conditions – Junction temperature (T J) range: -40°C to +125°C – Ambient temperature (T A) range: -40°C to +85°C

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 4 1. DDR3L SDRAM Features The SAM9X75 SiP is available with 1-Gbit and 2-Gbit DDR3L SDRAM memory options. For power consumption, electrical characteristics and timings of these memories, refer to the manufacturer’s documentation listed in Reference Documents.

• Power supply: DDRM_VDD = 1.283V to 1.45V
• 2-Kbyte page size (x16)
• 8-bank operation controlled by BA0, BA1 and BA2
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• Precharge: auto-precharge option for each burst access
• Auto-Refresh and Self-Refresh modes
• Average refresh period: – 7.8 µs at t J ≤ +85°C – 3.9 µs at t J ≤ +105°C – 1.95 µs at t J ≤ +125°C
• High-speed data transfer realized by the 8-bit prefetch pipelined architecture
• Double Data Rate architecture: two data transfers per clock cycle
• Bidirectional differential data strobe (DQS and /DQS) transmitted/received with data for capturing data at the receiver
• DQS edge-aligned with data for reads and center-aligned with data for writes
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted CAS by programmable additive latency for better command and data bus efficiency
• MultiPurpose Register (MPR) for predefined pattern read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• Reset pin for power-up sequence and reset function
• Self-Refresh Temperature (SRT) range: normal/extended
• Automatic Self-Refresh (ASR)
• Programmable output driver impedance control

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 5 2. Con figur ation Summary Feature SAM9X75D1G SAM9X75D2G EBI 8-bit NAND Flash controller SDRAM embedded in SiP 1-Gbit DDR3L SDRAM 2-Gbit DDR3L SDRAM MIPI DPHY Bidirectional, 4 lanes PIOs 106 SRAM0/SRAM1 64/4 Kbytes Quad/Octal SPI 1 LCD + GFX2D LVDS, MIPI DSI, RGB interface Camera interface (ISC) MIPI CSI2, parallel port GMAC 10/100/1000 with IEEE 1588 and TSN CAN-FD 2 USB 3 (3 hosts or 2 host/1 device) UART/SPI/I2C 13 SDIO/SD/MMC 2 I2SMCC/SSC/Class D 1/1/1 ADC inputs 8 (8 channels) 64-bit timers/32-bit timers 2/6 PWM 4 (PWMC) Cryptography AES/TDES/SHA/TRNG

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 6 3. Block Diagram SAM9X75 SiP In-Circuit Emulator ARM926EJ-S DCache 32 KB ICache 32 KB MMU Bus Interface Unit Key Digital Analog Memories, bridges PIO Backup area Processor and crypto-accelerators H Matrix host C Matrix client HH C C C C H H H H H H H H Multi- Layer System Matrix C C C C I D ROM (96 KB + KB) OTP Memory (32 KB) USB HOST HS EHCI FS OHCI PC PB PA DMA HS T rans HS T rans HS T ransHS USB DMA DHSDP /HHSDPA DHSDM/HHSDMA HHSDPB HHSDMB HHSDPC HHSDMC PIO NANDALE, NANDCLE NANDOE, NANDWE NANDDAT[7:0] NANDRDY NANDCS EBI PMECC PMERRLOC MPDDRC PWM 9-b ADC 12-Ch. PIO CAN [1:0] (x2) IS DMA XLCDC DMA GMAC (TSN) DMA GTXCK/GREFCK GTXEN/GTXCTL GTX[3:0] GRX[3:0] GRXER/GRXCTL, GCRSDV GMDIO, GMDC, GTSUCOMP DMA SDMMCx_CMD SDMMCx_CK SDMMCx_DA T[3:0] GFX2D DMA QSPI QSCK QCS QIO[7:0] Peripheral Bridge APB1 - MCKAPB0 - MCK PWM[3:0] CANTXx CANRXx AD[7:0] ADVREFP , ADVREFN Peripheral Bridge PIO JTAG Boundary Scan JT AGSEL TMS, TCK TDI TDO, R TCK TC [5:0] (x6) TIOAx, TIOBx TCLKx PIO PIO A – D AICDBGU PMCWDT GPBR RT C / RT T RSTC SHDWC PLLA UTMI PLL Slow RC Osc. 32768 Hz Xtal Osc. XIN32 XOUT32 Main RC Osc. Main Xtal Osc. XIN XOUT Clock Generator VDDCORE POR VDDBU POR VDDOSC POR VDDPLL REG PCK[1:0] FIQ IRQ SHDN WKUP NRST Clock Sources System Clocks DTXDDRXD System Controller FLEXCOM 0,1,2,3 6,7,8,9,10 9FLEXCOMx_IO[2:0] FLEXCOMx_IO[6:3] H OTPC C SRAM1 (4 kB) H H XDMA TRNG TDES AES SHASSCRF , RK RD TD TF , TK CLASSD CLASSD_L[3:0] CLASSD_R[3:0] I2SMCC I2SMCC_MCK, I2SMCC_ DOUT I2SMCC_WS, I2SMCC_CK I2SMCC_DIN RTUNE NTRST PIO NRST_OUT C SRAM0 (64 kB) PUFSRAM (4 kB) PIT64B (x2) LVDS serializer D-PHY CSI2 DSI PUF LCDC_DISP, LCDC_PWM LCDC_VSYNC, LCDC_HSYNC LCDC_DAT[23:0] LCDC_PCLK, LCDC_EN ISC_MCK ISC_HSYNC, ISC_VSYNC ISC_PCK ISC_D[11:0] NAND ISC_FIELD LVDS_A[3:0]P LVDS_A[3:0]M DQS QINT Audio PLL AUDIOCLK G125CK, GRXCK FLEXCOM 4,5,11,12 4FLEXCOMx_IO[2:0] FLEXCOMx_IO[6:3] LVDSPLL DDR_ZQ DDR_VREF DDRM_ZQ GND LVDS_CLK1M/P MIPI_DN[3:0]/DP[3:0] MIPI_CLKN/P SDMMC [2:0] (x2) DDRM_VDD MIPI_REXT DDR3L SDRAM

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 7 4. Chip Identifier Table 4-1. Chip ID and Extended ID De finition Chip Name CHIPID_CIDR CHIPID_EXID SAM9X75D1G 0x89750030 0x00000018 SAM9X75D2G 0x00000020

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 8 5. Package and Pinout 1-Gbit and 2-Gbit SAM9X75 SiP devices are pin-to-pin compatible. Package Name Ball Count Ball Pitch Package Size TFBGA243 243 0.8 mm 16 x 16 (mm) For further details, see Mechanical Characteristics.

5.1 TFBGA243 Package

Figure 5-1. 243-Ball TFBGA Pinout L K J H G F E D C 1 2 3 4 5 6 7 8 9 10 11 PC4 GND PD1 HHS DMA HHS DMB HHS DPA HHS DPB HHS DMC HHSR TUNE HHS DPC PC0 PC2A B PC27 PC13 PC19 PC28 PC26 PC1 NRST PC15 AUDIO CLK VDD IN33 PC7 PC11 PD5 PD4 PD3 PD8 GND PD2 PA7 GND PA3 PA2 12 13 14 15 16 Power Ground Analog signals PA8 PA0 PD13 XOUT T R P N M XIN SHDN GND PB19 PB16 PB14 GND PB13 PB4 MIPI _CLKN GND TST U XOUT XIN WKUP0 PA12 PA17 JTAG SEL PA18 PA16 PA14 GND PB0 PB3 PA21 PB1 PA20 PC29 PC24 PC22 PC18 VDD IOP1 VDD IOP2 PD14 PB26 PA5 PB18 PA9 PD9 GND GND PC14 PC16 PC20 PC17 PC31PC21 VDD ANA GND PB17 PA11 PB23 VDD CORE PC23 PC5 PC8 PC3 PC9 PD0 PC30 GND ANA ADV REFP PD7 GND PB24 PA1PB11 GND PD6 VDD CORE PB25 PA10 GND PB21 PB20 PA6 PA4 GND PB22 PD10 VDD IOM PB15 VDD QSPI MIPI _CLKP GND VDD CORE MIPI _DP0 PB9 PB10PD12 GND VDD BU PA23 GND MIPI _DN0 MIPI _REXT MIPI _DN1 MIPI _DP1 PB2 PB6 PB8 GND VDD LVDS VDD MIPI VDD IOP0 VDD CORE VDD CORE GND PA19PB5 PB7 PA15 VDD IN25 VDD CORE VDD CORE PA22 DDR VREF GND PA13 GND GND PD11 GND L K J H G F E D C A B T R P N M U L K J H G F E D C A B T R P N M U GND GND GND GND GND GND GND GND GND GND GND GND GND GND DDRM_ VDD GND GND GND GND GND GND PC6 PC10 PC12 GND GND GND DDRM_ VDD GND DDRM_ VDDGND DDRM_ VDD PC25 GND GND DDRM_ VDD GND DDRM_ VDDGND DDRM_ VDD GND DDRM_ VDD GND DDRM_ VDDGND DDRM_ VDD DDRM_ VDD DDRM_ VDD GND GNDGND GND DDRM_ VDD GND DDRM_ VDDGND DDRM_ VDD DDRM_ VDD GND DDRM_ VDDGND DDRM_ VDD MIPI _DN2 MIPI _DP2 VDD IOM GND GND GND VDD IOM MIPI _DN3 MIPI _DP3 PB12 VDD OUT25 VDD IN33 VDD NF VDD IOM TDI RTCK TDO ADV REFN TCK TMS PA30 PA25 PA27 PA31 PA26 PA24 PA29 PA28 DDR CAL DDRM CAL

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 9

5.2 Ball Description

Table 5-1. Ball Description BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER H17 VDDIOP0 GPIO PA0 I/O – – A SDMMC0_DAT0 I/O 1 PIO, I, PU, ST T9 VDDIOP0 GPIO PA1 I/O – – A SDMMC0_CMD I/O 1 PIO, I, PU, ST K17 VDDIOP0 GPIO PA2 I/O WKUP1 – A SDMMC0_CK I/O 1 PIO, I, PU, ST P16 VDDIOP0 GPIO PA3 I/O – – A SDMMC0_DAT1 I/O 1 PIO, I, PU, ST J17 VDDIOP0 GPIO PA4 I/O – – A SDMMC0_DAT2 I/O 1 PIO, I, PU, ST L13 VDDIOP0 GPIO PA5 I/O – – A SDMMC0_DAT3 I/O 1 PIO, I, PU, ST L17 VDDIOP0 GPIO PA6 I/O – – A FLEXCOM0_IO4 O 1 PIO, I, PU, STB SDMMC1_DAT1 I/O 1 T7 VDDIOP0 GPIO PA7 I/O WKUP2 – A FLEXCOM0_IO3 I/O 1 PIO, I, PU, STB SDMMC1_DAT2 I/O 1 G17 VDDIOP0 GPIO PA8 I/O WKUP3 – A FLEXCOM0_IO2 I/O 1 PIO, I, PU, STB SDMMC1_DAT3 I/O 1 T11 VDDIOP0 GPIO PA9 I/O – – A FLEXCOM4_IO1 I/O 1,2 PIO, I, PU, STB SDMMC1_DAT0 I/O 1 M16 VDDIOP0 GPIO PA10 I/O – – A FLEXCOM4_IO0 I/O 1,2 PIO, I, PU, STB SDMMC1_CMD I/O 1 L14 VDDIOP0 GPIO PA11 I/O – – A FLEXCOM4_IO2 I/O 1,2 PIO, I, PU, STB SDMMC1_CK I/O 1 R5 VDDIOP0 GPIO PA12 I/O – – A FLEXCOM4_IO3 I/O 1,2 PIO, I, PU, STC FLEXCOM5_IO4 O 1 U11 VDDIOP0 GPIO PA13 I/O – – A FLEXCOM2_IO0 I/O 1 PIO, I, PU, STB FLEXCOM4_IO4 O 1 T5 VDDIOP0 GPIO PA14 I/O – – A FLEXCOM2_IO1 I/O 1 PIO, I, PU, STB FLEXCOM5_IO3 I/O 1,2 C FLEXCOM4_IO5 O 1 T10 VDDIOP0 GPIO PA15 I/O – – A TIOA0 I/O 1 PIO, I, PU, STB FLEXCOM5_IO1 I/O 1,2 C CLASSD_R0 O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 10 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER U8 VDDIOP0 GPIO PA16 I/O – – A TIOA1 I/O 1 PIO, I, PU, STB FLEXCOM5_IO0 I/O 1,2 C CLASSD_R1 O 1 P17 VDDIOP0 GPIO PA17 I/O – – A TIOA2 I/O 1 PIO, I, PU, STB FLEXCOM5_IO2 I/O 1,2 C CLASSD_R2 O 1 R17 VDDIOP0 GPIO PA18 I/O – – A TCLK0 I 1 PIO, I, PU, STB TK I/O 1 C CLASSD_L0 O 1 N17 VDDIOP0 GPIO PA19 I/O – – A TCLK1 I 1 PIO, I, PU, STB TF I/O 1 C CLASSD_L1 O 1 U7 VDDIOP0 GPIO PA20 I/O WKUP4 – A TCLK2 I 1 PIO, I, PU, STB TD O 1 C CLASSD_L2 O 1 R16 VDDIOP0 GPIO PA21 I/O – – A TIOB0 I/O 1 PIO, I, PU, STB RD I 1 C CLASSD_L3 O 1 U10 VDDIOP0 GPIO PA22 I/O – – A TIOB1 I/O 1 PIO, I, PU, STB RK I/O 1 C CLASSD_R3 O 1 U9 VDDIOP0 GPIO PA23 I/O – – A TIOB2 I/O 1 PIO, I, PU, STB RF I/O 1 C FLEXCOM2_IO7 I 1 R4 VDDANA GPIO PA24 I/O AD0 – A FLEXCOM6_IO0 I/O 1 PIO, I, PU, STB FLEXCOM5_IO6 O 1 R2 VDDANA GPIO PA25 I/O AD1 – A FLEXCOM6_IO1 I/O 1 PIO, I, PU, STB FLEXCOM5_IO5 O 1 N4 VDDANA GPIO PA26 I/O AD2 – A DRXD I 1 PIO, I, PU, STB CANRX0 I 1 T1 VDDANA GPIO PA27 I/O AD3 – A DTXD O 1 PIO, I, PU, STB CANTX0 O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 11 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER T4 VDDANA GPIO PA28 I/O AD4 – A FLEXCOM1_IO0 I/O 1 PIO, I, PU, STB CANTX1 O 1 L5 VDDANA GPIO PA29 I/O AD5 – A FLEXCOM1_IO1 I/O 1 PIO, I, PU, STB CANRX1 I 1 T3 VDDANA GPIO PA30 I/O AD6 – A FLEXCOM0_IO0 I/O 1 PIO, I, PU, STB FLEXCOM5_IO4 O 2 C FLEXCOM4_IO4 O 2 R1 VDDANA GPIO PA31 I/O AD7 – A FLEXCOM0_IO1 I/O 1 PIO, I, PU, STB FLEXCOM4_IO5 O 2 C GTSUCOMP O 1 G16 VDDIOP2 GPIO PB0 I/O WKUP5 – A GRX2 I 1 PIO, I, PU, STB FLEXCOM2_IO4 O 1 C GRXER I 1 L15 VDDIOP2 GPIO PB1 I/O – – A GRX3 I 1 PIO, I, PU, STB FLEXCOM2_IO3 I/O 1 H16 VDDIOP2 GPIO PB2 I/O – – A G125CK I 1 PIO, I, PU, STB FLEXCOM2_IO2 I/O 1 R8 VDDIOP2 GPIO PB3 I/O WKUP6 – A GCRSDV/GRXCTL I 1 PIO, I, PU, STB FLEXCOM4_IO6 O 1 J16 VDDIOP2 GPIO PB4 I/O – – A GTX2 O 1 PIO, I, PU, STB FLEXCOM8_IO0 I/O 1 N15 VDDIOP2 GPIO PB5 I/O – – A GTX3 O 1 PIO, I, PU, STB FLEXCOM8_IO1 I/O 1 F16 VDDIOP2 GPIO PB6 I/O – – A GTXCK/GREFCK I/O 1 PIO, I, PU, STB FLEXCOM0_IO7 I 1 R13 VDDIOP2 GPIO PB7 I/O – – A GTXEN/GTXCTL O 1 PIO, I, PU, STC FLEXCOM6_IO2 I/O 1 D17 VDDIOP2 GPIO PB8 I/O – – A GRXCK I 1 PIO, I, PU, STC FLEXCOM6_IO3 I/O 1 R14 VDDIOP2 GPIO PB9 I/O – – A GMDIO I/O 1 PIO, I, PU, STB PCK1 O 1 C FLEXCOM6_IO4 O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 12 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER K16 VDDIOP2 GPIO PB10 I/O – – A GMDC O 1 PIO, I, PU, STB PCK0 O 1 C FLEXCOM8_IO2 I/O 1 T8 VDDIOP2 GPIO PB11 I/O – – A GRX0 I 1 PIO, I, PU, STB PWM0 O 2 C FLEXCOM8_IO3 I/O 1 L16 VDDIOP2 GPIO PB12 I/O – – A GRX1 I 1 PIO, I, PU, STB PWM1 O 2 C FLEXCOM8_IO4 O 1 N16 VDDIOP2 GPIO PB13 I/O – – A GTX0 O 1 PIO, I, PU, STB PWM2 O 2 E17 VDDIOP2 GPIO PB14 I/O – – A GTX1 O 1 PIO, I, PU, STB PWM3 O 2 C7 VDDQSPI GPIO PB15 I/O – – A QIO5 I/O 1 PIO, I, PU, STC FLEXCOM11_IO0 I/O 1 D I2SMCC_WS I/O 1 A11 VDDQSPI GPIO PB16 I/O – – A QIO6 I/O 1 PIO, I, PU, STC FLEXCOM11_IO1 I/O 1 D I2SMCC_DIN0 I 1 A10 VDDQSPI GPIO PB17 I/O – – A QIO7 I/O 1 PIO, I, PU, STC FLEXCOM12_IO0 I/O 1 D I2SMCC_DOUT0 O 1 C10 VDDQSPI GPIO PB18 I/O WKUP7 – A QDQS I 1 PIO, I, PU, STB ADTRG I 1 C FLEXCOM12_IO1 I/O 1 D IRQ I 1 A9 VDDQSPI GPIO PB19 I/O – – A QSCK O 1 PIO, I, PU, STC FLEXCOM12_IO2 I/O 1 B11 VDDQSPI GPIO PB20 I/O – – A QCS O 1 PIO, I, PU, STC FLEXCOM12_IO3 I/O 1 B9 VDDQSPI GPIO PB21 I/O – – A QIO0 I/O 1 PIO, I, PU, STC FLEXCOM12_IO4 O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 13 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER D10 VDDQSPI GPIO PB22 I/O – – A QIO1 I/O 1 PIO, I, PU, STC FLEXCOM9_IO2 I/O 1 C8 VDDQSPI GPIO PB23 I/O – – A QIO2 I/O 1 PIO, I, PU, STC FLEXCOM9_IO3 I/O 1 B10 VDDQSPI GPIO PB24 I/O – – A QIO3 I/O 1 PIO, I, PU, STC FLEXCOM9_IO4 O 1 D8 VDDQSPI GPIO PB25 I/O WKUP8 – A QINT I 1 PIO, I, PU, STD I2SMCC_MCK O 1 C11 VDDQSPI GPIO PB26 I/O – – A QIO4 I/O 1 PIO, I, PU, STD I2SMCC_CK I/O 1 G2 VDDIOP1 GPIO PC0 I/O – – A LCDC_DAT0 O 1 PIO, I, PU, STB ISC_D0 I 1 C FLEXCOM7_IO0 I/O 1 H4 VDDIOP1 GPIO PC1 I/O – – A LCDC_DAT1 O 1 PIO, I, PU, STB ISC_D1 I 1 C FLEXCOM7_IO1 I/O 1 A3 VDDLVDS GPIO PC2 I/O LVDS_A0M – A LCDC_DAT2 O 1 PIO, I, PU, STB ISC_D2 I 1 C TIOA3 I/O 1 B3 VDDLVDS GPIO PC3 I/O LVDS_A0P – A LCDC_DAT3 O 1 PIO, I, PU, STB ISC_D3 I 1 C TIOB3 I/O 1 A4 VDDLVDS GPIO PC4 I/O LVDS_A1M – A LCDC_DAT4 O 1 PIO, I, PU, STB ISC_D4 I 1 C TCLK3 I 1 B4 VDDLVDS GPIO PC5 I/O LVDS_A1P – A LCDC_DAT5 O 1 PIO, I, PU, STB ISC_D5 I 1 C TIOA4 I/O 1 A5 VDDLVDS GPIO PC6 I/O LVDS_A2M – A LCDC_DAT6 O 1 PIO, I, PU, STB ISC_D6 I 1 C TIOB4 I/O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 14 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER B5 VDDLVDS GPIO PC7 I/O LVDS_A2P – A LCDC_DAT7 O 1 PIO, I, PU, STB ISC_D7 I 1 C TCLK4 I 1 G1 VDDIOP1 GPIO PC8 I/O – – A LCDC_DAT8 O 1 PIO, I, PU, STB ISC_D8 I 1 C FLEXCOM9_IO0 I/O 1 H3 VDDIOP1 GPIO PC9 I/O – – A LCDC_DAT9 O 1 PIO, I, PU, STB ISC_D9 I 1 C FLEXCOM9_IO1 I/O 1 A7 VDDLVDS GPIO PC10 I/O LVDS_CLK1 M – A LCDC_DAT10 O 1 PIO, I, PU, STB ISC_D10 I 1 C PWM0 O 3 B7 VDDLVDS GPIO PC11 I/O LVDS_CLK1P – A LCDC_DAT11 O 1 PIO, I, PU, STB ISC_D11 I 1 C PWM1 O 3 A8 VDDLVDS GPIO PC12 I/O LVDS_A3M – A LCDC_DAT12 O 1 PIO, I, PU, STB ISC_PCK I 1 C TIOA5 I/O 1 B8 VDDLVDS GPIO PC13 I/O LVDS_A3P – A LCDC_DAT13 O 1 PIO, I, PU, STB ISC_VSYNC I 1 C TIOB5 I/O 1 F2 VDDIOP1 GPIO PC14 I/O – – A LCDC_DAT14 O 1 PIO, I, PU, STB ISC_HSYNC I 1 C TCLK5 I 1 E3 VDDIOP1 GPIO PC15 I/O – – A LCDC_DAT15 O 1 PIO, I, PU, STB ISC_MCK O 1 C PCK0 O 2 E1 VDDIOP1 GPIO PC16 I/O – – A LCDC_DAT16 O 1 PIO, I, PU, STB ISC_FIELD I 1 C FLEXCOM10_IO0 I/O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 15 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER G4 VDDIOP1 GPIO PC17 I/O – – A LCDC_DAT17 O 1 PIO, I, PU, STB FLEXCOM1_IO7 I 1 C FLEXCOM10_IO1 I/O 1 E2 VDDIOP1 GPIO PC18 I/O – – A LCDC_DAT18 O 1 PIO, I, PU, STB FLEXCOM10_IO2 I/O 1 C PWM0 O 1 G3 VDDIOP1 GPIO PC19 I/O – – A LCDC_DAT19 O 1 PIO, I, PU, STB FLEXCOM10_IO3 I/O 1 C PWM1 O 1 D1 VDDIOP1 GPIO PC20 I/O – – A LCDC_DAT20 O 1 PIO, I, PU, STB FLEXCOM10_IO4 O 1 C PWM2 O 1 D3 VDDIOP1 GPIO PC21 I/O – – A LCDC_DAT21 O 1 PIO, I, PU, STC PWM3 O 1 D2 VDDIOP1 GPIO PC22 I/O – – A LCDC_DAT22 O 1 PIO, I, PU, STB FLEXCOM3_IO0 I/O 1 E4 VDDIOP1 GPIO PC23 I/O WKUP9 – A LCDC_DAT23 O 1 PIO, I, PU, STB FLEXCOM3_IO1 I/O 1 C1 VDDIOP1 GPIO PC24 I/O WKUP10 – A LCDC_DISP O 1 PIO, I, PU, STB FLEXCOM3_IO4 O 1 C4 VDDIOP1 GPIO PC25 I/O WKUP12 – A NTRST I 1 NRST_OUT, O, PDB FLEXCOM3_IO3 I/O 1 C NRST_OUT O 1 C2 VDDIOP1 GPIO PC26 I/O WKUP13 – A LCDC_PWM O 1 PIO, I, PU, STB FLEXCOM3_IO2 I/O 1 C5 VDDIOP1 GPIO PC27 I/O – – A LCDC_VSYNC O 1 PIO, I, PU, STC FLEXCOM1_IO4 O 1 B1 VDDIOP1 GPIO PC28 I/O – – A LCDC_HSYNC O 1 PIO, I, PU, STC FLEXCOM1_IO3 I/O 1 D5 VDDIOP1 GPIO PC29 I/O – – A LCDC_DEN O 1 PIO, I, PU, STC FLEXCOM1_IO2 I/O 1

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 16 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER A2 VDDIOP1 GPIO PC30 I/O – – A LCDC_PCK O 1 PIO, I, PU, STC FLEXCOM3_IO7 I 1 D7 VDDIOP1 GPIO PC31 I/O WKUP11 – A FIQ I 1 PIO, I, PU, STC PCK1 O 2 N11 VDDNF GPIO PD0 I/O – – A NANDOE O 1 PIO, I, PUC FLEXCOM7_IO2 I/O 1 H14 VDDNF GPIO PD1 I/O – – A NANDWE O 1 PIO, I, PUC FLEXCOM7_IO3 I/O 1 P11 VDDNF GPIO PD2 I/O – – A NANDALE O 1 A21,O, PDC FLEXCOM7_IO4 O 1 G15 VDDNF GPIO PD3 I/O – – A NANDCLE O 1 A22,O, PDC FLEXCOM11_IO2 I/O 1 P10 VDDNF GPIO PD4 I/O – – A NANDCS O 1 PIO, I, PUC FLEXCOM11_IO3 I/O 1 C17 VDDNF GPIO PD5 I/O – – C FLEXCOM11_IO4 O 1 PIO, I, PU P13 VDDNF GPIO PD6 I/O – – A NANDDAT0 I/O 1 PIO, I, PU P15 VDDNF GPIO PD7 I/O – – A NANDDAT1 I/O 1 PIO, I, PU H15 VDDNF GPIO PD8 I/O – – A NANDDAT2 I/O 1 PIO, I, PU R11 VDDNF GPIO PD9 I/O – – A NANDDAT3 I/O 1 PIO, I, PU D16 VDDNF GPIO PD10 I/O – – A NANDDAT4 I/O 1 PIO, I, PU N14 VDDNF GPIO PD11 I/O – – A NANDDAT5 I/O 1 PIO, I, PU K15 VDDNF GPIO PD12 I/O – – A NANDDAT6 I/O 1 PIO, I, PU P8 VDDNF GPIO PD13 I/O – – A NANDDAT7 I/O 1 PIO, I, PU E16 VDDNF GPIO PD14 I/O – – A NANDRDY I 1 PIO, I, PU

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 17 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 18 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER J15 VDDIOM power VDDIOM I – – – – – – – K8 VDDIOM power VDDIOM I – – – – – – – K14 VDDIOM power VDDIOM I – – – – – – – P7 VDDIOM power VDDIOM I – – – – – – – M15 VDDNF power VDDNF I – – – – – – – R9 VDDIOP0 power VDDIOP0 I – – – – – – – C6 VDDIOP1 power VDDIOP1 I – – – – – – – R12 VDDIOP2 power VDDIOP2 I – – – – – – – T2 VDDBU power VDDBU I – – – – – – – R6 VDDANA power VDDANA I – – – – – – – P6 GNDANA ground GNDANA I – – – – – – – E5 VDDIN25 power VDDIN25 I – – – – – – –

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 19 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER M1 VDDOUT25 power VDDOUT25 I – – – – – – – J3 VDDIN33 power VDDIN33 I – – – – – – – M4 VDDIN33 power VDDIN33 I – – – – – – – F7 VDDCORE power VDDCORE I – – – – – – – G6 VDDCORE power VDDCORE I – – – – – – – L6 VDDCORE power VDDCORE I – – – – – – – M2 VDDCORE power VDDCORE I – – – – – – – M7 VDDCORE power VDDCORE I – – – – – – – M11 VDDCORE power VDDCORE I – – – – – – – N5 VDDCORE power VDDCORE I – – – – – – – E7 VDDQSPI power VDDQSPI I – – – – – – – F3 VDDMIPI power VDDMIPI I – – – – – – – D9 VDDLVDS power VDDLVDS I – – – – – – – E15 VDDIOM analog DDR_VREF I – – – – – – – H13 VDDIOM analog DDR_CAL I – – – – – – – U3 VDDANA GPIO ADVREFP – – – – – – – I U2 VDDANA GPIO ADVREFN – – – – – – – I

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 20 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER K5 VDDIN33 USBHS HHSRTUNE – – – – – – – I P1 VDDIN33 USBHS HHSDPA – DHSDP – – – – – O, PD P2 VDDIN33 USBHS HHSDMA – DHSDM – – – – – O, PD N1 VDDIN33 USBHS HHSDPB – – – – – – – O, PD N2 VDDIN33 USBHS HHSDMB – – – – – – – O, PD N3 VDDIN33 USBHS HHSDPC – – – – – – – O, PD P3 VDDIN33 USBHS HHSDMC – – – – – – – O, PD T14 VDDBU GPIO WKUP0 – – – – – – – I, ST U14 VDDBU GPIO SHDN – – – – – – – O, PD U16 VDDBU GPIO JTAGSEL – – – – – – – I, PD P9 VDDBU GPIO TST – – – – – – – I, PD, ST U13 VDDIOP0 GPIO TCK – – – – – – – I, ST T13 VDDIOP0 GPIO TDI – – – – – – – I, ST T17 VDDIOP0 GPIO TDO – – – – – – – O U15 VDDIOP0 GPIO TMS – – – – – – – I, ST T15 VDDIOP0 GPIO RTCK – – – – – – – O P5 VDDIOP0 GPIO NRST – – – – – – – I, PU, ST U5 VDDBU CLOCK XIN32 – – – – – – – I U4 VDDBU CLOCK XOUT32 – – – – – – – O L1 VDDIN33 CLOCK XIN – – – – – – – I L2 VDDIN33 CLOCK XOUT – – – – – – – O H1 VDDMIPI analog MIPI_DN0 I/O – – – – – – HiZ H2 VDDMIPI analog MIPI_DP0 I/O – – – – – – HiZ J1 VDDMIPI analog MIPI_DN1 I/O – – – – – – HiZ J2 VDDMIPI analog MIPI_DP1 I/O – – – – – – HiZ K1 VDDMIPI analog MIPI_DN2 I/O – – – – – – HiZ K2 VDDMIPI analog MIPI_DP2 I/O – – – – – – HiZ L3 VDDMIPI analog MIPI_DN3 I/O – – – – – – HiZ L4 VDDMIPI analog MIPI_DP3 I/O – – – – – – HiZ K3 VDDMIPI analog MIPI_CLKN O – – – – – – HiZ K4 VDDMIPI analog MIPI_CLKP O – – – – – – HiZ H5 VDDMIPI analog MIPI_REXT I – – – – – – I

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 21 BGA243 Pins rotatethispage90 Power Rail I/O Type Primary Alternate PIO Peripheral Reset State Signal Dir Signal Dir Func Signal Dir I/O Set Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER M5 VDDANA GPIO AUDIO_CLK – – – – – – – O

Electrical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 22 6. Electrical Char act eristics Electrical characteristics, schematics, procedures and recommendations are the same as those given in the SAM9X7 Series data sheet (see Reference Documents).

• The VDDQ and VDD power inputs described in the DDR3L SDRAM data sheets are connected to the SAM9X75 SiP balls called “DDRM_VDD”. Therefore, the requirements placed on VDDQ and VDD power inputs in the “Absolute Maximum Ratings” and “Recommended DC Operating Conditions” sections of these data sheets apply to the DDRM_VDD power inputs.
• The VDDIN25 input powers the LVDS PLL of the device. It must be connected to VDDOUT25 on the PCB. From an Absolute Maximum Ratings perspective, VDDIN25 has the same specification as VDDLVDS.

6.1 Recommended Thermal Oper ating Conditions

Table 6-1. Recommended Thermal Oper ating Conditions Symbol Parameter Min Max Unit TA Ambient temperature range -40 85 °C TJ_MPU Junction temperature range -40 125 °C TJ_DDRx -40 125 °C Table 6-2. BGA243 Package Thermal Char act eristics (1)(2)(3) Symbol Parameter Typ Unit RJA Junction-to-ambient thermal resistance 26 °C/W Notes: 1. R JA = (TJ_MPU - TA) / PTOT, where TA is the ambient temperature and PTOT is the power consumption of both the processor and the embedded DDR memory. The DDR3L SDRAM junction temperature is always lower than the MPU junction temperature. 2. According to the JEDEC JESD51-2 standard, with 2s2p board and 0 m/s air flow. 3. These values are not directly applicable to the board where the device is mounted. As per JEDEC standards, these parameters do not characterize the package itself but rather the package together with the PCB (four layers or more) and other environmental factors, such as still air. For example, in still air JEDEC-defined RJA measurements, almost 70% of the power generated by the chip is dissipated from the test board, not from the package surfaces.

6.2 Power Sequences

The DDR SDRAM power rail (DDRM_VDD) must be connected to VDDIOM on the PCB. Refer to the section “Recommended Power Supply Sequencing” in the SAM9X7 Series data sheet (see Reference Documents).

6.3 Device Power Consumption in Applic ativ e Use Cases

Table 6-4 provides the processor power consumption in the following conditions:

• f CPU_CLK = 800 MHz
• f MCK = 266 MHz
• I & D caches are enabled.
• Use cases run on Linux
• Current consumptions are measured as shown in Figure 6-1. Note that external component current consumptions are not counted.
• Ambient temperature: 25°C The measurements are provided for typical SAM9X75D1G and SAM9X75D2G devices.

Electrical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 23 Figure 6-1. Current Measurement for Applic ativ e Use Cases (DDR3L Example) VDDIOP1 SAM9X75DxG DDR3 L QSPI Ethernet PH Y VDDIOMVDDQSPI Power supply 3.3V 1.35V 1.15V VDDCORE VDDIN33 VDDNF VDDAN A VDDIOP0 VDDBU VDDIOP0 LVDS screen VDD LVDS VDDDMIPI 3.0V (Backup source) 1.8V CSI-2 sensor VDDOUT25 VDDMIPI VDDOUT25 regulator DDRM_VDD VDDIOP1 VDDIOP2 Table 6-3. Use Case De finition Use Case Description

1 After Linux boot root prompt

2 Running 2D graphics benchmark with EGT monitor (800x480 DSI panel @ 46 fps) - 22% CPU usage

3 Run Bonnie++ on USB mass storage

4 SAM9X70 running as iPerf server

5 Image sensor video recording with QVGA resolution - 10 fps

Table 6-4. Power Consumption (mW) in Applic ativ e Use Cases Use Case VDDCORE 1.15V VDDIOM+ DDRM_VDD 1.35V VDDIN33 3.3V Total 1 135 41 165 341 2 165 55 125 345 3 190 84 115 390 4 165 95 165 425 5 170 61 330 561

Electrical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 24

6.4 SDRAM Power Consumption in Idle and Ultra-Low Power (ULP0, ULP1) Modes

with SDRAM in Self-Refresh For a complete description of how to enter and exit ULP0 or ULP1 mode, refer to the SAM9X7 Series data sheet (see Reference Documents). Table 6-5. Typical Current Consumption in Idle, ULP0 or ULP1 Mode on VDDIOM and DDRM_VDD VDDIOM DDRM_VDD (V) TA=-40°C TA= 25°C TA= 50°C TA= 70°C TA=85°C Unit 1.35 6 6 6 7 7 mA

Mechanical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 25 7. Mechanical Char act eristics 7.1 243-Ball TFBGA Mechanical Char act eristics B A 0.15 C 0.15 C

0.15 C A B

0.08 C TOP VIEW BOTTOM VIEW For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 243-Ball Thin Fine-Pitch Ball Grid Array (4TB) - 16x16x1.23 mm Body [TFBGA] © 2022 Microchip Technology Inc. Sheet 1 of 2Microchip Technology Drawing C04-21556 Rev B NOTE 1 C END VIEW 0.20 C 0.10 C 243X SEATING PLANE A B C D E F G H J K L M N P R T U 1 3 5 7 9 1 11 31 5 1 7 2 4 6 8 10 12 14 16 A B C D E F G H J K L M N P R T U 1 3 5 7 9 1 11 31 51 7 2 4 6 8 10 12 14 16 D E 243X Øb e M A

Mechanical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 26 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2022 Microchip Technology Inc. REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Terminal A1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 Number of Terminals Overall Height Ball Diameter Overall Width Ball Array Width Pitch Ball Height Units Dimension Limits A b e E N

0.80 BSC

0.35 0.40

12.80 BSC

0.21

16.00 BSC

0.45 1.23 0.312 MAX Overall Length Ball Array Length D Mold Thickness M 0.56 0.51 0.61 243-Ball Thin Fine-Pitch Ball Grid Array (4TB) - 16x16x1.23 mm Body [TFBGA] Microchip Technology Drawing C04-21556 Rev B

Mechanical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 27 RECOMMENDED LAND PATTERN Dimension Limits Units C2Contact Pad Spacing Contact Pitch MILLIMETERS E MAX Contact Pad Width (X243) X 0.35 NOM C1Contact Pad Spacing 12.80 BSC Contact Pad to Contact Pad G 0.45 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2022 Microchip Technology Inc. Microchip Technology Drawing C04-23556 Rev B E ØX G SILK SCREEN A B C D E F G H J K L M N P R T U 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 243-Ball Thin Fine-Pitch Ball Grid Array (4TB) - 16x16x1.23 mm Body [TFBGA]

Mechanical Char act eristics Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 28 Table 7-1. 243-ball TFBGA Package Char act eristics Moisture sensitivity level MSL3 Table 7-2. Device and 243-ball TFBGA Package Weight 520 mg Table 7-3. Package Reference JEDEC drawing reference NA J-STD-609 classification e8 Table 7-4. 243-ball TFBGA Package In f ormation Ball land 0.450 mm Nominal ball diameter 0.400 mm Solder mask opening 0.350 mm Solder mask definition Solder Mask Defined (SMD) Solder SAC105

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 29 8. Marking Top marking follows the scheme below: XXXXXXXXXXX YYWWNNN ARM XXXXXXXXXXX with possible values: Line Description Values

1 Company logo Microchip logo

2 Company name Microchip

3 Device name

4 Temperature code/Packaging code, Jedec symbol I/4PB

5 Lot traceability, Arm logo YYWWNNN ARM

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 30 9. Ordering In f ormation For details on ordering codes, see Product Identification System. Ordering Code Memory Type Memory Size Package Carrier Type Ambient Temperature Range SAM9X75D1G-I/4TB DDR3L SDRAM

1 Gbit

-40°C to +85°C SAM9X75D1GT-I/4TB Tape and Reel SAM9X75D2G-I/4TB

2 Gbits

SAM9X75D2GT-I/4TB Tape and Reel

Revision History

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 31 10. Revision History

10.1 DS60001827B - 11/2023

Various updates, including in document title and Configuration Summary

10.2 DS60001827A - 09/2023

First issue.

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 32 Microchip In f ormation The Microchip Website Microchip provides online support via our website at www.microchip.com/. This website is used to make files and information easily available to customers. Some of the content available includes:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
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© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 33 Product Identific ation System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Architecture Product Group X75 Memory SAM9 I Carrier Type Temperature / 4TB Package T –D1G Architecture: SAM9 = ARM926EJ–S Arm Thumb microprocessor Product Group: X75 = General purpose microprocessor Memory Type and Size: D1G = 1-Gbit DDR3L SDRAM D2G = 2-Gbit DDR3L SDRAM Carrier Type: Blank = Standard packaging (tray) T = Tape and reel Ambient Temperature Range: I = –40°C to +85°C (industrial) Example:

• SAM9X75D1GT–I/4TB = ARM926EJ–S Arm Thumb microprocessor, 1-Gbit DDR3L SDRAM, tape and reel packaging, industrial temperature range, 243-ball TFBGA package Notes: 1. The Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. Small form-factor packaging options may be available. Please check www.microchip.com/ packaging for small-form factor package availability, or contact your local Sales Office. Microchip Devices Code Pr ot ection Feature Note the following details of the code protection feature on Microchip products:
• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. Legal Notice This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 34 that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/design-help/ client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP , INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, MarginLink, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP , SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

© 2023 Microchip Technology Inc. and its subsidiaries DS60001827B - 35 All other trademarks mentioned herein are property of their respective companies. © 2023, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-6683-3387-7 AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP , RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Quality Management System For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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