TET-2000

TET-2000 BEL | Alldatasheet

Document overview

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Technical content

The TET2000 Series is a 2100 Watt AC -DC power -factor-corrected (PFC) and DC/DC power supply that converts standard AC mains power or high voltage DC bus voltages into a main output of 12 VDC for powering intermediate bus architectures (IBA) in high performance and reliability servers, routers, and network switches. The TET2000-12-086 Series meets international safety standards and displays the CE-Mark for the European Low Voltage Directive (LVD).

• Best-in-class, 80 PLUS certified “Titanium” efficiency
• Wide input voltage range: 180 - 264 VAC / 2100 W, 90 - 180 VAC / Linear derating
• AC input with power factor correction
• Always-on 24 W standby output (12 V / 2 A)
• Hot-plug capability
• Parallel operation with active current sharing thru analog bus
• Full digital controls for improved performance
• High density design: 51 W/in3
• Small form factor: 195 x 86 x 40 mm (7.68 x 3.39 x 1.57 in)
• Up to 400 kHz
• I2C communication interface with Power Management Bus protocol for monitoring, control, and firmware update via bootloader
• RoHS Compliant
• Status LED with fault signaling
• Safety-approved to IEC 62368-1:2014 2nd ed. and UL 62368-1 2nd ed.
• US patents
• High Performance Servers
• Routers
• Switches

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supply is fan cooled and ideally suited for server integration with a matching airflow path. unity power factor over a wide operating range. on the output ensures n o reverse load current and renders the supply ideally suited for operation in redundant power systems. an active OR-ing device provides for maximum reliability. of the firmware in the DSP controllers. power demand and supply temperature and can be overridden through the I2C buses. Figure 1. TET2000-12-086 Series Block Diagram cause permanent damage to the supply.

General Condition: TA = 0…+50 °C, unless otherwise noted. 2) The Front-End is provided with a typical hysteresis of 5 V during turn-on and turn-off within the ranges. internal in-rush current limiting device PTC may not sufficiently cool down and self over temperature protection may result. Figure 2. Inrush current, Vin = 264Vac, 90°

4.1 INPUT FUSE

Quick-acting 16 A input fuses (5.4 × 22.5 in mm) in series with the L-line inside the power supply protect against severe defects. The fuses are not accessible from the outside and are therefore not serviceable parts.

4.2 INRUSH CURRENT

is connected to the mains. The internal bulk capacitor will be charged through a PTC which will limit the inrush current.

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Figure 3. Power Factor vs. Load Figure 4. Power Factor vs. Load

4.3 INPUT UNDER-VOLTAGE

inhibited. Once the input voltage returns within the normal operating range, the supply will return to normal operation again.

4.4 POWER FACTOR CORRECTION

4.5 EFFICIENCY

operating temperature regardless of the ambient temperature and load conditions.

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2019 Bel Power Solutions & Protection BCD.00877_AB General Condition: Ta = 0… +50°C unless otherwise specified. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Main Output V1 V1 nom Nominal Output Voltage 0.5 ∙I1 nom, Tamb = 25 °C

12.3 VDC

V1 set Output Setpoint Accuracy -0.5 +0.5 % V1 nom dV1 tot Total Regulation Vi min to Vi max, 0 to 100% I1 nom, Ta min to Ta max -2 +2 % V1 nom P1 nomll Nominal Output Power V1 = 12.3 VDC, Vin < 180 VAC See Section 10.3 Figure 42 I1 nomll Nominal Output Current V1 = 12.3 VDC, Vin < 180 VAC See Section 6.3 Figure 24 and Table 1 P1 nom Nominal Output Power V1 = 12.3 VDC, Vin > 180 VAC 2079 W I1 nom Nominal Output Current V1 = 12.3 VDC, Vin > 180 VAC 169 A IV1 ol Short Time Over Load Current V1 = 12.3 VDC, Vin > 180 VAC Ta min to Ta max, maximum duration 20 ms (See Section 5.2) 203 A V1 pp Output Ripple Voltage V1 nom, I1 nom, 20MHz BW (See Section 5.1) (see Figure 11,12) 80 120 mVpp dV1 Load Load Regulation Vi = Vi nom, 0 - 100 % I1 nom 110 mV dV1 Line Line Regulation Vi =Vi min…Vi max 0 mV dIshare Current Sharing (I1 x - I1 y ) / I1 tot, I1 tot > 25% I1 nom -5 +5 % dVdyn Dynamic Load Regulation ΔI1 = 50% I1 nom, I1 = 5 … 100% I1 nom, dI1/dt = 1A/μs, recovery within 1% of V1 nom (see Figure13,14,15,16) -0.6 0.6 V Trec Recovery Time 0.5 1 ms tAC V1 Start-up Time from AC V1 = 10.8 VDC (see Figure 5) 2.7 3 sec tV1 rise Rise Time V1 = 10…90% V1 nom (see Figure 8) 30 ms CLoad Capacitive Loading Ta = 25°C 20,000 μF Standby Output VSB VSB nom Nominal Output Voltage 0.5 ∙ISB nom, Tamb = 25°C

12.0 VDC

VSB set Output Setpoint Accuracy -1 +1 %VSB nom dVSB tot Total Regulation Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max -3 +3 %VSB nom PSB nom Nominal Output Power VSB = 12.0 VDC 24 W ISB nom Nominal Output Current VSB = 12.0 VDC 2 A VSB pp Output Ripple Voltage VSB nom, ISB nom, 20 MHz BW (See Section 5.1) (see Figure 9, 10) 60 120 mVpp dVSB Droop 0 - 100 % ISB nom 180 mV dVSBdyn Dynamic Load Regulation ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom, dIo/dt = 1 A/μs, recovery within 1% of V1 nom -0.6 0.6 V Trec Recovery Time 0.5 ms tAC VSB Start-up Time from AC VSB = 90% VSB nom (see Figure 5) 2.5 3 sec tVSB rise Rise Time VSB = 10…90% VSB nom (see Figure 7) 30 ms CLoad Capacitive Loading Tamb = 25°C 1,000 μF

6 TET2000 Series

Figure 5. Turn-On AC Line 230VAC, full load (400ms/div) Figure 6. Turn-Off AC Line 230VAC, full load (10ms/div) Figure 7. Turn-On AC Line 230VAC, full load (4ms/div) Figure 8. Turn-On AC Line 230VAC, full load (2ms/div) Figure 9. VSB Ripple 230VAC, full load (10ms/div) Figure 10. VSB Ripple 230VAC, full load (10us/div) Figure 11. V1 Ripple 230VAC, full load (10ms/div) Figure 12. V1 Ripple 230VAC, full load (2us/div)

Figure 13. Load Transient V1, 92.95 to 8.45 A, 1A/uS (200 μs/div) Figure 14. Load Transient V1, 8.45 to 92.95 A, 1A/uS (200 μs/div) Figure 15. Load Transient V1, 169 to 84.5 A, 1A/uS (200 μs/div) Figure 16. Load Transient V1, 84.5 to 169 A, 1A/uS (200 μs/div) Figure 17. Short circuit on V1 (4ms/Div), Short with 400A Figure 18. Short circuit on V1 (0.4ms/Div),Short without control

5.1 OUTPUT VOLTAGE RIPPLE

ceramic capacitors, referring the setup in Figure 19. b) The ripple voltage is measured with 20 MHz BWL. Figure 19. Output Ripple Test Setup

8 TET2000 Series

5.2 SHORT TIME OVERLOAD

of 20ms. This allows the system to consume extended power for short time dynamic processes. Figure 20. Short circuit on V1 (20ms/Div)

5.3 OUTPUT GROUND / CHASSIS CONNECTION

Figure 21. Alternatively, separated ground signals can be used as shown in Figure 22. In this case the two ground planes should be connected at the power supplies ground pins. Figure 21. Common Low Impedance Ground Plane Figure 22. Separated Power and Signal Ground

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2019 Bel Power Solutions & Protection BCD.00877_AB PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT F Input Fuse (Line) Not user accessible, quick-acting (F) 16 Arms V1 OV OV Threshold V1 13.3 13.9 14.5 VDC tOV V1 OV Latch Off Time V1 1 ms VSB OV OV Threshold VSB 13.3 13.9 14.5 VDC tOV VSB OV Latch Off Time VSB 1 ms IV1 lim Current Limitation V1 Vi < 180 VAC, Ta < 50°C Vi < 180 VAC, Ta = 55 °C 3) Vi < 180 VAC, Ta = 60 °C 3) Vi > 180 VAC, Ta < 50°C Vi > 180 VAC, Ta = 55 °C 3) Vi > 180 VAC, Ta = 60 °C 3 See Figure 24 and Table 1 A 177 160 141.6 185 166.5 148 193 173 154.4 tV1 lim Current Limit Blanking Time Time to latch off when in over current 20 ms IV1 ol lim Current Limit During Short Time Overload V1 Maximum duration 20 ms 203 210 214 A IV1 SC Max Short Circuit Current V1 V1 < 3V 2104) A tV1 SC off Short Circuit Latch Off Time Time to latch off when in short circuit (Short circuit current < 400 A) See Figure 17 (Short circuit current > 400 A) See Figure 18 0.2 ms IVSB lim Current Limitation VSB 2.2 2.5 2.8 A tVSB lim Current Limit Blanking Time Time to hit hiccup when in over current 1 ms 3) See Figure 24 and Table 1 for linear derating > 50°C 4) Limit set doesn’t include effects of main output capacitive discharge.

6.1 OVERVOLTAGE PROTECTION

The TET2000-12-086 Series front-end provides a fixed threshold overvoltage (OV) protection implemented with a HW comparator for both the main and the standby output. Once an OV condition has been triggered on the main output, the supply will shut do wn and latch the fault condition. The latch can be unlocked by disconnecting the supply from the AC mains or by toggling the PSON_L input. The standby output will continuously try to restart with a 1 s interval after OV condition has occurred.

6.2 UNDERVOLTAGE DETECTION

Both main and standby outputs are monitored. PWOK pin signal if the output voltage exceeds ±5% of its nominal voltage. The main output will latch off if the main output voltage when V1 falls below 11.2V (typically in an overload condition), the latch can be unlocked by disconnecting the supply from the AC mains or by toggling the PSON_L input. If the standby output leaves its regulation bandwidth for more than 10ms then the main output is disabled to protect the system, and the standby output will continuously try to restart with a 1s interval after UV condition has occurred.

6.3 CURRENT LIMITATION

The main output current limitation level I V1 lim will decrease if the ambient (inlet) temperature increases beyond 50 °C (see Figure24 and Table1). Note that the current limitation on V1 will kick in at a current level approximately 10A-16A higher nominal output current that is shown. The 2nd protection is a substantially rectangular output characteristic controlled by a software feedback loop. This protects the power supply and system during the 20ms blanking time of the static over current protection. If the output current is rising fast and reaches IV1 ol lim, the supply will immediately reduce its output voltage to prevent the output current from exceeding I V1 ol lim. When the output current is reduced below IV1 ol lim, the output voltage will return to its nominal value. When the main output over current, the V1 will shut down and latch off. The latch can be cleared by recycling the input voltage or the PSON_L input. A failure on the Main output will shut down only the Main output, while Standby continues to operate.

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Figure 23. Current Limitation on V1 (Vi = 230 VAC) Figure 24. Derating on V1 vs Ta & Vin repeatedly trying to restart with 1s intervals. A failure on the Standby output will shut down both Main and Standby outputs.

Figure 25. Current Limitation on VSB Table 2. Monitoring accuracy

8.1 ELECTRICAL CHARACTERISTICS (INPUT SIGNALS)

Table 3. Input signals

8.1.1 PSKILL INPUT

will remain on regardless of the PSKILL input state.

12 TET2000 Series

8.1.2 PSON_L INPUT

Figure 26. PSON_L Connection

8.1.3 SENSE INPUTS

path. The maximum allowed voltage drop is 200 mV on the positive rail and 50 mV on the GND rail. case the power supply will shut down.

8.2 ELECTRICAL CHARACTERISTICS (OUTPUT SIGNALS)

All Output signals versus signal ground SGND in PSU.

Table 4. Output signals

8.2.1 PWOK

sufficiently long so that power supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. Figure 27. PWOK circuit in PSU

8.2.2 ACOK

protect internal circuits from negative and high positive voltage. The ACOK signal is active-high. Figure 28. ACOK Connection

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8.2.3 SMB_ALERT_L

The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate. limits. This signal is to be asserted in parallel with LED turning solid Amber. temperature range. Fan speed control algorithm shall ramp up the fan speed to the maximum prior to the SMB_ALERT_L insertion. Figure 29. SMB_ALERT_L Connection

8.2.4 PRESENT_L OUTPUT

4 mA to guarantee a low level voltage if power supply is seated. Figure 30. PRESENT_L Signal Pin

8.3 ELECTRICAL CHARACTERISTICS (BIDIRECTIONAL SIGNALS)

8.3.1 CURRENT SHARE

ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases. Master/Slave current share function. The power supply providing the largest current among the group is automatically the Master. their output voltage. The voltage increase is limited to +250 mV. The output will share within 5% at full load. device and is disconnected from internal circuits when the power supply is switched off. The 12 VSB output is not required to actively share current between power supplies (passive sharing).

Table 5. Power Available When PSU in Redundant Operation

8.4 FRONT LEDS

or fault situations. For the position of the LED see Table lists the different LED status. Table 6. LED Status

8.5 SIGNAL TIMING

Table 7. Timing

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Figure 31. AC Turn-On Timing Figure 32. AC Long Dips Figure 33. AC Short Dips Figure 34. PSON_L Turn-on/off Timing

8.6 I2C / Power Management Bus COMMUNICATION

Figure 35. Physical Layer of Communication Interface

• The SDA/SCL IOs use 3V3 logic levels
• External pull-up resistors on SDA/SCL required for correct signal edges
• Full SMBus clock speed of 400 kbps
• Clock stretching limited to 1 ms
• SCL low time-out of > 25 ms with recovery
• within 10 ms
• Recognizes any time Start/Stop bus conditions Communication to the DSP or the EEPROM will be possible as long as the input AC voltage is provided. If no AC is present, communication to the unit is possible if it is connected to a life 12 V or 12 VSB output (provided e.g. by the redundant unit).

Table 9. Address and Protocol Encoding

1 Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF

Table 8. I2C / SMBus Specification Figure 36. I2C / SMBus Timing addressing offset exists between the Controller and the EEPROM.

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8.7 CONTROLLER AND EEPROM ACCESS

accessed under different addresses, see Table 9 Address and Protocol Encoding. The SDA/SCL lines are connected directly to the controller and EEPROM which are supplied by internal 3V3. The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply. Figure 37. I2C Bus to DSP and EEPROM

8.8 EEPROM PROTOCOL

commands are defined, it is recommended to use the single byte write / read commands. bus should only occur after 1ms of the last STOP condition to allow the EEPROM to write the data into its memory. the data byte at the specified location.

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2019 Bel Power Solutions & Protection BCD.00877_AB

8.9 POWER MANAGEMENT BUS PROTOCOL

The Power Management Bus is an open standard protocol that defines means of communicating with power conversion and other devices. For more information, please see the System Management Interface Forum web site at: www.powerSIG.org. Power Management Bus command codes are not register addresses. They describe a specific command to be executed. TET2000-12-086 Series supply supports the following basic command structures:

• Clock stretching limited to 1 ms
• SCL low time-out of >25 ms with recovery within 10 ms
• Recognized any time Start/Stop bus conditions WRITE The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte or after the first data byte (Byte command) or then after sending 2 data bytes (Word command). In addition, Block write commands are supported with a total maximum length of 255 bytes. See TET2000-12-086 Series Programming Manual for further information. READ The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word. In addition, Block read commands are supported with a total maximum length of 255 bytes. See TET2000-12-086 Series Power Management Bus Communication Manual URP.00560 for further information. S Address W A Command A Data Low Byte1) A Data High Byte1) A P 1) Optional S Address W A Command A Byte 1 A Byte N A P Byte Count A S Address W A Command A Data (Low) Byte AS Address R A Data High Byte1) nA P 1) Optional S Address W A Command A Byte 1 A S Address R A Byte N nA PByte Count A

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Figure 38. Mechanical Drawing - Front / Rear View Figure 39. Mechanical Drawing - Side / Top View NOTE: A 3D step file of the power supply casing is available on request.

10.1 FAN CONTROL

optimal supply cooling and is a function of output power and the inlet temperature. Figure 40. Airflow Direction Figure 41. Fan Speed vs. Main Output Load

10.2 TEMPERATURE MONITOR AND OVER TEMPERATURE PROTECTION

accordingly through LED, PWOK and SMB_ALERT_L. Table 10. NA revision Temperature Sensor Location and Thresholds

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10.3 TEMPERATURE MONITOR AND OVER TEMPERATURE PROTECTION

Figure 42. Output power VS Input voltage and inlet temperature Table 11. Immunity

11.2 EMISSION

Table 12. Emission

11.1 IMMUNITY

Table 13. Safety/Approvals temperature specifications and lifetime requirements. to the air exhaust side must be classified as “Handle, knobs, grips, etc. held for short periods of time only”. temperature in compliance with IEC/UL 60950-1 and additionally 85C rated power cords must also be used with this power supply. Table 14. Operation Environmental

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Table 15. Connector pin assignment The AC input receptacle shall be a 3 pins IEC320 C20 inlet. For the pin assignment of DC connector, please refer to Figure 43 and Table 15. The Mating connector should be FCI 10121510-480020ALF. Figure 43. Pin Assignment of DC Connector

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2019 Bel Power Solutions & Protection BCD.00877_AB ITEM DESCRIPTION ORDERING PART NUMBER SOURCE I2C Utility Windows XP/Vista/7 compatible GUI to program, control and monitor TET2000-12-086NA/RA Front-Ends (and other I2C units) N/A befuse.com/lpower-solutions Single Connector Board Connector board to operate TET2000-12- 086NA/RA unit. Includes an on-board USB to I2C converter (use Ii2C Utility as desktop software). YTM.G1Z01.0 befuse.com/lpower-solutions REVISION DESCRIPTION OF CHANGES DATE ORIGINATOR AA Initial release 2018-02-27 Jun.li AA1 1) Disclaimer on the first page (PMBus is a registered trademark of SMIF, Inc.): was removed 2) PMBus needs to be fully spelled out every time it is used: Power Management Bus 3) No trademark symbols used with Power Management Bus 2019-03-29 Stefancova, Vladimira AB 1) Change the Max Input Current to 13.5A from 12A in section4 page3 2) Remove HVDC Input efficiency in Figure 4 page 4 3) Correct max power typo in section10.3 page22 4) Change tV1 off and tVSB off from 1000ms to 500ms min in section8.5 page15 5) Add ACCESSORIES information in section15 page 25 6) Change Electrical Strength Test Input to case voltage from 2.8 to 2.1 kVDC in section12 page23 2019-06-18 Jun.li NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice.