TEST ETC | Alldatasheet
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Technical content
- General description The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I2C-bus interface. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCAL6408A has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/O voltages is required. Its wide V DD range of 1.65 V to 5.5 V on the dual power rail allows seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side. There are two supply voltages for PCAL6408A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The bidirectional voltage level translation in the PCAL6408A is provided through VDD(I2C-bus). VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates the VDD level of the I2C-bus to the PCAL6408A, while the voltage level on Port P of the PCAL6408A is determined by the VDD(P). The PCAL6408A contains the PCA6408A register set of 8-bit Configuration, Input, Output, and Polarity Inversion registers and additionally, the PCAL6408A has Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. The PCAL6408A is a pin-to-pin replacement to the PCA6408A, however, the PCAL6408A powers up with all I/O interrupts masked. This mask default allows for a board bring-up free of spurious interrupts at power-up. At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete components. PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers Rev. 3 — 18 September 2013 Product data sheet
Product data sheet Rev. 3 — 18 September 2013 2 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander The system master can reset the PCAL6408A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part. The PCAL6408A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. Thus, the PCAL6408A can remain a simple slave device. The input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. This minimizes the host’s interrupt service response for fast moving inputs. The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I2C-bus address and allow up to two devices to share the same I2C-bus or SMBus. 2. Features and benefits I2C-bus to parallel port expander Operating power supply voltage range of 1.65 V to 5.5 V Allows bidirectional voltage-level translation and GPIO expansion between: 1 . 8V S C L / S D A a n d 1 . 8V , 2 . 5V , 3 . 3V o r 5V P o r tP 2 . 5V S C L / S D A a n d 1 . 8V , 2 . 5V , 3 . 3V o r 5V P o r tP 3 . 3V S C L / S D A a n d 1 . 8V , 2 . 5V , 3 . 3V o r 5V P o r tP 5V S C L / S D A a n d 1 . 8V , 2 . 5V , 3 . 3V o r 5V P o r tP Low standby current consumption of 1 A Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs Vhys = 0.18 V (typical) at 1.8 V Vhys = 0.25 V (typical) at 2.5 V Vhys = 0.33 V (typical) at 3.3 V Vhys = 0.5 V (typical) at 5 V 5 V tolerant I/O ports Active LOW reset input (RESET) Open-drain active LOW interrupt output (INT) 400 kHz Fast-mode I2C-bus Internal power-on reset Power-up with all channels configured as inputs No glitch on power-up Noise filter on SCL/SDA inputs Latched outputs with 25 mA drive maximum capability for directly driving LEDs Latch-up performance exceeds 100 mA per JESD 78, Class II
2.1 Agile I/O features
Table 1. Ordering information
3.1 Ordering options
Table 2. Ordering options
6000 T amb = 40 C to +85 C
2500 Tamb = 40 C to +85 C
4000 T amb = 40 C to +85 C
5000 T amb = 40 C to +85 C
All I/Os are set to inputs at reset.
8 BITS
Product data sheet Rev. 3 — 18 September 2013 5 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 5. Pinning information
5.1 Pinning
The exposed center pad, if used, must be connected only as a secondary VSS or must be left electrically open. Fig 2. Pin configuration for TSSOP16 Fig 3. Pin configuration for HVQFN16 Fig 4. Pin configuration for XQFN16 PCAL6408APW VDD(I2C-bus) VDD(P) ADDR SDA RESET SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 002aah086 002aah087 Transparent top view SCL VSS ADDR VDD(I2C-bus) VDD(P) SDA 4 9 3 10 2 11 1 12 terminal 1 index area RESET P0 INT PCAL6408ABS PCAL6408AHK terminal 1 index area 002aah088 Transparent top view 8 P5 7 P4
6 VSS
VDD(P)14 VDD(I2C-bus)15 ADDR 16 SCL12 INT11 P710 P6 9
1 RESET
5.2 Pin description
[1] All I/O are configured as input at power-on. Table 3. Pin description ADDR 2 16 16 B2 Address input. Connect directly to V DD(P) or ground. pull-up resistor if no active connection is used. P0[1] 4 2 2 B1 Port P input/output 0. P1[1] 5 3 3 C2 Port P input/output 1. P2[1] 6 4 4 C1 Port P input/output 2. P3[1] 7 5 5 D1 Port P input/output 3. P4[1] 9 7 7 D3 Port P input/output 4. P5[1] 10 8 8 D5 Port P input/output 5. P6[1] 11 9 9 C4 Port P input/output 6. P7[1] 12 10 10 C3 Port P input/output 7. VDD(P) 16 14 14 A3 Supply voltage of PCAL6408A for Port P.
Refer to Figure 1 “Block diagram (positive logic)”.
7.1 Device address
The address of the PCAL6408A is shown in Figure 7. read operation, while a LOW (logic 0) selects a write operation. Table 4. Voltage translation
7.2 Interface definition
7.3 Pointer register and command byte
(Agile I/O). This register is ‘write only’. Table 5. Interface definition Table 6. Command byte
7.4 Register descriptions
7.4.1 Input port register (00h)
7.4.2 Output port register (01h)
register, not the actual pin value.
7.4.3 Polarity inversion register (02h)
‘0’), the corresponding port pin’s original polarity is retained.
7.4.4 Configuration register (03h)
bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 7. Input port register (address 00h) Table 8. Output port register (address 01h) Table 9. Polarity inversion register (address 02h) Table 10. Configuration register (address 03h)
7.4.5 Output drive strength registers (40h, 41h)
See Section 9.2 “Output drive strength control” for more details.
7.4.6 Input latch register (42h)
next read of the input port register bit 4 should now read ‘0’. not cleared if the input latch register changes from latched to non-latched configuration. latched input, the read from the input port register reflects the latched logic level. Table 11. Current control register (address 40h) Table 12. Current control register (address 41h)
7.4.7 Pull-up/pull-down enable register (43h)
7.4.8 Pull-up/pull-down selection register (44h)
I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
7.4.9 Interrupt mask register (45h)
the Interrupt mask register is set to 0, the interrupt pin is asserted. interrupt pin is de-asserted. Table 13. Input latch register (address 42h) Table 14. Pull-up/pull-down enable register (address 43h) Table 15. Pull-up/pull-down selection register (address 44h) Table 16. Interrupt mask register (address 45h)
7.4.10 Interrupt status register (46h)
indicates that the input pin is not the source of an interrupt.
7.4.11 Output port configuration register (4Fh)
The output port configuration register selects port-wise push-pull or open-drain I/O stage. (03h) sets the port pins as outputs. Table 17. Interrupt status register (address 46h) Table 18. Output port configuration register (address 4Fh)
Product data sheet Rev. 3 — 18 September 2013 13 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either V DD(P) or VSS. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. On power-up or reset, all registers return to default values. Fig 9. Simplified schematic of the I/Os (P0 to P7) INTERRUPT MASK VDD(P) P0 to P7 output port register dataconfiguration register DQ CK Q data from shift register write configuration pulse output port register DQ CKwrite pulse polarity inversion register DQ CK data from shift register write polarity pulse input port register DQ CKread pulse input port register data 002aah089 FF data from shift register FF FF FF VSS to INT PULL-UP/PULL-DOWN CONTROL ESD protection diode 100 kΩ VDD(P) ESD protection diode input port latch DQ EN LATCH read pulse input latch register DQ CK FF data from shift register write input latch pulse
Product data sheet Rev. 3 — 18 September 2013 14 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
7.6 Power-on reset
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the PCAL6408A in a reset condition until VDD(P) has reached VPOR. At that time, the reset condition is released and the PCAL6408A registers and I2C-bus/SMBus state machine initialize to their default states. After that, VDD(P) must be lowered to below VPOR and back up to the operating voltage for a power-reset cycle. See Section 9.3 “Power-on reset requirements”.
7.7 Reset input (RESET )
The RESET input can be asserted to initialize the system while keeping the VDD(P) at its operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCAL6408A registers and I2C-bus/SMBus state machine are changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor to VDD(I2C-bus) if no active connection is used.
7.8 Interrupt output (INT )
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt (see Figure 13 ). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input port register. The INT output has an open-drain structure and requires a pull-up resistor to VDD(P) or VDD(I2C-bus) depending on the application. INT should be connected to the voltage source of the device that requires the interrupt information. When using the input latch feature, the input pin state is latched. The interrupt is reset only when data is read from the port that generated the interrupt. The reset occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Product data sheet Rev. 3 — 18 September 2013 15 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 8. Bus transactions The PCAL6408A is an I2C-bus slave device. Data is exchanged between the master and PCAL6408A through write and read commands using I2C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Write commands
Data is transmitted to the PCAL6408A by sending the device address and setting the Least Significant Bit (LSB) to a logic 0 (see Figure 7 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. Fig 10. Write to Output port register 0 AS slave address START condition R/W acknowledge from slave 002aaf825 00000010 command byte A acknowledge from slave 12345678SCL 9 SDA DATA 1 A write to port data out from port tv(Q) acknowledge from slave DATA 1 VALID data to port 10000 AD DR0 P STOP condition Fig 11. Write to Configuration or Polarity inversion registers 0 AS slave address START condition R/W acknowledge from slave 002aah090 1/0 0 0 0 1/0 1/0 1/00 command byte A acknowledge from slave 12345678SCL 9 SDA DATA 1 A acknowledge from slave data to register 10000 AD DR0 P STOP condition
Product data sheet Rev. 3 — 18 September 2013 16 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
8.2 Read commands
To read data from the PCAL6408A, the bus master must first send the PCAL6408A address with the least significant bit set to a logic 0 (see Figure 7 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart the device address is sent again, but this time the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the PCAL6408A (see Figure 12 and Figure 13). Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. Fig 12. Read from register AS START condition R/W acknowledge from slave 002aaf827 A acknowledge from slave SDA A P acknowledge from master DATA (first byte) slave address STOP condition S (repeated) START condition (cont.) (cont.) 10000 AD DR 1 A0 R/W acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter NA no acknowledge from master 10000 AD DR0 0 data from register DATA (last byte) data from register command byte 000000 1 1/0 Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 12). Fig 13. Read Input port register (non-latched) 10000 AD DR 1 AS0 slave address START condition R/W acknowledge from slave 002aaf828 data from port A acknowledge from master SDA 1 no acknowledge from master read from port data into port data from port DATA 1 DATA 4 INT DATA 4 DATA 2 DATA 3 P STOP condition tv(INT) trst(INT) th(D) tsu(D) 12345678SCL 9 DATA 1 DATA 5 INT is cleared by read from port STOP not needed to clear INT
Product data sheet Rev. 3 — 18 September 2013 17 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 12). Fig 14. Read Input port register (latch enabled) 10000 AD DR 1 AS0 slave address START condition R/W acknowledge from slave 002aah091 data from port A acknowledge from master SDA 1 no acknowledge from master read from port data into port data from port DATA 1 DATA 1 INT DATA 2 DATA 2 P STOP condition tv(INT) trst(INT) th(D) tsu(D) 12345678SCL 9 DATA 1 INT is cleared by read from port STOP not needed to clear INT
Product data sheet Rev. 3 — 18 September 2013 18 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 9. Application design-in information
9.1 Minimizing I DD when I/Os control LEDs
When the I/Os are used to control LEDs, normally they are connected to VDD through a resistor as shown in Figure 15. The LED acts as a diode, so when the LED is off, the I/O VI is about 1.2 V less than VDD. The IDD parameter in Table 23 “Static characteristics” shows how IDD increases as VI becomes lower than VDD. Designs that must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevent additional supply current consumption when the LED is off. Device address configured as 0100 000x for this example. P0 and P2 through P4 are configured as inputs. P1 and P5 through P7 are configured as outputs. (1) Resistors are required for inputs (on P port) that may float. If a driver to an input will nev er let the input float, a resistor is not needed. Outputs (in the P port) do not need pull-up resistors. Fig 15. Typical application PCAL6408A SCL SDA VDD SCL SDA VSS MASTER CONTROLLER VSS VDD(I2C-bus) = 1.8 V controlled switch A B enable INT VDD(P) INT 10 kΩ SUBSYSTEM 1 (e.g., alarm system) ALARM(1) 10 kΩ10 kΩ RESETRESET VDD(P) 002aah092 VDD(I2C-bus) VDD(I2C-bus) ADDR KEYPAD 10 kΩ 10 kΩ (× 3)
Product data sheet Rev. 3 — 18 September 2013 19 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
9.2 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure 18 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. Fig 16. High-value resistor in parallel with the LED Fig 17. Device supplied by a lower voltage 002aah278 LEDVDD(P) Pn 100 kΩ VDD 002aah279 LEDVDD(P) Pn
3.3 V 5 V
Fig 18. Simplified output stage VDD(P) P0 to P7 Configuration register 002aah093 DECODER PMOS_EN0 PMOS_EN1 PMOS_EN2 PMOS_EN3 NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 Output port register Current Control register PMOS_EN[3:0] NMOS_EN[3:0]
Product data sheet Rev. 3 — 18 September 2013 20 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and creates noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time creates ground and supply noise. The output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues without the need of additional external components.
9.3 Power-on reset requirements
In the event of a glitch or data corruption, PCAL6408A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 19 and Figure 20. Table 19 specifies the performance of the power-on reset feature for PCAL6408A for both types of power-on reset. Fig 19. V DD is lowered below 0.2 V or 0 V and then ramped up to VDD Fig 20. V DD is lowered below the POR threshold, then ramped back up to VDD 002aag960 VDD(P) time ramp-up ramp-down (dV/dt)r (dV/dt)f re-ramp-up (dV/dt)rtime to re-ramp when VDD(P) drops below 0.2 V or to VSS td(rst) 002aag961 VDD(P) time ramp-down (dV/dt)f ramp-up (dV/dt)rtime to re-ramp when VDD(P) drops to VPOR(min) − 50 mV td(rst)VI drops below POR levels
[1] Level that V DD(P) can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD <1 s. [2] Glitch width that will not cause a functional disruption when VDD(gl) =0 . 5 VDD(P). how to measure these specifications. 0V . Figure 22 and Table 19 provide more details on this specification. Table 19. Recommended supply sequencing and ramp rates Tamb =2 5 C (unless otherwise noted). Not tested; specified by design.
Product data sheet Rev. 3 — 18 September 2013 22 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
9.4 Device current consumption with internal pull-up and pull-down
The PCAL6408A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. Since these pull-up and pull-down resistors are internal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. The pull-up or pull-down function is selected in register 44h, while the resistor is connected by the enable register 43h. The configuration of the resistors is shown in Figure 9. If the resistor is configured as a pull-up, that is, connected to VDD, a current flows from the VDD(P) pin through the resistor to ground when the pin is held LOW. This current appears as additional IDD upsetting any current consumption measurements. In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH, current flows from the power supply through the pin to the VSS pin. While this current is not measured as part of IDD, one must be mindful of the 200 mA limiting value through VSS. The pull-up and pull-down resistors are simple resistors and the current is linear with voltage. The resistance specification for these devices spans from 50 k with a nominal 100 k value. Any current flow through these resistors is additive by the number of pins held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 26 for a graph of supply current versus the number of pull-up resistors.
[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
- Recommended operating conditions
Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 21. Operating conditions
[1] The package thermal impedance is calc ulated in accordance with JESD 51-7. Table 22. Thermal characteristics Table 23. Static characteristics Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Table 23. Static characteristics …continued Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
[1] All typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 5 V V DD) and Tamb =2 5 C. their default states. After that, VDD(P) must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. [3] The total current sourced by all I/Os must be limited to 80 mA. [4] Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA. [6] Internal pull-up/pull-down resistor disabled. Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Product data sheet Rev. 3 — 18 September 2013 27 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
13.1 Typical characteristics
Fig 23. Supply current versus ambient temperature Fig 24. Standby supply current versus ambient temperature Tamb =2 5 CV DD(P) =5V Fig 25. Supply current versus supply voltage Fig 26. Supply current versus number of I/O held LOW IDD (μA) Tamb (°C) −40 85 6010 35−15 002aag973 VDD(P) = 5.5 V 5.0 V 3.6 V 3.3 V 2.5 V 2.3 V VDD(P) = 1.8 V 1.65 V 600 800 400 1400 IDD(stb) (nA) Tamb (°C) −40 85 6010 35−15 002aag974 VDD(P) = 5.5 V 5.0 V 3.6 V 3.3 V 200 1000 2.5 V 2.3 V 1.8 V 1.65 V IDD (μA) VDD(P) (V) 002aag975 200 400 600 I DD(P) (μA) number of I/O held LOW 08 624 002aah245 Tamb = −40 °C 25 °C 85 °C
Product data sheet Rev. 3 — 18 September 2013 28 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander a. V DD(P) =1 . 6 5V b . V DD(P) =1 . 8V c. V DD(P) =2 . 5V d . V DD(P) =3 . 3V e. V DD(P) =5 . 0V f . V DD(P) =5 . 5V Fig 27. I/O sink current versus LOW-le vel output voltage with CCX.X = 11b VOL (V) 0 0.3 0.20.1 002aaf578 35I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf579 35I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf580 Isink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf581 I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf582 70I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf583 70I sink (mA) Tamb = −40 °C 25 °C 85 °C
Product data sheet Rev. 3 — 18 September 2013 29 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander a. V DD(P) =1 . 6 5V b . V DD(P) =1 . 8V c. V DD(P) =2 . 5V d . V DD(P) =3 . 3V e. V DD(P) =5 . 0V f . V DD(P) =5 . 5V Fig 28. I/O source current versus HIGH-level output voltage with CCX.X = 11b VDD(P) − VOH (V) 0 0.6 0.40.2 002aaf561 I source (mA) Tamb = −40 °C 25 °C 85 °C VDD(P) − VOH (V) 0 0.6 0.40.2 002aaf562 35I source (mA) Tamb = −40 °C 25 °C 85 °C VDD(P) − VOH (V) 0 0.6 0.40.2 002aaf563 I source (mA) Tamb = −40 °C 25 °C 85 °C VDD(P) − VOH (V) 0 0.6 0.40.2 002aaf564 70I source (mA) Tamb = −40 °C 25 °C 85 °C VDD(P) − VOH (V) 0 0.6 0.40.2 002aaf565 I source (mA) Tamb = −40 °C 25 °C 85 °C VDD(P) − VOH (V) 0 0.6 0.40.2 002aaf566 I source (mA) Tamb = −40 °C 25 °C 85 °C
Product data sheet Rev. 3 — 18 September 2013 30 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (1) V DD(P) = 1.8 V; Isink =1 0m A (2) V DD(P) = 5 V; Isink =1 0m A (3) V DD(P) = 1.8 V; Isink =1m A (4) V DD(P) = 5 V; Isink =1m A Isource = 10 mA Fig 29. LOW-level output voltage versus temperature Fig 30. I/O high voltage versus temperature 100 120VOL (mV) Tamb (°C) −40 85 6010 35−15 002aah056 (1) (3) (4) (2) Tamb (°C) −40 85 6010 35−15 002aah057 160 120 200 VDD(P) − VOH (mV) VDD(P) = 1.8 V 5 V
Table 24. I 2C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Figure 31. Table 25. Reset timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Figure 34.
- Parameter measurement information
Table 26. Switching characteristics Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 33. CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
Product data sheet Rev. 3 — 18 September 2013 33 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander a. Interrupt load configuration b. Voltage waveforms CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Fig 32. Interrupt load circuit and voltage waveforms 002aag979 DUT CL = 100 pF RL = 4.7 kΩ INT VDD(I2C-bus) 10000 AD DR 1 AS0 slave address START condition R/W acknowledge from slave 002aag980 8 bits (one data byte) from port A acknowledge from slaveSDA 1 no acknowledge from master data into port data from port DATA 1 DATA 2 INT DATA 2 DATA 1 P STOP condition tv(INT) trst(INT) tsu(D) 12345678SCL 9 ADDRESS trst(INT) A A View A - A INT Pn tv(INT) 0.5 × VDD(I2C-bus) 0.5 × VDD(P) View B - B SCL 0.5 × VDD(I2C-bus)INT R/W A trst(INT) 0.3 × VDD(I2C-bus) 0.7 × VDD(I2C-bus) B B
Product data sheet Rev. 3 — 18 September 2013 34 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander a. P port load configuration b. Write mode (R/W =0 ) c. Read mode (R/W =1 ) CL includes probe and jig capacitance. tv(Q) is measured from 0.7 VDD(I2C-bus) on SCL to 50 % I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Fig 33. P port load circuit and voltage waveforms 002aag981 DUT CL = 50 pF 500 Ω Pn 2 × VDD(P) 500 Ω 002aag982 SCL SDA P0 A tv(Q) 0.3 × VDD(I2C-bus) 0.7 × VDD(I2C-bus) last stable bitunstable data Pn 002aag983 SCL Pn P0 A th(D) 0.3 × VDD(I2C-bus) 0.7 × VDD(I2C-bus) 0.5 × VDD(P) tsu(D)
Product data sheet Rev. 3 — 18 September 2013 35 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander a. SDA load configuration b. P port load configuration c. RESET timing CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. Fig 34. Reset load circuits and voltage waveforms 002aag977 DUT CL = 50 pF RL = 1 kΩ SDA VDD(I2C-bus) 002aag981 DUT CL = 50 pF 500 Ω Pn 2 × VDD(P) 500 Ω SDA SCL 002aag984 trst trec(rst) tw(rst) RESET Pn START trst ACK or read cycle 0.3 × VDD(I2C-bus) 0.5 × VDD(I2C-bus) 0.5 × VDD(P) trec(rst)
Product data sheet Rev. 3 — 18 September 2013 36 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 16. Package outline Fig 35. Package outline SOT403-1 (TSSOP16) 81,7 $ $ $ ES F ' H + ( / / S 4 =\\ZY ș 5()(5(1&(6287/,1( 9(56,21 (8523($1 ,(& -('(& -(,7$ PP R R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 627 02 ES H ș GHWDLO; F Y 0 $ PP VFDOH 76623 SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJH OHDGV ERG\\ZLGWKPP 627 PD[ SLQLQGH[
Product data sheet Rev. 3 — 18 September 2013 37 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Fig 36. Package outline SOT758-1 (HVQFN16) WHUPLQDO LQGH[DUHD $ (KE81,7 \\H F 5()(5(1&(6287/,1( 9(56,21 (8523($1 ,(& -('(& -(,7$ PP H H ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 627 02 Y Z PP VFDOH 627 +94)1 SODVWLFWKHUPDOHQKDQFHGYHU\\WKLQTXDGIODWSDFNDJH QROHDGV WHUPLQDOV ERG\\[[PP PD[ F GHWDLO; \\\\&H H H E % $ H WHUPLQDO LQGH[DUHD H H %Y 0 Z 0 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
Product data sheet Rev. 3 — 18 September 2013 38 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Fig 37. Package outline SOT1161-1 (XQFN16) 5HIHUHQFHV2XWOLQH YHUVLRQ (XURSHDQ SURMHFWLRQ ,VVXHGDWH ,(& -('(& -(,7$ 627 VRWBSR 8QLW PP PD[ QRP PLQ 'LPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG ;4)1 SODVWLFH[WUHPHO\\WKLQTXDGIODWSDFNDJH QROHDGV WHUPLQDOV ERG\\[[PP 627 $ $ E'(HH H // YZ PP VFDOH % $ WHUPLQDO LQGH[DUHD \\&\\ GHWDLO; $ $ WHUPLQDO LQGH[DUHD E H H $&%Y H H
Product data sheet Rev. 3 — 18 September 2013 39 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Fig 38. Package outline SOT1354-1 (XFBGA16) 5HIHUHQFHV2XWOLQH YHUVLRQ (XURSHDQ SURMHFWLRQ ,VVXHGDWH ,(& -('(& -(,7$ 627 VRWBSR 8QLW PP PD[ QRP PLQ 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV ;)%*$ SODVWLFH[WUHPHO\\WKLQILQHSLWFKEDOOJULGDUUD\\SDFNDJH EDOOV $ $ E'(HH H YZ 627 VFDOH PP GHWDLO; EDOO$ LQGH[DUHD H H H H $&%Y &ZE \\&\\ EDOO$ LQGH[DUHD
Product data sheet Rev. 3 — 18 September 2013 40 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 39) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 27 and 28 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 39.
Table 27. SnPb eutectic process (from J-STD-020D) Table 28. Lead-free process (from J-STD-020D)
Product data sheet Rev. 3 — 18 September 2013 42 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. MSL: Moisture Sensitivity Level Fig 39. Temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature
Product data sheet Rev. 3 — 18 September 2013 43 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 18. Soldering: PCB footprints Fig 40. PCB footprint for SOT758-1 (HVQFN16); reflow soldering 627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH 'LPHQVLRQVLQPP 63\\WRW 63[WRW Q63[ Q63\\ VRWBIU RFFXSLHGDUHD VROGHUODQGSOXVVROGHUSDVWH VROGHUODQG VROGHUSDVWHGHSRVLW ,VVXHGDWH $\\ %\\6/\\ 6/[ *\\+\\ 63[ 63\\ 63[WRW 63\\WRW Q63[ Q63\\
Product data sheet Rev. 3 — 18 September 2013 44 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Fig 41. PCB footprint for SOT403-1 (TSSOP16); reflow soldering ',0(16,216LQPP VRWBIU 627 VROGHUODQG RFFXSLHGDUHD )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH $\\%\\*\\ *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\\RXW
Product data sheet Rev. 3 — 18 September 2013 45 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Fig 42. PCB footprint for SOT1161-1 (XQFN16); reflow soldering 627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;4)1SDFNDJH VRWBIURFFXSLHGDUHD VROGHUODQG SODFHPHQWDUHD VROGHUUHVLVWDURXQGFRSSHU VROGHUODQGSOXVVROGHUSDVWH 'LPHQVLRQVLQPP FOHDUDQFHDURXQGRFFXSLHGDUHD î î VROGHUSDVWHGHSRVLWDURXQGFRSSHU VWHQFLOWKLFNQHVV
Table 29. Abbreviations Table 30. Revision history
- Section 2 “Features and benefits”, 17th bullet item: added “XFBGA16”
- Table 1 “Ordering information”: added Type number PCAL6408AEX
- Table 2 “Ordering options”: added Type number PCAL6408AEX
- Added (new) Figure 5 “Pin configuration for 1.6 mm 1.6 mm XFBGA16”
- Added (new) Figure 6 “Ball mapping for 1.6 mm 1.6 mm XFBGA16”
- Table 3 “Pin description”: added column “XFBGA16”
- Table 6 “Command byte”, register “Output port configuration”: – Pointer register bits corrected from “0100 0111” to “0100 1111” (correction to documentation, no functional change to device) – Command byte corrected from “47h” to “4Fh” (correction to documentation, no functional change to device)
- Section 7.4.11 “Output port configuration register (4Fh)”: – register number corrected from “47h” to “4Fh” in Section title (correction to documentation, no functional change to device) – first paragraph, third sentence: register number corrected from “(47h)” to “(4Fh)” (correction to documentation, no functional change to device) – register number corrected from “47h” to “4Fh” in title of Table 18 (correction to documentation, no functional change to device)
- Added (new) Figure 38 “Package outline SOT1354-1 (XFBGA16)” PCAL6408A v.2 20121206 Product data sheet - PCAL6408A v.1 PCAL6408A v.1 20120906 Product data sheet - -
Product data sheet Rev. 3 — 18 September 2013 47 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 21. Legal information
21.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 3 — 18 September 2013 48 of 49 NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 September 2013 Document identifier: PCAL6408A Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 23. Contents