TESDC5V0LC_15 TSC | Alldatasheet

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  • Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) - Meet IEC61000-4-4 (EFT) rating. 40A (5/50ns) - Protects one Bi-directional I/O line - Working Voltage : 5V - Pb free version and RoHS compliant - Packing code with suffix "G" means green compound (halogen-free) - Case: SOD-323 small outline plastic package - High temperature soldering guaranteed : 260°C/10s - Weight: 4.85 ± 0.5 mg - Marking code: AC - Cell Phone Handsets and Accessories - Notebooks, Desktops, and Servers - Keypads, Side Keys, USB 2.0, LCD Displays - Portable Instrumentation - Microprocessor Based Equipment SYMBOL UNIT P PP W TJ , TSTG oC SYMBOL UNIT VRWM V V(BR) V IR μA CJ pF Document Number: DS_S1501014 Version: C15 Junction Capacitance VR = 0 V , f = 1.0 MHz 1.2 Clamping Voltage IPP = 1 A VC -9 . 8 VIPP = 8 A - 18.3 Reverse Breakdown Voltage IR = 1 mA 6- Reverse Leakage Current VR = 5 V -5 Junction and Storage Temperature Range -55 to +150 PARAMETER MIN MAX Reverse Stand-Off Voltage - 5 Peak Pulse Power (tp=8/20μs waveform) 350 ESD per IEC 61000-4-2 (Air) VESD ± 15 KVESD per IEC 61000-4-2 (Contact) ± 8 - Terminal: Matte tin plated, lead free., solderable per MIL-STD-202, Method 208 guaranteed

APPLICATIONS

MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise noted) PARAMETER VALUE TESDC5V0LC Taiwan Semiconductor Bi-directional ESD Protection Diode

FEATURES

(TA=25°C unless otherwise noted) Document Number: DS_S1501014 Version: C15 TESDC5V0LC Taiwan Semiconductor RATINGS AND CHARACTERISTICS CURVES 0.01 0.1 0.1 1 10 100 1000 Peak Pulse Power Ppp (KW) Fig. 1 Non-Repetitive Peak Pulse Power VS. Pulse Time Pulse Duration (μs) 100 110 0 5 10 15 20 25 30 Percent of IPP Time (us) Fig. 2 Pulse Waveform td = Ipp / 2 100 120 0 20 40 60 80 100 120 140 160 180 Power Rating (%) Ambient Temperature(oC) Fig. 3 Admissible Power Dissipation Curve 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345 Normalized Capacitance (pF) Reverse Voltage (V) Fig. 4 Typical Junction Capacitance f = 1.0 MHz Waveform parameters: tr = 8 μs , td = 20 μs e-1 0 5 10 15 20 25 30 Clamping Voltage (V) Peak Pulse Current (A) Fig. 5 Clamping Voltage VS. Peak Pulse Current Waveform parameters: tr = 8 μs , td = 20 μs

PACKAGE OUTLINE DIMENSIONS Min Max Min Max A 1.150 1.400 0.045 0.055 B 2.300 2.700 0.091 0.106 C 0.250 0.450 0.010 0.018 D 1.600 1.800 0.063 0.071 E 0.800 1.000 0.031 0.039 F 0.050 0.177 0.002 0.007 G H - 0.100 - 0.004 SUGGEST PAD LAYOUT G X Y Note: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts may vary depending on application. APPLICATION INFROMATION - Designed to protect one data, I/O, or power supply line - Designed to protect sensitive electronics from damage or latch-up due to ESD - Designed to replace multilayer varistors (MLVs) in portable applications - Offers superior electrical characteristics such as lower clamping voltage and no device degradation when compared to MLVs - The combination of small size and high ESD surge capability makes them ideal for use in portable applications CIRCUIT BOARD LAYOUT RECOMMENDATIONS - Good circuit board layout is critical for the suppression of ESD induced transients - Place the ESD Protection Diode near the input terminals or connectors to restrict transient coupling - Minimize the path length between the ESD Protection Diode and the protected line - Minimize all conductive loops including power and ground loops - The ESD transient return path to ground should be kept as short as possible Document Number: DS_S1501014 Version: C15 0.45 0.018 1.52 0.060 0.59 0.023 2.70 0.106 DIM. Unit (mm) Unit (inch) 0.475 REF 0.019 REF DIM. Unit (mm) Unit (inch) Min Min TESDC5V0LC Taiwan Semiconductor Small Signal Product ORDER INFORMATION (EXAMPLE) SOD-323 TESDC5V0LC RRG Green compound code Packing code Part no. B A E D C F G H

assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied,to any intellectual property rights is granted by this document. Except as provided in TSC's terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or seling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. Document Number: DS_S1501014 Version: C15 TESDC5V0LC Taiwan Semiconductor Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf,