TESD24VS2BT TSC | Alldatasheet

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Technical content

B T Tai wan Semiconductor Version: A 805 200W 24V ESD Protection Array

FEATURES

Small package for use in portable electronics Meet IEC61000 2(ESD) kV(air) , kV(contact) Moisture sensitivity level: level 1, per J STD 020 Compliant to RoHS d irective 2011/65/EU and in accordance to WEEE 2002/96/EC Halogen free according to IEC 61249

APPLICATIONS

S p eed Line: USB 2.0 / VGA/ DVI /SDI /HDMI Touch Panel Battery Management System POE PD MECHANICAL DATA Case: SOT Molding compound meets UL 94 V 0 flammability rating Terminal: Matte tin plated leads, solderable per J STD 002 Meet JESD 201 class 1A whisker test Weight: mg (approximately) Marking code on the device: W3 KEY PARAMETERS P ARAMETER VALUE UNIT P PP M 200 W I PP A V WM V V C at I PP A V Package SOT ABSOLUTE M AXIMUM RATINGS T A unless otherwise noted P ARAMETER S YMBOL TESD24VS2BT UNIT Rated random recurring peak Impulse power dissipation tp=8/20μs waveform) P PP M 200 W P eak impulse current (tp=8/20μs waveform) I PP A ESD per IEC 61000 2 (Air) ESD per IEC 61000 2 (Contact) V ESD K V Junction t emperature range T J to + 150 Storage temperature range T STG to + 150

B T Tai wan Semiconductor Version: A 805 ELECTRICAL SPECIFICATIONS T A = 25 unless otherwise noted PARAMETER CONDITIONS SYMBOL MIN T YP M AX U NIT Reverse breakdown voltage I R mA V (BR) 25.4 V R ated working standoff voltage V WM V R everse current V R V I R n A Clamping voltage I PP 1 A V C V Clamping voltage I PP A V C V Junction capacitance

1 MHz

V R V C J p F Notes: Pulse test with PW= ms tp=8/20μs waveform

ORDERING INFORMATION

K / 7" Reel

B T Tai wan Semiconductor Version: A 805 CHARACTERISTICS CURVES T A 25°C unless otherwise noted) Fig. 8/20μ s pulse waveform according to IEC 61000 Fig.

2 ESD pulse waveform

Fig. Typical Junction Capacitance 120 100% Ipp ; 8 μ s e t 50% Ipp ; 20 μ s 100 110 -10 t r =0.7ns to 1ns 0.0 2.0 4.0 6.0 8.0 10.0 P eak I mpulse C urrent I PP (%) t ( μ Junction Capacitance C J (pF) Reverse Voltage V R (V) t(ns) P eak I mpulse C urrent I PP (%)

B T Tai wan Semiconductor Version: A 805 PACKAGE OUTLINE DIMENSION SUGGEST PAD LAYOUT SOT DIM. Unit (mm) Unit (inch) Min Max Min Max A 0.1 0.12 B 0.04 0.05 C 0.3 0.51 0.01 0.020 D 1.78 2.04 0.070 0.080 E 2.6 0.0 0.10 F 0.89 0.035 0.0 DIM. Unit (mm) Unit (inch) Typ. Typ. Z 2.9 0.114 X 0.8 0.031 Y 0.90 0.035 C 2.0 0.079 E 0.053

B T Tai wan Semiconductor Version: A 805 Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product descrip tion only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implie d warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown her ein are not designed for use in medical, life saving, or life sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such impro per use or sale.