TEA2376DT1

NXP Semiconductors

Digital configurable interleaved PFC controller Rev. 1 - 10 August 2023

Manufacturer: NXP Semiconductors

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PDF pages: 46

Technical content

Datasheet sections

1 General description
2 Features and benefits
2.1 Distinctive features
2.2 Green features
2.3 Protection features
3 Applications
4 Ordering information
5 Marking
6 Block diagram
7 Pinning information
7.1 Pinning
7.2 Pin description
8 Functional description
8.1 Start-up and supply voltage
8.2 PFC start-up
8.3 Brownin and brownout
8.4 Overcurrent protection SNSCUR pin
8.5 Overcurrent protection SNSSRC pin
8.6 Gate drivers
8.7 Antialiasing filters
8.8 Power good output
8.9 Power factor correction (PFC) regulation
8.9.1 Power factor and THD
8.9.2 PFC switching frequency
8.9.3 Frequency limitation
8.9.4 Multimode operation (DCM/QR)
8.10 Output voltage regulation
8.10.1 Output voltage control loop
8.10.2 Notch filter
8.11 Current control
8.11.1 Current limiter
8.11.2 Input voltage-dependent current limit
8.12 CCM operation
8.13 Phase control
8.14 Valley switching and demagnetization
8.15 Phase shedding
8.16 Burst mode
8.16.1 Burst mode with VCC pin control
8.16.2 Burst mode BURST pin control
8.16.3 Follow mode burst operation
8.16.4 Ripple mode burst operation
8.16.5 SNSBOOST pull-up
8.16.6 Autonomous mode burst operation
8.16.7 Burst mode soft start/soft stop
8.17 Protections
8.17.1 Undervoltage protection VCC (UVP VCC)
8.17.2 Overvoltage protection VCC (OVP VCC)
8.17.3 MTP fail
8.17.4 Undervoltage protection mains (brownout
8.17.5 Internal overtemperature protection (OTP
8.17.6 External overtemperature protection (OTP
8.17.7 Short-circuit protection/fast disable (SCP
8.17.8 Overvoltage protection boost voltage (OVP
8.17.9 Overvoltage protection measured via AUX
8.17.10 Overcurrent protection, inrush protection
8.17.11 Current sense resistor short protection
8.17.12 PFC coil short protection (SCP coil,
8.17.13 PFC output diode short protection (SCP
8.17.14 Phase fail protection (AUX1/AUX2 pin)
8.17.15 Overvoltage protection mains (OVP mains)
8.17.16 Latched, safe restart, or latched after safe
8.17.17 Fast latch reset
8.18 Settings
8.18.1 General settings
8.18.1.1 Protection register
8.18.1.2 Read lock
8.18.1.3 Write lock
8.18.1.4 Reset to the default values
8.18.1.5 Customer MTP code
8.18.2 PFC settings
8.18.2.1 Start-up time
8.18.2.2 Mains measurement
8.18.2.3 Number of mains resistors
8.18.2.4 PFC minimum and maximum frequency
8.18.3 Protection settings
8.18.3.1 Safe restart time
8.18.3.2 Fast latch reset delay time
8.18.3.3 Fast disable
8.18.3.4 Brownin/brownout level
8.18.3.5 VCC OVP
8.18.3.6 Internal OTP level
8.18.3.7 SNSCUR OCP level
8.18.3.8 PFC maximum on-time
8.18.3.9 Coil short protection
8.18.3.10 Output diode short protection
8.18.3.11 Output OVP
8.18.3.12 Valley detection timeout
8.18.3.13 PFC minimum off-time in CCM operation
8.18.3.14 PFC minimum secondary stroke time
9 Limiting values
10 Recommended operating conditions
11 Thermal characteristics
12 Characteristics
13 Application information
14 Package outline
15 Appendix: Ringo parameter settings
16 Revision history
17 Legal information

Digital configurable interleaved PFC controller Rev. 1 — 10 August 2023 Product data sheet

1 General description

The TEA2376DT is a digital configurable two-phase interleaved PFC controller for high-efficiency power supplies. The PFC operates in discontinuous conduction mode or quasi-resonant mode with valley switching to optimize efficiency. The TEA2376DT enables the building of an interleaved power factor controller, which is easy to design with a low external component count. The TEA2376DT is available in a low profile and narrow body-width SO14. The digital architecture of the TEA2376DT is based on a high-speed configurable hardware state machine ensuring reliable real-time performance. To meet specific application requirements, many operation and protection settings of the PFC controller can be adjusted by loading new settings into the device with I2C during power supply development. For a high power factor and a low THD, input current shaping is used. A notch filter allows a faster transient response by suppressing the mains frequency component in the regulation loop, while maintaining a low THD. For low-load operation with good efficiency, phase shedding and burst mode operation are included. To meet the efficiency and standby power regulations of Energy Star, the Department of Energy, the Eco-design directive of the European Union, the European Code of Conduct, and other guidelines, the power consumption of the IC is reduced in burst mode operation. The TEA2376DT contains many protections, like internal and external overtemperature protection (OTP), overcurrent protection (OCP), dual overvoltage protection (OVP), inrush current protection (ICP), pin open, pin short protection, and phase fail protection. The protections can be configured independently and using programmable parameters. The TEA2376DT allows an easy to design, highly efficient, and reliable interleaved PFC, for power levels up typically to 1000 W1. 1 For high switching frequency and high power applications, IC package thermal limitations require attention.

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

2 Features and benefits

2.1 Distinctive features

Interleaved PFC controller in an SO14 package
Programmable phase shedding and burst mode operation
Dual output over voltage protection
Inrush current protection
High power factor (PF) and low total harmonic distortion (THD), also at high input voltages
Many parameters can be configured during evaluation with the use of a user-friendly graphical user interface (GUI)
Good phase control over full input voltage range
Low audible noise
Power good output and a burst mode input pin
Live monitoring of (internal) IC status values over time with the help of the user-friendly GUI similar to oscilloscope reading
I2C communication while in operation

2.2 Green features

Valley/zero voltage switching for minimum switching losses
High efficiency from high load to medium load and low load by phase shedding and burst mode operation

2.3 Protection features

Protections can independently be set to latched, safe restart, or latched after several attempts to restart
Dual output overvoltage protection (OVP)
Supply undervoltage protection (UVP) and overvoltage protection (OVP)
Internal and external overtemperature protection (OTP)
Overcurrent protection (OCP)
Inrush current protection (ICP)
Brownin/brownout protection
Open and short pin protection
Coil short protection
Output diode short protection
Open control loop protection
Phase fail protection TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

3 Applications

HD and U-HD television
Server
Desktop and all-in-one PCs
Gaming consoles
High-power adapter
5G supplies
Home audio

4 Ordering information

Table 1. Ordering information

5 Marking

6 Block diagram

7 Pinning information

7.1 Pinning

Figure 2. TEA2376DT pin configuration (SOT108-1)

7.2 Pin description

8 Functional description

8.1 Start-up and supply voltage

8.2 PFC start-up

At start-up, the PFC output voltage increases according to an RC curve (see Figure 3). Figure 3. PFC start-up for application with one mains resistor (applications with two mains resistors start one half value, avoiding audible noise. The RC time value can be programmed via the MTP. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

8.3 Brownin and brownout

When the (filtered) mains-sense peak voltage exceeds the brownin level, the IC leaves the brownout state on the second mains peak. If no AC mains is detected, the brownout state is left after a timeout period when the (filtered) mains-sense peak voltage exceeds the brownin level. When the (filtered) mains-sense peak voltage drops to below the brownin level minus the hysteresis, Ibo(hys), for at least the brownout delay time, td(det)bo, the IC enters the brownout state. When the PFC stops switching, a soft stop is made to prevent audible noise and overshoots on the rectified mains voltage caused by the energy in the differential mode filter inductor.

8.4 Overcurrent protection SNSCUR pin

The SNSCUR pin provides an overcurrent protection. The protection level is −150 mV for single-phase operation and −300 mV for two-phase operation (Vocp(SNSCUR)). To prevent false triggering, a blanking time is included at the start of each switching cycle of either phase. The overcurrent protection circuit is also used for detection and protection for a shorted PFC coil condition.

8.5 Overcurrent protection SNSSRC pin

The SNSSRC pin can be connected to ground. It can also be used as an additional overcurrent protection by connecting it to an additional current sense resistor in series with the sources of the external MOSFETs. The protection level is 125 mV (Vocp(SNSSRC)). To prevent false triggering, a blanking time is included at the start of each switching cycle of either phase. This overcurrent protection circuit is primarily intended for detection and protection for a shorted PFC output diode. Because the SNSSRC pin is also used as power ground for the internal gate drivers, the overcurrent signal is blanked when the gates of the external MOSFETs are discharged. To prevent damage to the IC due to inductive voltage spikes, a series resistor must be inserted between the SNSRC pin and the current sense resistor.

8.6 Gate drivers

The gate drivers can source 1.2 A (Isource(peak)) and sink 1.9 A (Idch(GATEx)). To prevent disturbance of the internal signals connected to the ground pin, the discharge current from the external MOSFETs is through the SNSSRC pin. After the external MOSFET is turned off, the driver is connected to the ground pin to prevent that the driver signals cross couple via the SNSSRC pin.

8.7 Antialiasing filters

On the input of the internal ADCs, an antialiasing filter is added to restrict the bandwidth of the signal. The adding of the antialiasing filter complies with the Nyquist-Shannon sampling theorem over the band of interest.

8.8 Power good output

A power good signal that indicates if the output voltage of the PFC exceeds an MTP programmable minimum level, Vstart(SNSBOOST), is provided. The power good signal also gives an indication about if the controller is operating and not in a protection state. This output can be used to control a downstream converter that is connected to the output of the PFC or as signal to a microcontroller. When the brownout is activated and the MTP programmable mask bit for this function is set, the power good signal is removed. It is also removed when VSNSBOOST drops to or is pulled to below a minimum level and the MTP programmable mask bit for this function is set. The POWERGOOD pin is an open-drain output. The polarity of this signal is programmable. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

8.9 Power factor correction (PFC) regulation

8.9.1 Power factor and THD

To achieve a high power factor (PF) and low total harmonic distortion (THD), the input current of the power supply must follow the mains input voltage. Because the filter capacitances cause a shift of 90° between the mains current and the mains voltage, the input filter disrupts PF and THD. To improve PF and THD, the average PFC current is in accordance with a shifted sine wave (see Figure 4). TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

Figure 4. Shifted sine wave current (IPFC), the mains current approaches a sine waveform. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

requested to the output, the amplitude of the shifted current sine wave increases.

8.9.2 PFC switching frequency

lower due to valley switching. Figure 5. Switching frequency current increases, the switching frequency increases as well until it reaches the maximum level. pin inputs connect via a resistor to the auxiliary winding of the transformers. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.9.3 Frequency limitation

To avoid audible noise, the minimum frequency is limited to fsw(PFC)min. To ensure correct control of the PFC MOSFET under all circumstances, the minimum off-time is limited. The minimum and maximum frequency limitation values are adjustable.

8.9.4 Multimode operation (DCM/QR)

Figure 6. Multimode operation pin inputs connected via a resistor to the auxiliary windings of the transformers.

8.10 Output voltage regulation

voltage with an accurate trimmed reference voltage (Vreg(SNSBOOST) at continuous operation). TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.10.1 Output voltage control loop

Figure 7. Transfer curve of digital PI controller harmonic reduction (MHR) requirements may be hard to meet. The mains input voltage for the loop compensation is measured via the SNSMAINS pin. increase for overshoots tracks the RC start-up curve. An MTP setting can disable the gain increase for undershoots. Figure 8. Gain increase limits TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.10.2 Notch filter

two times the measured mains frequency. Figure 9. Transfer of notch filter for 50 Hz mains An MTP memory setting can disable the notch filter.

8.11 Current control

desired PFC current. The gain must be adapted according to the sense resistor and the PFC inductor value. The desired PFC current can be limited in specific conditions, which are described Section 8.11.1. block for the two phases adapts the t-on signal (see Section 8.13). Figure 10. Current control

8.11.1 Current limiter

input voltage is close to the output voltage, the current limit is automatically activated. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.11.2 Input voltage-dependent current limit

can be set using an MTP parameter. The current limiter can also be disabled.

8.12 CCM operation

8.13 Phase control

the same while regulating the phase difference, one on-time is reduced when the other on-time is increased. Figure 11. Phase control

8.14 Valley switching and demagnetization

the AUX1 and AUX2 pins. The ringing amplitude can change due to damping or at different input voltages. demagnetization level plus the hysteresis for 4 repetitive switching cycles, valley switching is enabled again. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.15 Phase shedding

constant mains input current. continuous toggling between single-phase operation and two-phase operation if loads vary, hysteresis is added. Figure 12. Phase shedding

8.16 Burst mode

Burst-mode operation is included in the TEA2376DT to improve the light load efficiency.

Follow mode
Ripple mode
Autonomous mode Burst mode can be programmed to single-phase operation only or independent of the phase-shedding mechanism. Burst mode operation can be controlled externally via the VCC pin, the SNSBOOST pin, or the BURST pin, depending on the programmed settings. To prevent irregular burst-mode operation with repetitive load steps in autonomous mode, the entering of burst mode can be delayed with a programmable delay. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

To prevent audible noise, entering and exiting a burst active cycle is done with a soft start and a soft stop.

8.16.1 Burst mode with VCC pin control

If VCC-controlled burst mode is enabled in the MTP settings, the VCC pin voltage controls the burst mode. mode with VCC control operates in follow mode or ripple mode.

8.16.2 Burst mode BURST pin control

burst mode. When the BURST pin voltage exceeds 1.34 V, Vburst(u), continuous PFC switching is enabled. continuous switching, nonburst mode state.

8.16.3 Follow mode burst operation

a value exceeding the burst threshold level. the burst threshold level and the SNSBOOST pin exceeds 2.475 V (Vreg(SNSBOOST) at burst mode operation). Figure 13. VCC pin controlled follow burst mode 2 The polarity of the BURST pin is programmable. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Figure 14. BURST pin controlled follow burst mode

8.16.4 Ripple mode burst operation

level. The SNSBOOST ripple voltage amplitude can be selected using an MTP parameter. criterion equals the follow mode. Figure 15. VCC pin controlled ripple mode Figure 16. BURST pin controlled ripple burst mode 3 The polarity of the BURST pin is programmable. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.16.5 SNSBOOST pull-up

(typically about 12 V PFC output voltage drop), the TEA19161 releases the SNSBOOST pin.

2.50 V regulation

Figure 17. Follow mode and ripple mode SNSBOOST pull-up burst mode control

8.16.6 Autonomous mode burst operation

SNSBOOST pin has reached 2.475 V and the output power is below the programmed burst level.

3 Hz filter)

Figure 18. Autonomous burst mode operation

8.16.7 Burst mode soft start/soft stop

8.17 Protections

Table 4 gives an overview of the available protections. Table 4. Protections overview TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Table 4. Protections overview...continued [1] Can be selected using an MTP parameter.

8.17.1 Undervoltage protection VCC (UVP VCC)

VCC supply voltage exceeds its start level Vstart(VCC), the system restarts.

8.17.2 Overvoltage protection VCC (OVP VCC)

The voltage on the VCC pin is continuously monitored via an internal analog-to-digital converter. triggered. The VCC overvoltage protection level and the delay time can be selected using an MTP parameter.

8.17.3 MTP fail

To restart the system after 4 failed MTP reads, a brownout/brownin cycle is required. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

8.17.4 Undervoltage protection mains (brownout mains)

Figure 19. Mains and external OTP management resistor can be used connected to L or N. The value and the number of mains resistors must be set in MTP. influence the mains measurement. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller The TEA2376DT measures the SNSMAINS voltage via an analog-to-digital converter for brownin and brownout detection. The mains voltage amplitude, measured at t = t2, is stored and also used for the mains compensation. To prevent that the PFC operates at very low mains input voltages, the PFC stops switching with a soft stop when the measured mains voltage drops to below the brownout level (Ibi − Ibo(hys)). When the mains voltage exceeds the brownin level (Ibi), the PFC restarts with a soft start. To avoid that the system is interrupted during a short mains interruption, a delay can be set before the brownout function is active. The levels and delay can be selected using MTP parameters.

8.17.5 Internal overtemperature protection (OTP int)

An accurate internal temperature protection is provided in the circuit. When the junction temperature exceeds the thermal shutdown temperature (Totp), the converter stops switching. The internal OTP can be programmed as either latched or safe restart.

8.17.6 External overtemperature protection (OTP ext)

To measure a temperature in the application with an external NTC, the SNSMAINS pin is connected to an NTC resistor in series with a (low leakage) diode. Using a low leakage diode like BAS416 is essential because the forward voltage drop of a fast recovery diode can be too low causing an inaccurate mains measurement. During the NTC measurement, the 10kΩ/20kΩ resistor is disconnected from the SNSMAINS pin and the internal current source is switched on. After a settling time, the SNSMAINS pin voltage is measured via the analog-to- digital converter. The actual value of the resistance of the NTC resistor is determined in a search loop: If the NTC has a low resistance, the measured value will be low and for the next NTC measurement the current sourced from the SNSMAINS pin will be increased. If the NTC has a high resistance, the measured value will be high and for the next NTC measurement the current sourced from the SNSMAINS pin will be decreased. When the measured voltage is within the targeted range of 1.1 V to 2.4 V, the current is not changed anymore. The measured NTC resistance value is used to determine if the external temperature is within the specified maximum value. The current from the 10 MΩ/20 MΩ resistor connected to the mains is compensated. An MTP parameter sets the maximum allowed external temperature. The MTP parameter sets the maximum allowed conductance (=1/resistance). Also the delay time before a protection is triggered when an overtemperature is detected (td(otp)), can be set with an MTP parameter. The measurement is done at the peak of the input mains voltage or, if no AC mains is detected, every 100 ms. The SNSMAINS pin outputs a current and measures the pin voltage after 350 μs settling time. In low-power mode, the settling time is extended to 450 μs (tdet(NTC)) to match the internal ADC that is also operating in low power consumption mode. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

8.17.7 Short-circuit protection/fast disable (SCP SNSBOOST)

The PFC does not start switching until the voltage on the SNSBOOST pin exceeds Vstart(scp). This function acts as short-circuit protection for the boost voltage. When the SNSBOOST pin is shorted to ground or the SNSBOOST upper resistor of the divider is disconnected, this protection inhibits switching. This function can also be used as a fast disable. If this pin is shorted to ground via an external MOSFET, the system either stops switching or enters the protection mode followed by a safe restart protection or a latched protection. In this way, an additional external protection can be added or the SNSBOOST pin can be used as an enable/disable function of PFC operations.

8.17.8 Overvoltage protection boost voltage (OVP SNSBOOST)

To prevent output overvoltage during load steps and mains transients, a PFC output overvoltage protection circuit is built in. When the voltage on the SNSBOOST pin exceeds the Vovp(SNSBOOST) level, switching of the power factor correction circuit is inhibited. When the SNSBOOST pin voltage drops to below the regulation level (Vreg(SNSBOOST)) again, the switching of the PFC recommences.

8.17.9 Overvoltage protection measured via AUX pins (OVP AUX)

If the SNSBOOST pin does not provide overvoltage information on the PFC output voltage, a second overvoltage protection is provided via the AUX pins. During the primary and secondary stroke, the currents flowing out of and into the AUX pins are monitored. If the sum of the currents of the primary stroke and secondary stroke exceeds the programmable overvoltage level, a protection is triggered after a programmable number of switching cycles. The OVP level, Vovp(AUXx)(p-p), can be programmed.

8.17.10 Overcurrent protection, inrush protection (OCP SNSCUR)

The PFC current is measured via an external sense resistor (RSENSE) connected to the SNSCUR pin (see Figure 21). If the voltage drops to below Vocp(SNSCUR), the PFC MOSFET is turned off. It resumes switching at the next cycle, if the voltage at the SNSCUR is above the Vocp(SNSCUR) level. The SNSCUR overcurrent protection also prevents the PFC MOSFET from turning on during an inrush situation. To ensure that the OCP level is not exceeded due to disturbance caused by a turn-on of the PFC MOSFET, the OCP level is filtered via an internal 3 MHz filter.

8.17.11 Current sense resistor short protection (SCP SNSCUR)

To detect a (partially) shorted current sense resistor, the SNSCUR information is compared to the information retrieved from the AUX pins. If the current sense resistor is (partially) shorted, a protection is triggered after a programmable number of cycles and if the deviation is too great and the current is above a minimum level.

8.17.12 PFC coil short protection (SCP coil, SNSCUR pin)

If the PFC coil is shorted, the overcurrent protection on the SNSCUR pin is triggered continuously. To avoid overheating, the system enters the protection state when the OCP is continuously triggered for a selectable number of switching cycles.

8.17.13 PFC output diode short protection (SCP diode)

To enable the output diode short protection, a resistor must be placed in series with the source of the external MOSFETs to ground. To protect the IC against currents caused by parasitic inductance in the MOSFET current TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

triggered for a selectable number of switching cycles.

8.17.14 Phase fail protection (AUX1/AUX2 pin)

pins is compared. If deviations greater than a programmable threshold are detected, a protection is triggered.

8.17.15 Overvoltage protection mains (OVP mains)

may increase due to (stray) capacitance across the rectifier bridge diodes.

8.17.16 Latched, safe restart, or latched after safe restart

When a protection is set to be a latched protection, the system stops switching when this protection is triggered. below the latch-reset level (Vrst(VCC)). time (td(restart)). This safe restart time is the same for all protection functions. It can be set using MTP parameter. again within a specific time, it latches. Figure 20. Latch after safe restart again, the counter is increased. If the counter reaches the number as set with a parameter, the system latches. If the protection is not triggered within 65 seconds (trst(cnt)restart), the counter is reset. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

8.17.17 Fast latch reset

If a protection is triggered, the system enters the protection state. To reset a latched protection, the mains voltage can be kept below the brownout level for a specified time. This fast latch reset functionality is useful during production testing. The time before reset (td(flr)) can be set using a parameter. Resetting of a latched protection in the TEA19161 LLC downstream converter can be done by enabling the option of a fast latch reset pulse on the common SNSBOOST node. After the brownout and a delay time, the TEA2376DT forces a 2 V pulse (Vpu(rst)SNSBOOST) of 200 μs (tpu(rst)SNSBOOST)) on the SNSBOOST pin when the brownin level has been exceeded again. The TEA19161 recognizes this fast latch reset pulse and resets the latched protection.

8.18 Settings

The TEA2376DT has an internal MTP memory where different settings can be programmed. Disclaimer: The MTP parameter settings can be changed using the “Ringo" GUI software of NXP Semiconductors. Before the user can change any MTP parameters using the GUI, the terms and conditions in the start-up pop-up screen must be accepted.

8.18.1 General settings

8.18.1.1 Protection register

When the TEA2376DT triggers a protection, the protection information is stored and can be read via I2C. The protection information can be read or cleared using the Ringo GUI.

8.18.1.2 Read lock

To verify settings and for debugging, the MTP memory can be read if the read-lock bit is not programmed. When the read-lock bit in the MTP memory is set, MTP memory is protected from reading. Using the MTP erase function also resets the read-lock bit.

8.18.1.3 Write lock

To prevent that the MTP memory is overwritten accidentally, a write-lock bit can be set. Using the MTP erase function also resets the read-lock bit.

8.18.1.4 Reset to the default values

When the MTP memory is reset, all parameter bits are set to a default value. The default values are suitable for the reference application to work properly.

8.18.1.5 Customer MTP code

If the read-lock bit is set, the content of the MTP memory is unreadable. To still identify the customer MTP coding version, a customer code can be programmed. The read-lock bit does not mask this customer code. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

8.18.2 PFC settings

8.18.2.1 Start-up time

time, the PFC output voltage follows an RC curve until the target output voltage is reached.

8.18.2.2 Mains measurement

The SNSMAINS input impedance that can be chosen is 10 kΩ for 10 MΩ external resistors to the mains or 20 kΩ for 20 MΩ external resistors to the mains. The input resistance value is set with an MTP setting.

8.18.2.3 Number of mains resistors

To achieve the lowest no-load input power, a single mains sense resistor can be used. If continuously measuring the mains voltage is necessary, two mains resistors can be used. For proper functionality, the resistor value and number of resistors in the application are required to correspond to the IC MTP settings.

8.18.2.4 PFC minimum and maximum frequency

The minimum switching frequency of the PFC (fsw(PFC)min) can be set within a range from 25 kHz to 80 kHz. The maximum switching frequency (fsw(PFC)max) can be set within a range from 75 kHz to 300 kHz.

8.18.3 Protection settings

8.18.3.1 Safe restart time

When the system is in protection mode and the triggered protection is programmed as safe restart, it restarts after a safe-restart time (td(restart)). This time can be set at different values ranging from 0.5 s to 10 s. It is applicable for all related protections.

8.18.3.2 Fast latch reset delay time

When the system does not detect a mains voltage for a programmed period, it assumes that the mains is disconnected and resets all protections. When the mains voltage exceeds the brownin level again, the system restarts. The delay between detecting a brownout (td(flr); including the brownout delay time) and resetting all protections can be programmed to different values ranging from 0 s to 10 s.

8.18.3.3 Fast disable

When the SNSBOOST voltage is pulled below the Vstop(scp) level, the system stops switching. When the voltage on the SNSBOOST pin exceeds the Vstart(scp) again, level switching resumes. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

8.18.3.4 Brownin/brownout level

For the brownin level (Ibi), several values can be selected ranging from 67 V (AC) to 185 V (AC). For the hysteresis between the brownin and brownout level (Ibo(hys)), several values can be selected from 2 V (AC) to 17 V (AC). The given values depend on the resistor values in the application and their tolerances. When the mains voltage is below the brownout period for a time, the system enters the brownout state. For the time (td(det)bo), several values can be selected ranging from 50 ms to 1.2 s.

8.18.3.5 VCC OVP

The VCC OVP limit (Vovp(VCC)) can be set from 10 V to 25 V in steps of 1 V steps. The delay until protection (td(ovp)VCC)) can be set to 10 μs, 50 μs, 100 μs, 500 μs, 1000 μs, 5000 μs, or 10,000 μs. This function can also be disabled. If VCC exceeds 25 V, the protection is triggered without delay.

8.18.3.6 Internal OTP level

The internal OTP (Totp) is fixed at 150 °C. When the internal OTP is triggered, it follows the same response as selected for the external OTP, either latched, safe restart, or latched after safe restart.

8.18.3.7 SNSCUR OCP level

The PFC OCP level is fixed to Vocp(SNSCUR)(two-phase) or Vocp(SNSCUR)(single-phase). It depends on if the converter runs in one-phase operation or two-phase operation. The corresponding current value can be selected using the external sense resistor.

8.18.3.8 PFC maximum on-time

The maximum on-time of the PFC equals 1 / minimum frequency. The minimum frequency (fsw(pfc)min) set with the MTP defines the minimum frequency.

8.18.3.9 Coil short protection

When the PFC continuously triggers the SNSCUR OCP for a selectable number of switching cycles, the system enters the protection state. The number of switching cycles can be set to 500 cycles, 2500 cycles, 5000 cycles, or 12,500 cycles. This function can also be disabled.

8.18.3.10 Output diode short protection

When the PFC continuously triggers the SNSSRC OCP for a selectable number of switching cycles, the system enters the protection state. The number of switching cycles can be set to 500 cycles, 2500 cycles, 5000 cycles, or 12,500 cycles. This function can also be disabled.

8.18.3.11 Output OVP

The PFC output voltage is measured via the SNSBOOST pin and the AUX pins. For the OVP at the When an OVP is detected at the SNSBOOST pin, the PFC stops switching. When its voltage drops below the regulation level, switching continues. For the OVP at the AUX pins (Vovp(AUXx)(p-p)), the following values can be selected: 573 μA, 606 μA, 639 μA, and 671 μA. To avoid false triggering, filtering is added. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller The response of an OVP at the AUX pins can be latched, safe restart, or latched after safe restart. This function can also be disabled.

8.18.3.12 Valley detection timeout

When the PFC MOSFET is off and the current through the PFC coil becomes zero, the coil is demagnetized. Normally, shortly after the demagnetization, the drain voltage starts to ring and a valley is detected. When the system detects demagnetization but does not detect a valley shortly after, the ringing is too small to detect a valley. A valley detection timeout is selected. The values can be: 2 μs, 3 μs, 5 μs, or 7 μs.

8.18.3.13 PFC minimum off-time in CCM operation

To ensure a minimum off-time of the drivers and a stable switching operation, a minimum off-time of the PFC driver output can be selected. The available values are 500 ns, 750 ns, 1000 ns, or 1500 ns.

8.18.3.14 PFC minimum secondary stroke time

To avoid false triggering of the demagnetization and valley detection, a minimum secondary stroke of the PFC driver output can be selected using an MTP parameter. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

9 Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Table 5. Limiting values TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

10 Recommended operating conditions

Table 6. Recommended operating conditions

11 Thermal characteristics

93 K/W

63 K/W

12 Characteristics

[1] Available when enabled via MTP modification. [2] Covered by correlating measurement. [3] As the minimum limit determines the application design, the maximum limit is not relevant. Figure 21. Application diagram TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.

Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

15 Appendix: Ringo parameter settings

1 VCC OVP mtp_vcc_ovp OK - 0

2 AUX OVP mtp_aux_ovp OK - 0

3 SNSBOOST short mtp_snsboost_short OK - 0

4 SNSMAINS OVP mtp_mains_ovp OK - 0

5 SNSSRC OCP mtp_snssrc_ocp OK - 0

6 SNSCUR OCP mtp_snscur_ocp OK - 0

7 SNSCUR short mtp_snscur_short OK - 0

8 DIFF PHASE mtp_diff_phase_fail OK - 0

9 POSAUX mtp_posaux_fail OK - 0

10 NEGAUX mtp_negaux_fail OK - 0

11 External OTP mtp_eotp OK - 0

12 Internal OTP mtp_iotp OK - 0

13 MTP read failure mtp_read_fail OK - 0

16 I2C ending delay on GATE mtp_i2c_mode_to_sel 100 ms 0

17 Protection register logging mtp_prot_reg_mtp_en disabled - 0

18 MTP writing write_lock enabled - 0

19 MTP reading read_lock enabled - 0

22 Brownout delay mtp_brown_out_delay 50 ms 0

23 PFC valley switching mtp_valleysw enabled - 1

24 Filter delay compensation mtp_t_filt_delay 277 μs 0

25 Mains sensitivity mtp_mains_sensitivity low - 0

26 Mains sensing resistor value mtp_rmains 20 MΩ 1

27 Notch filter in regulation loop mtp_notch_en enabled - 1

28 PFC gamma value mtp_pfc_gamma 36 - 36

29 Mains peak zero crossing detection mtp_pk_pos_detect enabled - 1

30 Mains sense wait time after NTC mtp_t_snsmains_discharge 500 μs 0

31 Disable NTC during startup mtp_ntc_chk_en enabled - 1

33 SNSBOOST level low gain increase mtp_level_gm_low off - 0

34 SNSBOOST low gain increase mtp_gain_gm_low 2x - 0

35 VCC stop level mtp_vcc_stop 8 V 0

36 Mains sensing resistors mtp_nr_resistors 1 resistor - 0

37 VCC start level mtp_vcc_start 11 V 0

38 AUX sensing filter mtp_fc_aux 5 MHz 0

39 AUX blanking time mtp_t_aux_blank 600 ns 0

40 AUX high time for sec stroke mtp_t_wait_aux_high 750 ns 0

41 Time slot for measuring NTC mtp_t_meas_ntc 450 μs 0

42 NTC circuit diode voltage drop mtp_udiode_dig0 460 mV 0

43 Number of phases controller mtp_phase1_only 2 phase 0

44 Startup delay for AC/DC detection mtp_wait_for_acdc wait AC/DC det - 1

45 Phase when no valley switching mtp_force_phase_valley_dis phase 180 - 0

46 Min switch on delay between phases mtp_min_tps_diff_delay 204 ns 0

47 Max switch on delay between

48 Ipfc_peak for Fmin mtp_vrsense_fmin 55 - 0

49 Delta Ipfc_peak for Fmax-Fmin mtp_vrsense_fmax_fmin 110 - 0

52 Minimum switching frequency mtp_fmin 40 kHz 0

53 Maximum switching frequency mtp_fmax 130 kHz 0

54 Power level for leaving Shedding mtp_pshed_high_perc 30 % 3

55 Hysteresis for entering Shedding mtp_pshed_hys_perc 10 % 0

56 Time delay for entering Shedding mtp_time_shed 140 ms 0

57 Value of AUX measurement resistor mtp_raux 33 kΩ 0

59 Soft start time BM mtp_softstart_time normal - 0

60 Ton steps in soft stop CCM mtp_softstop_tonstep normal - 0

61 Initial on time at startup mtp_scale_duty_init normal - 0

63 Proportional loop gain mtp_pgain 10 - 0

64 Regulation Vin compensation mtp_vincomp enabled - 1

65 Regulation Vin current

66 Regulation Tring compensation mtp_tringcomp enabled - 1

67 QR mode switching mtp_en_qr enabled - 1

68 CCM allowed mtp_sel_ipfc_ok when needed - 0

69 AUX min oscillation level mtp_osc_amin 17 V 0

70 AUX scaling oscillation to valley mtp_osc_scale 1 - 0

71 AUX delay compensation mtp_osc_offset 93 ns 0

72 AUX valley detection time out mtp_osc_timeout 3 μs 0

73 AUX valley detection hysteresis mtp_osc_hys 2 - 0

74 AUX demag time out mtp_wait_mag 3 μs 0

75 Minimum GATE off time mtp_toffmin 1 μs 0

76 Notch filter for mains frequency mtp_ton_fir_filt enabled - 1

77 PFC current loop gain mtp_igain 35 - 35

79 Limit the power at start mtp_pwr_limit_start 255;

80 Minimum secondary stroke time mtp_minsecstroke 1 μs 0

81 Minimum stretch time mtp_stretchmin 200 ns 0

82 Minimum Ides clamp level mtp_idesmax_min 13 % 0

83 Ides clamp slope K mtp_k_idesclamp 1 - 2

84 Ipfc clamp function mtp_idesclamp_en enabled - 1

85 Slope clamp value mtp_slope_clamp 512 - 0

86 SNSBOOST high gain increase mtp_gain_gm_high 4x - 0

88 External OTP protection Level mtp_gotp_limit 88 - 0

89 External OTP delay time mtp_t_eotp 4 s 0

90 FLR only when protection mtp_flr_only_at_prot disabled - 0

91 SNSBOOST low clears all

92 Fast latch reset delay time mtp_flr_delay 50 ms 0

93 External OTP level multiplier mtp_mult_gntc 32x - 0

94 Safe Restart Time mtp_restart_time 1 s 0

95 VCC OVP delay mtp_vcc_ovp_delay 1000 μs 0

96 AUX OVP level mtp_aux_ovp_value 215 - 0

97 SNSMAINS OVP level mtp_snsmains_ovp_value 420 mV 0

99 VCC OVP level mtp_vcc_ovp_limit 24 V 0

100 Max pos AUX voltage difference mtp_min_auxpos_value 12 (dig) 1

101 Fast Latch Reset function mtp_fast_latch_reset disabled - 0

102 PFC shortwinding delay cycles mtp_max_drain_short_count 2500 - 0

103 OCP blanking time mtp_ocp_blanking_time 250 ns 0

104 SNSCUR short detection level mtp_snscur_short_det_lvl 30 - 0

105 Max SNSCUR cycles to show short mtp_nr_snscur_short_cycles 200 cycles 3

106 Max AUX voltage difference in

107 AUX voltage measurement filter mtp_aux_v_filt_setting 4 cycles 0

108 AUX min time for valid stroke mtp_tmin_pk_hold 750 ns 0

109 Max missed AUX primary strokes mtp_max_missed_prim_strokes 100 cycles 0

110 Max missed AUX secondary strokes mtp_max_missed_sec_strokes 100 cycles 0

111 SNSCUR current ratio mtp_snscur_ratio 128 - 0

112 SNSBOOST pulldown at brownout mtp_snsboost_pulldown_brownout 0 ms 0

113 SNSMAINS OVP prot follow up mtp_mains_ovp_mode disabled - 0

114 VCC OVP prot follow up mtp_vcc_ovp_mode safe restart - 0

115 AUX OVP prot follow up mtp_aux_ovp_mode disabled - 7

116 SNSBOOST short prot follow up mtp_snsb_short_mode auto continue - 0

117 SNSSRC overcurrent prot follow up mtp_snssrc_oc_mode safe restart - 0

118 Allow startup with mains DC mtp_allow_startup_dc_load disabled - 0

119 SNSCUR overcurrent prot follow up mtp_snscur_oc_mode safe restart - 0

120 SNSCUR short protect follow up mtp_snscur_short_mode safe restart - 0

121 Internal OTP prot follow up mtp_iotp_mode safe restart - 0

122 External OTP prot follow up mtp_eotp_mode safe restart - 0

123 AUX phase fail prot follow up mtp_pf_vout_diff_mode safe restart - 0

124 AUX pos phase fail prot follow up mtp_pf_pos_aux_mode safe restart - 0

125 AUX neg phase fail prot follow up mtp_pf_neg_aux_mode safe restart - 0

126 Duration soft start/stop operation mtp_bm_end_soft_start_stop infinite - 0

127 Burst mode SNSBOOST ripple mtp_bmripple 105 mV 0

128 BM soft start mtp_skip_soft_start softstart - 0

129 BM soft stop mtp_skip_soft_stop softstop - 0

130 Burst mode delay time mtp_burstdelay 0 s 0

132 Burst on/off level on VCC mtp_bmvccth 10 V 0

133 Burst mode type mtp_bm auto - 0

134 BM boost recover mtp_boostrecover disabled - 0

135 External BM control pin mtp_bm_ctrl_sel BURST normal - 0

136 BM depending on shedding mtp_bm1phase 1 phase only - 1

137 Burst starts with 1 phase mtp_single_phase_burst_restart disabled - 0

140 Power good at mains brownout mtp_pwrgood_bo_stop enabled - 1

142 Power Good polarity mtp_pwrgood_pol normal - 0

143 PG stopped by SNSBOOST mtp_pwrgood_lvl_stop enabled - 1

144 Vendor code mtp_code 0x0003 - 3

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller

17 Legal information

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NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. TEA2376DT All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 10 August 2023

NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products.

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NXP Semiconductors TEA2376DT Digital configurable interleaved PFC controller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2023 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 10 August 2023 Document identifier: TEA2376DT

Product Information

TEA2376DT1 specifications and overview.

Summary

Digital configurable interleaved PFC controller Rev. 1 - 10 August 2023

Description

Digital configurable interleaved PFC controller Rev. 1 - 10 August 2023

Source title TEA2376DT1 Datasheet(PDF) - NXP Semiconductors

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