TEA2028

TEA2028 STMICROELECTRONICS | Alldatasheet

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Technical content

By : J-M. MERVAL & B. D’HALLUIN SUMMARY Page TEA2028 V.2.2.1 IC ID

TEA2028 - TEA2029 APPLICATION NOTE

VIII APPLICATION INFORMATION ON FRAME SCANNING IX TEA2029 APPLICATION DIAGRAM COMPLETE APPLICATION WITH TEA2164 ... 4 6 I - GENERAL DESCRIPTION As depicted in Figure 1, the TEA2028 combines 3 major functions of a TV set as follows : - Horizontal (line) and vertical (frame) time base generation for spot deviation. The video signal is used for the synchronization of both time bases. - On-chip switching power supply controller syn- chronized on line frequency. This integrated circuit has been implemented in bipolar I2L technology, and various functions are digitally processed. In fact, resorting to logic func- tions has the advantage of working with pure and accurate signals while full benefit is drawn from high integration of logic gates (approx. 110 gates per mm 2). The main objective is to drive all functions using an accurate time base generated by a master 500kHz oscillator. Also, horizontal and vertical time bases, are ob- tained by binary division of reference frequency. This has the advantage of eliminating the 2 adjust- ments which were necessary in former devices. One section of this integrated circuit is designed to drive a switching power supplyof recent implemen- tation called ”master-slave”. Switching takes place on the primary side (i.e., directly on mains) of a transformer. The device ensuresSMPS Control, Start-upand Protectionfunctions. Control signals go through a small pulse transformer thereby pro- viding full isolation from mains supply. This new approach fully eliminates the bulky mains transformersused in the past. In addition, it offers optimized power consumption and reduction of TV cost-price. TEA2028 - TEA2029 APPLICATION NOTE

• Detection and extraction of line and frame syn- chronization pulses from the composite video signal. - Horizontal scanning control and synchronization by two phase-locked loop devices. - Video identification. - 50 or 60Hz standardrecognition for vertical scan- ning. - Generation of a self-synchronized frame saw- tooth for 50/60Hz standards. - Line time constant switching for VCR operation through an input labeled ”VCR” (Video Cassette Recorder). - Control and regulation of a primary-connected switching power supply by on-chip controller de- vice combining :
• an error amplifier
• a pulse width modulator synchronized on line frequency
• a start-up and protection system - Overall TV set protection input - Frame blanking and super sandcastle outputsig- nals - Frame blanking safety input for CRT protection in case of vertical stage failure. III - PIN CONNECTIONS Pin Description

1 Horizontal output monostable capacitor

2 Frame blanking safety input

3 Frame saw-tooth output

4 Frame blanking output

5 Frame ramp generator

6 Power ground

POWER AMP. VERTICAL POWER AMP. SMPS CONTROLLER TEA2028B Miscellaneous Power Supplies PRIMARY CONNECTED SMPS Miscellaneous Power Supplies Mains Input Video Signal UHF I.F. SEPARATOR SOUND I.F. PICTURE I.F. SOUND DETECTION PICTURE DETECTION UHF COLOR DECODING RGB 2028B-05.EPS Figure 1 Pin Description

7 SMPS control output

8 Supply voltage (V

CC )

9 SMPS regulation input

10 Horizontal output

11 Super-sandcastle output

12 Horizontal flyback input

13 Horizontal saw-tooth generator

14 Current reference

15 SMPS soft-start and safety time constant

16 φ2 phase comparator capacitor (and horizontal phase adjustment) 17 V CO phase shift network

18 V CO output

19 V CO input

20 Frame sync time constant adjustment capacitor

21 Substrate Ground

22 φ1 phase comparator capacitor

23 VCR switching input

24 Video and 50/60Hz identification output (Mute)

25 Video identification capacitor

26 Horizontal sync detection capacitor

(50% of peak to peak sync level)

27 Video input

28 Safety input

DIP28.EPS TEA2028 - TEA2029 APPLICATION NOTE

2028B-02.EPS Figure 2 IV - INTERNAL BLOCK DIAGRAM 2425 H. SYNC 50/60Hz MUTING OUTPUT 23 22 VCR SWITCHING INPUT SAFETY INPUT 1.26VV R 2021 SUBSTRAT GROUND SUBST 1.26VV R H. OUTPUT 109 H. INHIBIT S.M.P.S. OUTPUT 1.26VVR FRAME BLANK OUTPUT 2µs FRAME ERROR AMPLIFIER Hz 503kHz VIDEO INPUT FRAME SAWTOOTH OUTPUT FRAME SAWTOOTH H. SAWTOOTH GENERATOR HORIZONTAL FLYBACK INPUT 3.3kΩ V CC HORIZONTAL OUTPUT S SC OUTPUT VCO 500kHz V CC POWER GROUND V CC FRAME BLANKING OUTPUT FRAME BLANKING SAFETY FRAME SAWTOOTH OUTPUT VIDEO IDENTIFICATION VCR INPUT ϕ 1 INHIBITIONTIME CONSTANT SWITCHING ϕ1 DET HORIZONTAL SYNCHRO AND FRAME SYNCHRO SAFETY LOGIC FRAME SAFETY S.M.P.S. ϕ MODULAT. SUPER SANDCASTLE REFERENCE CURRENT VOLTAGE LINE MONOSTABLE HORIZONTAL LOGIC TIMINGFRAME TIMING IDENTIFICATIONLOGIC50/60Hz SWITCH ON/OFF SAFETYCIRCUIT SOFT STARTING CIRCUIT TEA2028B TEA2028 - TEA2029 APPLICATION NOTE

V.3.2 - Functional duty of individual blocks V.3.2.1 - Phase comparator The duty of this comparator is to issue an output current proportional to the phase difference be- tween φ IN and φOUT . V.3.2.2 - Low-pass filter This filter suppresses the parasiticcomponent con- taining the sum of phases, smoothens the phase difference component and determines the timing characteristics of the loop. V.3.2.3 - VCO centered on 500kHz This is a voltage-controlled oscillator which gener- ates an output frequency proportional to the volt- age applied to its input. This voltage is delivered by low-pass filter. V.3.2.4 - Divider stage It is used to divide the VCO frequency (500kHz) by 32 so that it can be compared with the line sync signal frequency of 15625Hz. V.3.3 -Functional descriptionofbuilding blocks V.3.3.1 - Phase comparator ”φ1” The comparator is functionally equivalent to a sig- nal multiplier (see Figure 12). Let’s assume that : LS = I sin (ω H t+ φIN) and Vφ1 = k cos (ω H t+ φOUT ) then : - i= iLS ⋅k 2 [ sin (Φ IN -Φ OUT ) + sin (2ω H t+ Φ IN + Φ OUT )] (see Figure 13) - the low-pass filter will suppress the 2fH frequency component -φIN -φOUT difference being low : sin (φIN -φOUT )≈ φIN -φOUT - the output current will be therefore proportionalto the phase difference between the signals com- pared. In other words, the averagecurrent overone period is : IAV ⋅TH =I  t S 2 + Δt -I t S 2 − Δ t =2 IΔt I AV =2 IΔt TH and Δt= ΔΦ TH The comparator conversion gain is thus : A= i ΔΦ = I π (in A/rd) Later in our discussion we shall consider the two possible values of the current I. For the time being, let’s define these values as follows : - I = 500µA for ”long time constant” or normal operation - I = 1.5mA for ”short time constant” VCR mode or synchronization search (Mute). The values of A are therefore : -A LONG = 0.16mA/rd -A SHORT = 0.47mA/rd Use of comparator inhibition signal is quite useful under noisy transmission conditions. It eliminates risk of incorrect comparison during the line scan- ning phase whichwould be due tothe noisepresent on LS signal. Horizontal phase and image stability are thus highly enhanced. Characteristics of this inhibition signal will be dis- cussed at the end of this chapter. i V + CC 1.26V iLS I2I 1mA 500µA LS Long ϕ1 inhibition≤ 1 Mute VCR Video Recognition VCR Mode Switching φOUT 1.26V vϕ1 Signal φIN V φI iO LS = 1 T HtS0 Δt 2028B-15.EPS Figure 12 TEA2028 - TEA2029 APPLICATION NOTE

Where : R1 = 7Ω , L1 = 1.26mH, C1 = 78pF, C0 = 507pF - Series resonance frequency : fS = 1 - Parallel resonance frequency : C0 = 540kHz - Tolerance within the resonance area : 503kHz ± 0.3 % - Temperature stability :± 0.3% of fO atΔT = 100oC B - SIMPLIFIED BLOCK DIAGRAM OF VCO The overall arrangement is equivalentto avariable- phase amplifier configured in closed loop with the external passive filter. The system will oscillate if the open-loop gain is 0dB and if V OUT leads VIN. In closed-looposcillating mode, the phase variation of V18/VIN imposed by V22 will result in same VOUT /V18 variation but of opposite sign. This phase change will finally correspond to a change in frequency. C. - CHARACTERISTICS OF THE EXTERNAL FILTER The ceramic resonator behaves as a capacitor at f<fS (fS : series resonance frequency) and as an inductorat frequenciesfallingbetween its tworeso- nance frequencies. Combined with a ”R.C” network to generate a 90 o phase lag, the overall arrangement will exhibit the following characteristics : see Figure 21 450 600 10 4 IMPEDANCE |Z| (Ω )PHASE ϕ (Degrees) +90 -90 500 550 fS fP 2028B-21.EPS Figure 18 1819 Filter ϕ Amp. V22 Phase Control V 18 VIN VOUT (open-loop) 2028B-23.EPS Figure 20 1.2kΩ V S1 2mA 1.2kΩ 500Ω R 220Ω C 1.5nF 503kHz R 220Ω 5.6V i Comparator V 22 Non-linear Amplifier A4 A3 R 2.4kΩ

1.1 VDC

1.8 kΩ 2028B-22.EPS Figure 19 2.4kΩ V18 VOUT 503kHz440Ω 2.4kΩ Resistor = Pin 19 Input Resistance -135° Working Area Attenuation Frequency (kHz) -20 -10 (dB)V18 VOUT20 log V18 V18VOUT /φ (Degrees) -24° 480 500 520 -30 -90 -150 φ Attenuation 2028B-24.EPS Figure 21 TEA2028 - TEA2029 APPLICATION NOTE

It is therefore deduced that the system can follow all input phase variations without producing any static error. In practice, there will be a slight error due to the input bias current ”I B” of VCO, which is 0.55µAa t fO = 500kHz. This DC current is delivered by a phase comparator which will generate a phase error of : - long time constant : ΔΦ LONG = IB ALONG = 0.55⋅10−3 0.16 = 3.4⋅10-3 rd or 35ns inΔt - short time constant :ΔΦ SHORT = IB ASHORT = 12ns These two errors cause a horizontal picture dis- placement. On a large screen of 54cm wide, this will be : 64 - 12 = 52µs, which for both modes corresponds to a shift of : Δ LINE = ΔΦ LONG −Δ Φ SHORT 52 ⋅520 = 0.24mm It is obvious that such displacement can be fully neglected. Response to a Frequency Step - The input phase is :Φ IN(t) =Δω t which as a function of (p) is :Φ IN(p) =Δω - The accuracy is : lim p−>0 (Φ IN −Φ OUT )= lim p−>0 Δω p + ABf(o) = Δω ABR where R = 500kΩ at f(o) In this case, the phase error depends on both, the magnitude of the frequencystep and the static gain ABR. In general,Δ f Δ fwhich is the open-loop static gain, is taken into consideration. Δω ΔΦ = ABR = 2πΔ f Δt× 2π =A ⋅2 π ⋅B’⋅R ⇒ Δf Δt=A B ’ R⋅2π TH (B’ in kHz/V) - In normal mode : ALONG = 0.16 mA/rd ⇒ Δf Δt= 5.5kHz/µs, R = 500kΩ - In VCR mode : ASHORT = 0.47 mA/rd ⇒ Δf Δt= 16.5kHz/µs Note : The capture range is specified within ± 500Hz with respect to 15625Hz. Numerical Example Let’s suppose that in VCR mode there is a fre- quency variation of± 100Hz, this will yield a phase variation of 0.1/16.5, i.e.± 6ns which, on a 54cm wide screen, will produce a horizontal shift of ΔLINE = ± 0.06mm ! It is obvious that an excellent image stability is thus obtained. V.3.6.2 - Dynamic study The loop response in transient mode is quite im- portant. It determines the overall system stability and the phase recovery time, which are imposed by the external filter ”f(p)”. The close-loop transfer function is equivalent to a second order system. These time constants are in practice displayed on screen by a bar delivered by a special pattern generator representingthe phase errors. The following optimizedresults were obtainedfrom filter f(p) connected to Pin 22. Filter component values are : R1 = 4.7kΩ , C1 = 2.2µF, C = 10nF A. LONG TIME CONSTANT -A tΔto f4µs ⇒ N=18 lines, i.e.τLONG = 1.15ms. System oscillations are perfectly damped. Image stability with a noisy video signal is very satisfac- tory. B. SHORT TIME CONSTANT -A tΔt= 4µs ⇒ N = 5 lines, i.e.τSHORT = 0.32ms - n = 5 lines One should notice fast phase recovery, naturally followed by bounced oscillations due to the char- acteristics of a second order device. As given in application diagram section 6, an other alternative would be to use the following compo- nent values : R1 = 3.9kΩ , C1 = 4.7µF, C = 15nF. TEA2028 - TEA2029 APPLICATION NOTE

B. STUDY OF SHIFT ADJUSTMENT With R, P network connected to Pin 16, the tout becomes : tOUT = − BR ′IIN 1+T2 + tD − 59.7µs 1 + T2 B R ′ R ⋅KV CC 1 + T2 With : T2 = ABR’ (where R’ = R // RIN) and K∈ [0;1] Substituting the following values into above equa- tion : - R = 470kΩ - R’ = 470kΩ // 25MΩ = 46kΩ -A =1 7×10-6A/µs -B= 1 6µs/V -td =1 0µs -T 2 = 125 -V CC = 12V -tOUT = - 38ns - 390ns + 1.5µs×K therefore tout= 1.5⋅ K - 0.43 ( inµs) If K varies between 0 and 1 ⇒ tout[- 0.43ms to 1.07µs] which corresponds to a picture displacement of : ΔLINE [- 4mm to + 11mm]. Shift variations as a function of VCC (with adjustment) dtOUT dVCC B R ′ R ⋅K 1 + T2 B R ′ R ⋅K ≈ K AR =K ⋅0.12µs/V dL dVCC = 0.34mm/V at KNOMINAL = 0.28 Therefore, a constant VCC must be applied to the potentiometer. V.6 - Vertical deflection driver stage This stage must constantly drive the vertical spot deflection.Such deflectionwill horizontallyscan the screen from top to bottom thus generating the displayed image. Similar to horizontal deflection, the vertical deflection is obtained by magnetic field variations of a coil mounted on the picture tube. A saw-tooth current at frame frequency will go through this coil commonly called ”frame yoke”. Frame period is the time required for the entire screen to be scanned vertically. tively 50Hz and 60Hz Frame Scanning Frequen- cies. Also, a full screen display is obtained by two successivevertical scanningssuch that the second scanning is delayed by a half line period with respect to the first. This method increases the number of images per second (50 half images/s or 50 frames/s in 50Hz standard). This scanning mode called ”Interlaced Scanning” eliminates the fliker which would have been otherwise produced by scanning 25 entire images per second. The circuit will generate a saw-tooth voltage which is linear as a function of time and called ”frame saw-tooth”. A power amplifier will deliver to the ”frame yoke” a current proportional to this saw- tooth voltage. It is thus clear that this saw-tooth voltage reflects the function of the vertical spot deflection; which must itself be synchronized with the video signal. Synchronization signals are ob- tained from an extraction stage which will extract the useful signal during line pulse inversion of the composite sync signal. Synchronization occurs at the end of scanning, in other words, when the saw-tooth voltage at Pin 5 is reset. This function is accomplished by the ”frame logic circuitry” of full digital implementation. This processing method offers various advan- tages : -Accurate free-running scanning frequency eliminates the frequencyadjustment required by previous devices. -Digital synchronizationlocked onto half line frequency thereby yielding perfect interlaced dis- play andexcellent stabilitywith noisy video signal. -Automatic 50/60Hz standard recognitionand switching the corresponding display amplitude. -Optimized synchronization in VCR mode. -Generation of variousaccurate time intervals, such as narrow ”sync windows” thus reducing considerably the vertical image instability in case of forinstance,mainsinterference,superimposed on frame sync pulse. -Generation of vertical blankingsignal for spot flyback and toprotect the picture tube in case of scanning failure. TEA2028 - TEA2029 APPLICATION NOTE

• Full protection of the primary-connected transis- tor in case of short-circuit or open-load on secon- dary terminals - Can provide 1W to 7W, for TV standby mode operation (refer to TEA2164 application note). V.7.4 - Power supply soft-start When the TV set is initially turned on,control pulses are not yet available and consequently the control- ler block on primary side will impose a low-power transfer to the secondary winding. This power is produced by an intermittent switching mode called ”Burst Mode”. As soon as the V CC supply to TEA2028B exceeds 6V level, line andSMPSoutputsareenabled.Since the filtering capactitors on secondary side cannot charge up instantaneously,the voltage to be regu- lated would not yet be at its nominal value. Without conduction period limitation upon start-up, the de- vice will set a maximum cycle of 28µs which will result in a high current flow through the primary winding and thus through the switching transistor which will in turn activate the protection function implemented on primary side. Consequently, the primary controller block will be inhibited and the set will not turn-on. A start-up system has been implemented within TEA2028B to overcome this problem. This soft start system, will upon initial start-up, use the image of the falling voltage on Pin 15 to in- crease progressively the conduction cycle. The phase modulator ”M2” compares this voltage with line saw-tooth voltage and delivers the correspond- ing limitation cycle. During supply voltage rising cycle [V CC (Pin 8) < 6V], the capacitor Pin 15 will charge up rapidly while the voltage across it follows V CC . At VCC ≥ 6V, the capacitor is discharged via an internal current generatorand the voltage across it decays linearly. At V15 ≤ 3.5V (line saw-tooth peak-to-peak volt- age), phase comparator ”M2” delivers a low con- duction period which will gradually increase. The conduction period (Pin 7) will rise until the secondary voltage reaches the value set by poten- tiometer ”P”. When this occurs, the loop is acti- vated. The Pin 15 discharge current value is 100µAf ora duration of 2µs line frequency. Therefore I D (AV ) = 100 × 2 64 = 3.1µA Conductionperiod limitation voltage (Pin 15) TON(LIM) =5 6µs-1 6xV 15 (inµs) 5.5V 5.5V 12V 3.5 t t t t V CC V CC V CC Soft-start area Regulated Mode Active area PIN 8 SUPPLY VOLTAGE (V) PIN 15 VOLTAGE (V) SMPS CONTROL OUTPUT VOLTAGE (PIN 7) LINE OUTPUT VOLTAGE (PIN 10)* * Line output (Pin 10) and Thyristo rcontrol output (Pin 4) for TEA2029C 2028B-69.EPS Figure 66 TEA2028 - TEA2029 APPLICATION NOTE

VI - TEA2028 APPLICATION DIAGRAM 123 121314151617 26 27 28 TEA2028B V CC 470Ω 220Ω 1.8kΩ 503kHz 220Ω 10µF 150pF 22nF 1.5nF 10pF GROUND SUBSTRAT 4.7nF VCR SWITCH 10µF 1kΩ 10nF 5.6kΩ V CC MUTE OUTPUT 50Hz/60Hz IDENTIFICATION 100nF 220nF VIDEO INPUT V CC 10kΩ SAFETY INPUT 1.26V3.3nF 2.2kΩ 3.32kΩ 47kΩ 3.3nF V CC 2.2nF 470kΩ LR 10 VPP V CC 10kΩ FRAME BLANKING OUTPUT 2.7MΩ 470nF +200V 330Ω TO TEA2161 1kΩ V CC 150kΩ 1kΩ 1kΩ SMPS OUTPUT VOLTAGE ADJUST 100µF SUPER SAND CAST. 390Ω 1kΩ 47nF LINE YOKE 2mH - 2.5Ω +200V +24V LF EHT TRANSFORMER +140V FROM SMPS TRANSFORMER TDA8172 1nF Pin 14 (TEA2028B) 33kΩ 13kΩ 150kΩ 100kΩ1nF 680k Ω 15kΩ FRAME AMPLITUDEADJUST 100Ω 100nF 470kΩ FRAME YOKE 32µH 15Ω 0.7App 1000µF 220Ω VERT. SHIFT 2.2Ω 100nF 1N4001 100µF FRAME SAWTOOTH SAFETYINPUT V REF +12V V CC 2028B-75.EPS Figure 72 TEA2028 - TEA2029 APPLICATION NOTE

VII - TEA2029 :DIFFERENCES WITH TEA2028 VII.1 - General The TEA2029 has quite the same functions compared to TEA2028. The main difference is that the TEA2029 incorporates a frame phase modulator intended to work with a switched mode vertical stage using a thyristor. The TEA2029 can also be used with a linear vertical power amplifier such as the TDA8170. VII.2 - Pin by Pin Differences Pin TEA2029C TEA2028B

1 Dfferential inputs of the frame error amplifier (including

frame blanking safety in case of vertical stage failure). Capacitor for horizontal output duration adjustment (29µs typ. with c1 = 3.3nF)

2 Vertical blanking safety input

4 Frame output for thyristor control Vertical blanking output (21 lines duration)

10 Horizontal output (26µs typ. duration) Horizontal output (duration is adjustable)

11 Supersandcastle output (with a frame blanking duration

of 24 lines) Supersandcastle output (with a frame blanking duration of 21 lines)

12 Negative horizontal flyback input (115 VPP through a 47

kΩ resistor) positive horizontal flyback input (10Vpp through a 47kΩ resistor) 20 Positive AGC key pulse output (low level when no video) Capacitor for frame sync. time constant adjustment

28 Safety input (inhibition of SMPS, Horizontal and Frame

28 > 1.26V) Safety input (inhibition of SMPS, Horizontal outputs when V28 < 1.26V) VII.3 - TEA2029C Pin Connections Pin Description

1 Frame error amplifier non-inverting input

2 Frame error amplifier inverting input

4 Frame output (for thyristor control)

8 VCC Supply voltage

11 Supersandcastle output

16 φ2 phase comparator capacitor (and horizontal phase adjustment)

17 VCO phase shift network

18 VCO output

19 VCO input

20 AGC key pulse output

22 φ1 phase comparator capacitor (50% of peak to peak sync level) DIP28.EPS VII.4 - Frame Phase Modulator The Tranconductance Amplifier ”A1” converts the differential input voltage into two output currents S1” and ”IS3”. - A1 transconductance=IS1 VIN =1 0µA/mV - B transconductance=IS2 =4 0µA/V - Transfer characteristic =ΔtOUT ΔVIN = 6.4µs/V The filter time constant is maximum near the oper- ating point when IS1 ≅ IS2 In this case : - The base current of T1 =” IS2 -IS1” - The filter band-pass = 15kHz The maximum conduction period of ”40µs” is de- termined by the horizontal logic circuitry. The frame frame flyback is detected by transis- tor ”T3”. There is no feed-back during frame flyback and ”IS3” is maximum (higher than I4) which will drive the ”T3” into conduction. TEA2028 - TEA2029 APPLICATION NOTE

4.7µs BurstVIDEO SIGNAL (Pin 27) 2.3µs1.3µs0V 12V AGC SIGNAL (Pin 20) Without Video Signal 2028B-82.EPS Figure 79 VII.7 - AGC Key Pulse As illustrated below, this signal is used in some TV sets to perform sampling window for Automatic Gain Control of picture demodulationnetwork. This system is called ”clamped” AGC,andlocks the demodulated line sync amplitude and hence sets the video signal amplitude. This signal generated by line logic circuitry is cor- rectly positioned by the first phase locked loop ”φ1” and includes the line sync pulse of the video signal. This is an open-collector output. VIII - APPLICATION INFORMATION ON FRAME SCANNING IN SWITCHED MODE (TEA2029 ONLY) VIII.1 - Fundamentals(see Figure 80) The secondary winding of EHT transformer pro- vides the energy required by frame yoke. The frame current modulation is achieved by modulating the horizontal saw-tooth current and subsequent integration by a ”L.C” network to reject the horizontal frequency component. VIII.2 - General Description The basic circuit is the phase comparator ”C which compares the horizontal saw-tooth and the output voltage of Error Amplifier ”A”. The comparator output will go ”high” when the horizontal saw-tooth voltage is higher than the ”A” output voltage. Thus, the Pin 4 output signal is switched in synchronization with the horizontal fre- quency and the duty cycle is modulated at frame frequency. A driver stage delivers the current required by the external power switch. The external thyristor provides for energy transfer between transformer and frame yoke. The thyristor will conduct during the last portion of horizontal trace phase and for half of the horizontal retrace. The inverse parallel-connected diode ”D” conducts during the second portion of horizontal retrace and at the beginning of horizontal trace phase. Main advantages of this system are : -Power thyristor soft ”turn-on” Once the thyristor has been triggered,the current gradually rises from 0 to IP, where IP will reach the maximum value at the end of horizontal trace. The slope current is determined by, the current available through the secondary winding, the yoke impedance and the ”L.C.” filter charac- teristics. -Power thyristor soft ”turn-off” The secondary output current begins decreasing and falls to 0 at the middle of retrace. The thyristor is thus automatically ”turned-off”. -Excellent efficiency of power stagedueto very low ”turn-on” and ”turn-off” switching losses. TEA2028 - TEA2029 APPLICATION NOTE

The bias voltage ”VB” is supplied by the secondary winding of EHT transformer. The parabolic effect is due to the integration of frame saw-tooth by the filtering capacitor ”C1”. DVB = I Y ⋅T 8 ⋅C1 = 0.95V Where : -IY : Peak-to-peak yoke current = 380mApp - T : 20ms - C1 = 1000µF VIII.5 - Frame Flyback During flyback, due to the loop time constant, the frame yoke current cannot be locked onto the reference saw-tooth. Thus the output of amplifier ”A” will remain high and the thyristor is blocked. The scanning current will begin flowing through diode ”D”. As a consequence, the capacitor ”C” starts charging up to the flyback voltage.The thyris- tor is triggered as soon as the yoke current reaches the maximum positive value. EHT transformer winding (see Figure 88) (for 90 o tube : Yoke⇒ L = 120mH, rY =6 0Ω ) VIII.6 - Feed-back Circuit VIII.6.1 - Frame power in quasi-bridge configu- ration(see Figure 89) This stage measures the frame scanning current in differential mode and compares it to the reference saw-tooth on Pin 3. The overall configuration is built around two sym- metrical networks : -” R 1,R 2,R 3” network : determines the dynamic saw-tooth voltage - ”R’1,R ’2,R ’3” network : sets the bias voltage and the d.c. shift control. A.C. gain : G =R 2 R 1 = IY VIN ⋅α ⋅RM where : -IY : Peak-to-peak Yoke Current -V IN : Peak-to-peak saw-tooth voltage (Pin 3) -α ∈ [0,1] : amplitude adjustment VIII.6.1.1- Choice of ”R” value The saw-tooth generator output is an emitter fol- lower stage. Pin 3 output current must thereforebe always negative. R< <R 1 VIN(Min.) VBIAS − VIN(Min.) Where : -V BIAS : Bias voltage for Pins 1 and 2 -V IN(MIN): Saw-tooth voltage low level Example : - R1 = 22kΩ ⇒ R ≈ R 1 10-V BIAS =5 V -V IN(Min.)= 1.26V VIII.6.1.2- Influence of R3 value R 3 sets the bias voltage for Pins 1 and 2. This voltage should be lower than 5.5V so as to enable the frame to function upon initial start-up at V CC =6 V . If the bias voltage is higher than this 5.5V level, the d.c. open-loop gain will fall thereby rendering the system more sensitive to d.c. drift. Satisfactory results are obtained at V BIAS values falling within 4V to 5V range. R3 = R2 VBIAS VB [VIN(MEAN ) ⋅G]− VBIAS [1− G] Where : VIN(MEAN ) : saw-tooth mean value (Pin 3) Capacitor ”C” connected between Pins 1 and 2 determines the system stability. Its value must be appropriately calculated as a function of ”R1,R 2 and R3” values so as to reject the line frequency component. VLF C VB Load Yoke I I DIODE THYRISTOR L 2028B-91.EPS - VLF = 210VPP - IYOKE = 380mA PP - L = 500µH - C = 0.47µF - VLF ≈ 9.2 IY(PP) ⋅rY - Flyback duration = 1ms Figure 88 TEA2028 - TEA2029 APPLICATION NOTE

VIII.6.3 - Frame safety In case of failure in the loop, the thyristor may remain turned-off while the inverse parallel-con- nected diode conducts. This will result in a haz- ardeous situation where the voltage across the coupling capacitor ”CP” will reach an excessively high value. To avoid such situation, the voltage at point (a) should be appliedto the ”Safety” input Pin 28 after it hasgone through the matching network ”R4, R5”. VIII.7 - Frame Scanning in Class B with Flyback Generator VIII.7.1 - Application diagram 123 TDA8172 1N4001 100µF +24V 1nF 13kΩ 2.2kΩ100nF TEA2029C (Pin 14)33kΩ 10kΩ15nF 150kΩ 680kΩ 470kΩ 470nF 2.7MΩ 200V Frame Sawtooth 2.2kΩ 3.3kΩ 10kΩ +12V N.C. 100nF 15kΩ 100Ω Frame Yoke 32mH 15Ω 0.7App1000µF Vertical Phase Shift 220Ω Vertical Amplitude Adjust TEA2029C 2028B-95.EPS Figure 92 TEA2028 - TEA2029 APPLICATION NOTE

IX - TEA2029 APPLICATION DIAGRAM Complete application with TEA2164 Secondaryground (isolated frommains) BA157 31 3 12 13 1110 2 3 14 TEA216 4 100Ω BA159 47µF 100Ω 330Ω BY218 100µ F 1000µF 33kΩ 4 x 1N4007 FUSE1.6A 300kΩ 2x4 7µF (385V) 100kΩ (2W) PrimaryGround(connectedto mains) 1.2nF 110kΩ 12kΩ 470kΩ 6.8Ω 220µF 2.2Ω BA157 2.2Ω 390 Ω 0.27Ω 3 x 1N40410Ω 2µH 2.2nF BU508A 220Ω OREGA G.4173.04 BY218 BY218 470µ F 10kΩ TEA2029C 15 27 26 25 12 11 28 219814132316 172.2µF 4.7µF 1N4444 1.5nF 15nF4.7µF 3.9kΩ 220Ω 503 kHz 1.8kΩ 150pF 220Ω 10µF 470Ω VCC 8.2kΩ 1N4148 5.6kΩ 5.6kΩ 15kΩ VCC AGC PULSE MUTEOUT 50/60Hz IDENTIFICATION 100nF 220nF 4.7nF 100nF VIDEO INPUT LINE FLYBACK SUPER SANDCASTLE OUTPUT 10kΩ 2.7MΩ 220kΩ 470nF 220Ω 1kΩ 100nF 820Ω 820Ω 6.8kΩ 3.3kΩ 3.3kΩ 6.8kΩ 33Ω 82kΩ1kΩ 220Ω 220Ω 4.7Ω 2.2kΩ E/W CORRECTION FramePhase Adjust Frame Amplitude Adjust 200V +24V V CC HorizontalPhase Adjust 470kΩ 22nF VCR Switch 3.3nF +25V 3.32kΩ(1%) 22nF 1kΩ 1.5kΩ 47nF 1nF ESM

740 BA157

27Ω 680Ω 2N1711 V CC 100nF 220 µF +135V / 0.6A 1kΩ 1kΩ 220pF 150kΩ SMPS OutputVoltage Adjust 220pF 100kΩ 390Ω 1kΩ LINE YOKE 0.47µF FRAME YOKE 120mH Ω LINE FLYBACK EHT TRANSFORMER 500µH +200V +24V 220V MAINSINPUT AC 1nF 330 Ω 2028B-96.EPS Figure 93 TEA2028 - TEA2029 APPLICATION NOTE

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