TEA2017AAT

TEA2017AAT NXP | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 General description
• 2 Features and benefits
• 2.1 Distinctive features
• 2.2 Green features
• 2.3 Protection features
• 3 Applications
• 4 Ordering information
• 5 Marking
• 6 Block diagram
• 7 Pinning information
• 7.1 Pinning
• 7.2 Pin description
• 8 Functional description
• 8.1 Supply voltages
• 8.1.1 Start-up and supply voltage
• 8.1.2 High-side driver floating supply (SUPHS
• 8.2 LLC system regulation
• 8.2.1 Output power regulation loop
• 8.2.2 Output voltage start-up
• 8.3 Modes of operation
• 8.3.1 High-power mode
• 8.3.2 Low-power mode
• 8.3.3 Burst mode
• 8.3.3.1 Frequency regulation
• 8.3.3.2 Negative transient response
• 8.3.3.3 Burst-mode delay function
• 8.3.3.4 Burst-mode exit delay function
• 8.4 Optobias regulation
• 8.5 Power factor correction (PFC) regulation
• 8.5.1 PFC switching frequency
• 8.5.2 Frequency jitter
• 8.5.3 Multimode operation (DCM/QR/CCM)
• 8.5.4 DCM/QR mode of operation
• 8.5.5 Fixed-frequency CCM mode
• 8.5.6 PFC start-up
• 8.5.7 Output voltage regulation
• 8.5.8 PFC burst mode
• 8.5.9 PFC burst mode soft start/soft stop
• 8.5.10 Valley switching and demagnetization
• 8.5.11 Frequency limitation
• 8.5.12 Mains voltage compensation (SNSMAINS
• 8.5.13 Active X-capacitor discharge
• 8.6 Protections
• 8.6.1 Undervoltage protection SUPIC
• 8.6.2 MTP fail
• 8.6.3 Internal overtemperature protection (OTP)
• 8.6.4 Brownin/brownout and external
• 8.6.5 Short-circuit protection/fast disable
• 8.6.6 Brownout mains
• 8.6.7 Overvoltage protection (SNSBOOST pin)
• 8.6.8 Overvoltage protection (DRAINPFC pin)
• 8.6.9 Overcurrent protection, inrush protection
• 8.6.10 PFC coil short protection (SNSCURPFC
• 8.6.11 Undervoltage protection SUPHS
• 8.6.12 Undervoltage protection boost
• 8.6.13 Overvoltage protection
• 8.6.14 Capacitive mode regulation (CMR)
• 8.6.15 Overcurrent protection
• 8.6.16 Maximum start-up time
• 8.6.17 Overpower protection
• 8.6.18 Latched, safe restart, or latched after safe
• 8.6.19 Fast latch reset
• 8.7 Power good function
• 8.8 Settings
• 8.8.1 General settings
• 8.8.1.1 Protection register
• 8.8.1.2 Supply start level
• 8.8.1.3 Read lock
• 8.8.1.4 Write lock
• 8.8.1.5 Reset to the default values
• 8.8.1.6 Customer MTP code
• 8.8.2 PFC settings
• 8.8.2.1 Soft-start time
• 8.8.2.2 Active X-capacitor discharge
• 8.8.2.3 Mains measurement impedance
• 8.8.2.4 Number of mains resistors
• 8.8.2.5 PFC mode of operation
• 8.8.2.6 PFC minimum and maximum frequency
• 8.8.2.7 Burst mode: Output voltage ripple
• 8.8.2.8 Burst mode: Soft-start/soft-stop time
• 8.8.3 LLC settings
• 8.8.3.1 LLC disable
• 8.8.3.2 Start-up
• 8.8.3.3 LLC switching
• 8.8.3.4 Feedback
• 8.8.3.5 Operation modes
• 8.8.4 Protection settings
• 8.8.4.1 General protections
• 8.8.4.2 PFC general protections
• 8.8.4.3 LLC general protections
• 8.8.5 Power good settings
• 9 Limiting values
• 10 Thermal characteristics
• 11 Characteristics
• 12 Application information
• 13 Package outline
• 14 Appendix: Ringo parameter settings
• 15 Revision history
• 16 Legal information

Digital configurable LLC and multimode PFC controller Rev. 1 — 14 June 2021 Product data sheet

1 General description

The TEA2017AAT is a digital configurable LLC and PFC combo controller for high- efficiency resonant power supplies. It includes both the LLC controller and PFC controller functionality. The PFC can be configured to operate in DCM/QR, CCM fixed frequency, or multimode which supports all operation modes to optimize the PFC efficiency. The TEA2017AAT enables building a complete resonant power supply which is easy to design and has a very low component count. The TEA2017AAT comes in a low profile and narrow body-width SO16 package. The TEA2017AAT digital architecture is based on a high-speed configurable hardware state machine ensuring very reliable real-time performance. During the power supply development, many operation and protection settings of the LLC and PFC controller can be adjusted by loading new settings into the device to meet specific application requirements. The configurations can be fully secured to prevent unauthorized copying of the proprietary TEA2017AAT configuration content. In contrast to traditional resonant topologies, the TEA2017AAT shows a very high efficiency at low loads due to the LLC low-power mode. This mode operates in the power region between continuous switching (also called high-power mode) and burst mode. Because the TEA2017AAT regulates the LLC output voltage of the system via the primary capacitor voltage, it has accurate information about the power delivered to the output. This measured output power defines the mode of operation (burst mode, low- power mode, or high-power mode). The transition levels of the operating modes can be easily programmed into the device. The TEA2017AAT contains all protections like overtemperature protection (OTP), overcurrent protection (OCP), overvoltage protection (OVP), overpower protection (OPP), open-loop protection (OLP), and capacitive mode regulation (CMR). Each of these protections can be configured independently and accurately by programming parameters inside the device. The device contains both a low-voltage and high-voltage silicon technology for high- voltage start-up, integrated drivers, level shifter, protections, and circuitry assuring zero- voltage switching. The TEA2017AAT/TEA2095T combination gives an easy to design, highly efficient, and reliable power supply, providing 90 W to 1000 W, with a minimum of external components. The system provides a very low no-load input power (< 75 mW; total system including the TEA2017AAT/TEA2095T combination) and high efficiency from minimum to maximum load. This power supply meets the efficiency regulations of Energy Star, the Department of Energy, the Eco-design directive of the European Union, the European Code of Conduct, and other guidelines. So, any auxiliary low-power supply can be omitted.

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller To enhance readability, only typical values are given in this document, except in the parametric tables (Section 9, Section 10, and Section 11). If values in the text differ from the values for the same parameter in the parametric tables, the values in these tables are leading.

2 Features and benefits

2.1 Distinctive features

• Complete functionality of LLC and PFC controller in single small-size SO16 package
• Integrated high-voltage start-up
• Integrated drivers and high-voltage level shifter (LS)
• High-side driver directly supplied from the low-side driver output
• Accurate boost voltage regulation
• PFC can be configured to operate in: – DCM/QR – DCM/QR/CCM (also called mixed mode operation) – CCM fixed frequency
• Integrated X-capacitor discharge without additional external components
• Power good function
• PFC jitter for optimized EMI performance
• Excellent power factor (PF) and total harmonic distortion (THD), as the PFC current compensates for the input filter current
• Several parameters can easily be configured during evaluation with use of the graphical user interface (GUI), like: – Operating frequencies to be outside the audible area at all operating modes – Soft start and soft stop in burst mode, reducing the audible noise – Accurate transition levels between operation modes (high-power mode/low-power mode/burst mode) – Enabling/disabling the lower power mode

2.2 Green features

• Valley/zero voltage switching for minimum switching losses
• Extremely high efficiency from low load to high load
• Compliant with latest energy-saving standards and directives (Energy Star, EuP)
• Excellent no-load input power (< 75 mW for TEA2017AAT/TEA2095T combination) Product data sheet Rev. 1 — 14 June 2021

2.3 Protection features

• Independently configurable levels and timers
• All protections can independently be set to latched, safe restart, or latched after several attempts to restart
• Supply undervoltage protection (UVP)
• Overpower protection (OPP)
• Internal and external overtemperature protection (OTP)
• Capacitive mode regulation (CMR)
• Accurate overvoltage protection (OVP)
• Overcurrent protection (OCP)
• Inrush current protection (ICP)
• Brownin/brownout protection
• Disable input

3 Applications

• Desktop and all-in-one PCs
• LCD television
• Notebook adapter
• Printers
• Server
• 5G supplies
• UHD LED television

4 Ordering information

Table 1. Ordering information

5 Marking

Table 2. Marking codes

6 Block diagram

Figure 1. Block diagram

7 Pinning information

7.1 Pinning

Figure 2. TEA2017AAT pin configuration (SOT109-1)

7.2 Pin description

HVS 7 high-voltage spacer. Not to be connected. HVS 12 high-voltage spacer. Not to be connected. Table 3. Pin description

an optocoupler. Output for power good function. Table 3. Pin description...continued

8 Functional description

8.1 Supply voltages

• A high-voltage supply pin for start-up (DRAINPFC)
• A general supply to be connected to an external auxiliary winding (SUPIC pin)
• A floating supply for the high-side driver (SUPHS pin)

8.1.1 Start-up and supply voltage

Figure 3. HV start-up this start level with a hysteresis (Vstart(hys)SUPIC). memory) and defines the settings.

winding. So, the SUPIC pin is regulated to Vstart(SUPIC) via the DRAINPFC pin. protection (Vuvp(SUPIC)) is triggered because of a long non-switching period in burst mode. detection, for X-capacitor discharge, and for providing a second PFC OVP protection. Figure 4. Start-up sequence and normal operation

Figure 5. LLC controller flow diagram When the SUPIC voltage drops to below Vrst(SUPIC), the TEA2017AAT restarts.

8.1.2 High-side driver floating supply (SUPHS pin)

Figure 6. High-side driver supply the HB node is pulled low, CSUPHS is charged.

8.2 LLC system regulation

the operation mode transition levels are derived from the output power. continuously regulates the output voltage.

8.2.1 Output power regulation loop

TEA2017AAT. Figure 8 shows a corresponding timing diagram. Figure 7. Regulation loop Vcap control Figure 8. Timing diagram of the regulation loop resonant capacitor voltage initially increases further but eventually drops.

regulates the power and the frequency is a result. TL431 circuitry, determines the difference between the high and low capacitor voltages. increases and eventually the output voltage increases to its regulation level. is continuously regulated to Ireg(SNSFB) (see Section 8.4).

8.2.2 Output voltage start-up

limited current source during start-up. Figure 9. LLC start-up behavior

8.3 Modes of operation

between the high and low capacitor voltage levels. Figure 10. TEA2017AAT control curve ΔVCr voltage, corresponds to the maximum output power. low-power mode. The Pt(lp) level can be initialized via the MTP. minimum. The system then enters the burst mode (see Section 8.3.3).

8.3.1 High-power mode

a flow diagram of the high-power mode. Figure 11. High-power mode flow diagram

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller Initially, GATELS is on and GATEHS is off. The external bootstrap buffer capacitor (CSUPHS) is charged via the GATELS pin and an external diode. The system remains in this state for at least the minimum on-time (ton(min)) of GATELS. Before entering the next state, one of the following conditions must be fulfilled:

• The VSNSCAP voltage drops to below the minimum VSNSCAP voltage (Vls(SNSCAP))
• The measured current exceeds the OCP level (see Section 8.6.15)
• The system is close to capacitive mode (see Section 8.6.14)
• The maximum on-time (ton(max)), a protection that maximizes the time the high-side or low-side MOSFET is kept on, is exceeded. To avoid false detection of the HB peak voltage, the system remains in this state until the minimum non-overlap time (tno(min)) is exceeded. When this time is exceeded and it detects the peak of the HB node and the measured resonant current is negative (or zero), it enters the next state. If the system does not detect a peak at the HB node, it also enters the next state when the maximum non-overlap time (tno(max)) is exceeded under the condition of a negative (or zero) resonant current. Finally, the third and fourth states (see Figure 11) describe the GATEHS and GATEHS to GATELS transition criteria which are the inverse of the first two states.

8.3.2 Low-power mode

At low loads, the efficiency of a resonant converter drops as the magnetization and the switching losses become dominant. A low-power mode ensures high efficiency at lower loads because it reduces the magnetization and switching losses. When the output power drops to below the Pt(lp) level, the system enters the low-power mode (see Figure 10 and Figure 12). It continues switching for 3 half-cycles (low-side, high-side, low-side) with an MTP selectable duty cycle. To ensure a constant output power level, it increases the energy per cycle (Vhs(SNSCAP) − Vls(SNSCAP)) at the same time. Product data sheet Rev. 1 — 14 June 2021

Figure 12. Timing diagram transition high-power mode to low-power mode cycle (= ΔVSNSCAP) is reduced and the duty cycle remains the same (see Figure 13). cycle (= ΔVSNSCAP), it enters burst mode.

Figure 13. Low-power mode: Lowering the energy-per-cycle (ΔVSNCAP)

8.3.3 Burst mode

side the audible noise area. Figure 14. Burst mode

8.3.3.1 Frequency regulation

by the setting (see Figure 15). Figure 15. Burst mode: Regulating the number of low-power cycles period, the burst period (Tburst) remains constant. period again. In this example, the burst period is still below the targeted burst period. measured burst period equals the target burst period, which occurs at t4.

8.3.3.2 Negative transient response

the output voltage shows an overshoot (see Figure 16).

Figure 16. Burst mode - transient optocoupler current exceeds the Istop(burst) level.

8.3.3.3 Burst-mode delay function

audible noise or when using a multioutput configuration. Figure 17. Burst delay function continues to increase, the system enters burst mode anyway.

8.3.3.4 Burst-mode exit delay function

leave the burst mode and restart the burst-mode delay function (see Figure 18). Figure 18. Restart of the burst-mode delay

8.4 Optobias regulation

level that is independent of the output load. level (= 80 μA typical). This level is independent of the output power.

Figure 19. Optobias regulation the 12 kΩ resistor drops to below the targeted level of 960 mV (= 80 μA × 12 kΩ). The TEA2017AAT then slowly increases an additional offset at the power level (ΔP). continuous regulation of the optocurrent level does not influence the regulation level.

8.5 Power factor correction (PFC) regulation

accordance with a shifted sine wave (see Figure 20).

Figure 20. PFC current waveforms capacitances (IC_total) and the PFC current (IPFC), it approaches a sine waveform.

power is requested to the output, the amplitude of the shifted sine wave increases.

• DCM/QR/CCM, where the valley detection can be enabled/disabled
• DCM/QR
• Fixed frequency CCM

8.5.1 PFC switching frequency

Figure 21. PFC current as function of output power switching frequency increases as well until it reaches its maximum level. at low loads, while keeping the ripple to a minimum at higher loads.

8.5.2 Frequency jitter

8.5.3 Multimode operation (DCM/QR/CCM)

frequency is at minimum level. The PFC is then switching in DCM mode. Figure 22. PFC current over one mains cycle

8.5.4 DCM/QR mode of operation

frequency can drop to below the minimum set frequency.

8.5.5 Fixed-frequency CCM mode

and equals the set frequency.

8.5.6 PFC start-up

At start-up, the PFC output voltage increases in line with an RC curve (see Figure 23). Figure 23. PFC start-up regulation level, avoiding audible noise. The RC time value can be programmed via the MTP.

8.5.7 Output voltage regulation

regulates the amplitude of the desired PFC current (see Figure 15).

8.5.8 PFC burst mode

adjustable hysteresis, the PFC leaves burst mode. Figure 24 shows the behavior of the PFC in burst mode.

Figure 24. PFC burst mode regulation level again, the PFC stops switching. stops switching, the PFC stops switching as well.

8.5.9 PFC burst mode soft start/soft stop

8.5.10 Valley switching and demagnetization

started when the PFC MOSFET drain-source voltage is at its minimum (valley switching). signal (tto(vrec); 7 μs typical) after demagnetization is detected.

8.5.11 Frequency limitation

To avoid audible noise, the minimum frequency is limited to fsw(PFC)min. time is limited at toff(PFC)min. All frequency limitation values are adjustable.

8.5.12 Mains voltage compensation (SNSMAINS pin)

requirements may be hard to meet. on load steps is yielded, while still complying with class-D MHR requirements.

8.5.13 Active X-capacitor discharge

8.6 Protections

Table 4 gives an overview of the available protections. Table 4. Protections overview

Table 4. Protections overview...continued [1] Selectable via a parameter at the MTP.

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller When the system is in a latched or safe restart protection, the SUPIC voltage is regulated to its start level via the DRAINPFC pin.

8.6.1 Undervoltage protection SUPIC

When the voltage on the SUPIC pin is below its undervoltage level Vuvp(SUPIC), both the PFC and LLC converter stop switching. The capacitors at the SUPIC pin are recharged via the DRAINPFC pin. When the SUPIC supply voltage exceeds its start level, the system restarts.

8.6.2 MTP fail

At start-up, when the SUPIC reaches 12 V, the system reads the parameters from the internal MTP. If reading the MTP failed, the system retries reading the MTP until it succeeds. A mains reset is required before the system starts. During this time, the PFC and LLC remain off.

8.6.3 Internal overtemperature protection (OTP)

An accurate internal temperature protection is provided in the circuit. When the junction temperature exceeds the thermal shutdown temperature, the PFC and the LLC stop switching. The response of the internal OTP follows the setting of the external OTP. It can be either latched or safe restart. Product data sheet Rev. 1 — 14 June 2021

8.6.4 Brownin/brownout and external overtemperature protection

the SNSMAINS pin (see Figure 25). Figure 25. Mains and external OTP management

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller td(otp). The internal current source is turned on until the SNSMAINS voltage exceeds the Vdet(SNSMAINS) level level or a maximum time of tdet(max)NTC. The external resistor, which is connected between mains_L/mains_N and the SNSMAINS pin, can be either 20 MΩ or 10 MΩ. The amount of mains resistor can either be one (only connected to the mains-L or mains-N) or two (one connected to the mains-L and the other to the mains-N). However, the selected parameter of the resistor value and number of resistors must correspond to the application.

8.6.5 Short-circuit protection/fast disable

The PFC and LLC do not start switching until the voltage on the SNSBOOST pin exceeds Vscp(start). This function acts as short circuit protection for the boost voltage. When the SNSBOOST pin is shorted to ground or the SNSBOOST pull-up resistor is disconnected, this protection inhibits switching. This function can also be used as a fast disable. If this pin is shorted to ground via an external MOSFET, the system either stops switching or enters the protection mode followed by safe restart or latched protection. In this way, an additional external protection can be added.

8.6.6 Brownout mains

To prevent the PFC from operating at very low mains input voltages, the PFC stops switching with a soft stop when the measured mains voltage drops to below the brownout level. When the mains voltage exceeds the brownin level, the PFC restarts with a soft start. To avoid that the system is interrupted during a short mains interruption, a delay can be set before the brownout function is active. Typically, only the PFC stops switching and the LLC continues at a brownout. Due to the large PFC bulk capacitor, the LLC can continue for a long period while the mains is already disconnected. So, the option to stop the LLC at a brownout after a given delay can be selected with a parameter.

8.6.7 Overvoltage protection (SNSBOOST pin)

To prevent output overvoltage during load steps and mains transients, a PFC output overvoltage protection circuit is built in. When the voltage on the SNSBOOST pin exceeds the Vstop(ovp)PFC level, switching of the power factor correction circuit is inhibited. When the SNSBOOST pin voltage drops to below the regulation level (Vreg(SNSBOOST)) again, the switching of the PFC recommences. When an OVP at the SNSBOOST is detected for a minimum period (can be set using a parameter), the LLC can also be disabled.

8.6.8 Overvoltage protection (DRAINPFC pin)

To prevent output overvoltage of the PFC due to a disturbed SNSBOOST pin, an additional PFC output overvoltage protection is available. This overvoltage protection is measured via the DRAINPFC pin. To avoid false triggering, measuring the DRAINPFC is blanked for tleb(OVP)PFC after the PFC MOSFET is switched off. The DRAINPFC overvoltage protection level and the delay before it enters the protection state can be set with parameters. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller The DRAINPFC overvoltage protection can be a latched, a safe restart, or a latched after safe restart protection.

8.6.9 Overcurrent protection, inrush protection (SNSCURPFC pin)

The PFC current is measured via an external sense resistor (RSENSE) connected to the SNSCURPFC pin (see Figure 29). If the voltage drops to below Vocp(PFC), the PFC MOSFET is turned off. It resumes switching at the next cycle, under the condition that the voltage at the SNSCURPFC is above the Vocp(PFC) level. Otherwise, it remains off until this requirement is fulfilled. It avoids that the PFC MOSFET is turned on during an inrush. To ensure that the OCP level is not exceeded due to disturbance caused by a turn-on of the PFC MOSFET, the OCP level is filtered via an internal 1 MHz filter.

8.6.10 PFC coil short protection (SNSCURPFC pin)

If the PFC coil is shorted, the overcurrent protection is triggered continuously. To avoid overheating, the system enters the protection state when the OCP is continuously triggered for a selectable number of switching cycles. The PFC and LLC converters stop switching and a restart follows.

8.6.11 Undervoltage protection SUPHS

To ensure a minimum drive voltage at the high-side driver output (GATEHS), this driver is turned off when its voltage is below the minimum level (VSUPHS < Vrst(SUPHS)).

8.6.12 Undervoltage protection boost

The PFC output voltage is measured via a resistive divider connected to the SNSBOOST pin. The voltage at the SNSBOOST pin must exceed the start level (VSNSBOOST > Vstart(SNSBOOST)) before the LLC converter is allowed to start switching. When the system is operating and the voltage at the SNSBOOST pin drops to below the minimum level (VSNSBOOST < Vuvp(SNSBOOST)), the LLC converter stops switching. When it exceeds the start level, it restarts.

8.6.13 Overvoltage protection

When the voltage at the SUPIC pin exceeds the VO(ovp)SUPIC level for td(ovp)SUPIC, the OVP protection is triggered. The voltage at the SUPIC pin is continuously monitored via an internal A/D converter. The OVP protection level and the OVP delay time can be selected with a parameter. The OVP function can also be disabled.

8.6.14 Capacitive mode regulation (CMR)

The TEA2017AAT has a capacitive mode regulation (CMR) which ensures that the system is always operating in inductive mode and avoids operation in capacitive mode. At lower input voltage or higher output power and depending on the resonant design, the resonant current can already approach zero before the capacitor voltage reaches the regulation level. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.6.15 Overcurrent protection

The system measures the LLC primary current continuously via a sense resistor connected to the SNSCURLLC pin. If the measured voltage exceeds the fixed overcurrent level (Vocp(LLC)), the corresponding switch (GATELS/GATEHS) is turned off, but the system continues to switch. In this way, the primary current is limited to the OCP level. The OCP level can be adjusted via the external sense resistor. If the OCP is continuously triggered for an adjustable time, the system enters the OCP protection state. The OCP protection state can also be disabled. However, the primary current is always limited to the OCP level cycle-by-cycle.

8.6.16 Maximum start-up time

At start-up, the PFC starts switching. When the PFC output voltage exceeds a minimum level, the LLC starts switching as well. If the output voltage of the LLC is not in regulation within an adjustable time after the PFC has started switching, the maximum start-up time protection is triggered. The maximum start-up time (tstartup(max)) can be set with the parameter “Maximum start- up time”. If this protection is triggered, the system is latched, safe restart, or latched after safe restart, which follows the setting of the OPP.

8.6.17 Overpower protection

For the overpower protection, three levels can be set:

• Absolute maximum output power, which is the highest output power level. When the output power exceeds this maximum level, it is limited cycle-by-cycle. If the output power exceeds this maximum, the output voltage decreases. The maximum output power can be set to a percentage of the rated output power.
• A first overpower level, which is below the maximum output power level. When the output power exceeds this power level, a timer is started. When this timer exceeds a predefined value, the system enters the protection state. Both PFC and LLC are switched off. This power level can be set to a predefined level below the selected maximum output power. So, if the maximum output power is set to 170 % and this first overpower level is set to −20 %, the timer is started at 150 % of the rated output power. The timer of the first overpower level can also be set. The first overpower level can also be disabled.
• A second overpower level, which is typically below the first overpower level. When the output power exceeds this power level, a timer is started. When this timer exceeds a predefined value, the system enters the protection state. PFC and LLC are switched off. This power level can be set to a predefined level below the selected maximum output power. So, if the output power is set to 170 % and this second overpower level is set to −50 %, the timer is started at 120 % of the rated output power. The timer of the second overpower level can be set to a predefined level. The second overpower level can also be disabled. The overpower function can be either latched, safe restart, or latched after safe restart. Section 8.6.18 describes this function. Product data sheet Rev. 1 — 14 June 2021

8.6.18 Latched, safe restart, or latched after safe restart

(see Section 8.6.19) or when the SUPIC supply voltage drops below the UVP level. predefined safe restart time. This safe restart time is the same for all protection functions. It can be set with a parameter. protection. If the failure occurs again within a specific time, it latches eventually. Figure 27. Latched after safe restart within 65 seconds, the counter is reset.

8.6.19 Fast latch reset

mains voltage is below the brownout level for a specified time, the system also restarts. This time can be set with a parameter. This function is called fast latch reset.

8.7 Power good function

The TEA2017AAT provides a power good function via the SNSFB pin. Figure 28. Power good function an external MOSFET and an optocoupler. low. The external power good signal becomes active high.

• The voltage on the SNSBOOST pin drops to below Vdet(SNSBOOST)
• The OPP counter is close to its end value
• The converter is about to stop due to an OTP protection
• When the LLC converter is about to stop due to an OVP on the SNSBOOST when this function is enabled
• When the LLC converter is about to stop due to a mains brownout when this function is enabled To avoid any disturbance of the regulation loop, the increase and decrease of the SNSFB voltage is in alignment with a predefined ramp. When the system enters protection mode (OVP, OCP, or UVP), it pulls high the SNSFB pin and stops switching immediately. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8 Settings

The TEA2017AAT has an internal MTP at which different settings can be programmed. Disclaimer: The MTP parameter settings can be changed using the “Ringo” GUI software of NXP Semiconductors. Before the user can change any MTP parameters using the GUI, the terms and conditions in the start-up pop-up screen must be accepted.

8.8.1 General settings

8.8.1.1 Protection register

When the TEA2017AAT triggers a protection, it can be read which protection was triggered. Even when the root cause of the protection is solved and the converter continues switching, the information about the protection remains until the software program (Ringo GUI) clears it.

8.8.1.2 Supply start level

The SUPIC start level can be selected between 12 V and 19 V. Typically, a level of 19 V is selected. When the TEA2017AAT is externally supplied, for instance via a standby supply, the lower start level of 12 V can be used. After start-up, when the MTP is read and a 12 V start level is selected, charging via the PFCDRAIN is disabled, as the system assumes that it is externally supplied.

8.8.1.3 Read lock

Normally, the software tool can read all the programmed settings. This option can be used to verify the correct settings or for failure analyses. However, once in production, enabling the "Read lock" bit protects the parameters. Then it is not possible anymore to read the MTP content. It can however still be reset to the default values and also clear the read lock parameter.

8.8.1.4 Write lock

To avoid that the MTP content (accidentally) gets overwritten, a write-lock bit can be set. It can, however, still be reset to the default values and clear the write lock parameter.

8.8.1.5 Reset to the default values

When the MTP is reset, it implies that all parameters are set to a default value. The default values normally do not correspond to the original MTP values. They are chosen such that a general application works properly. When the MTP is reset, the MTP can be read and written again.

8.8.1.6 Customer MTP code

When in production, the content of the MTP can be hidden when the read lock bit is enabled. To get access to the content of the MTP, a unique customer code can be programmed. This customer code provides information about the MTP content. This customer code can always be read, even when the read lock bit is enabled. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8.2 PFC settings

8.8.2.1 Soft-start time

For the start-up time of the PFC, the following RC time periods can be selected: 12.8 ms, 25.6 ms, 51.2 ms, or 102.4 ms.

8.8.2.2 Active X-capacitor discharge

When the TEA2017AAT detects that the mains is disconnected, the X-capacitor discharge is activated after a delay of td(dch)xap. The following delays can be selected: 100 ms, 200 ms, and 400 ms. This function can also be disabled.

8.8.2.3 Mains measurement impedance

To realize a low no-load input power level, the external resistor connected to the SNSMAINS pin for measuring the mains input voltage is typically 20 MΩ. However, some applications request a maximum resistance of 10 MΩ. With this bit,

10 MΩ or 20 MΩ can be selected for the external resistor without affecting the mains

voltage-related levels like brownin and brownout.

8.8.2.4 Number of mains resistors

To achieve the lowest possible no-load input power, a single mains sense resistor can be used. If continuously measuring the mains voltage is necessary, two mains resistors can be used. For proper functionality, the resistor value and number of resistors in the application are required to correspond to the IC settings.

8.8.2.5 PFC mode of operation

When all modes are enabled, the PFC can operate in DCM, QR, or CCM mode. However, the frequency varies between the minimum and maximum frequency. It is also possible to either disable CCM mode or select the fixed frequency mode. For evaluation purposes, the option to disable the PFC is available as well.

8.8.2.6 PFC minimum and maximum frequency

The minimum switching frequency of the PFC can be set within a range from 25 kHz to 80 kHz. When the CCM mode of operation is disabled, the PFC always waits until the PFC coil is demagnetized before starting the next cycle. As a result, the switching frequency can drop to below the minimum frequency. The maximum frequency can be set within a range from 75 kHz to 250 kHz. When the PFC operating mode is set to fixed frequency, the frequency can be set between 55 kHz and 200 kHz.

8.8.2.7 Burst mode: Output voltage ripple

When the PFC enters burst mode, it stops switching when the SNSBOOST voltage, which reflects the PFC output voltage, reaches its regulation level and the LLC stops switching. When the voltage at the SNSBOOST pin has dropped to a programmed level, the PFC is enabled again. For the difference between these two levels the following values can be selected: 70 mV, 105 mV, 140 mV, 175 mV, 210 mV, 245 mV, and 280 mV. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller These values typically correspond with a ripple on the PFC output voltage of 10 V, 16 V, 22 V, 28 V, 34 V, 40 V, and 46 V. The PFC burst mode can also be synchronized to the LLC burst mode. It then follows the on and off periods of the LLC. However, it ensures that the SNSBOOST reaches its regulation level.

8.8.2.8 Burst mode: Soft-start/soft-stop time

To minimize audible noise of the PFC, a burst mode soft start and soft stop can be independently selected. The selectable values are: normal, short, and long. The additional soft-start and soft-stop can also be disabled.

8.8.3 LLC settings

8.8.3.1 LLC disable

Especially for validation purposes, an option is available to disable the LLC. When the LLC is disabled, a restart is required.

8.8.3.2 Start-up

Maximum (start-up) frequency The maximum switching frequency of the LLC is limited to a value, which is defined using a parameter. This value also defines the maximum switching frequency during start-up. The maximum frequency can be set to different values ranging from 150 kHz to 800 kHz. LLC soft-start time The LLC soft-start time defines the rate at which the converter lowers its switching frequency. This rate can be selected between 2 and 20 which leads to a start-up time of approximately between 1 ms and 10 ms. However, it depends on the LLC design. A higher speed lowers the start-up time. However, it can cause a high charge current and an overshoot at the output voltage. Maximum primary current during start-up At start-up, the LLC starts switching at the maximum frequency and ramps down the frequency until the ΔVSNSCAP reaches the required level. If during this start-up time the primary current, which reflects the output current, reaches a predefined level, the frequency is temporarily not further reduced until the primary current drops to below the level again. This level is measured via the SNSCURLLC pin. The following values can be Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8.3.3 LLC switching

ΔVSNSCAP dump level When the system is in low-power mode, a switching period is followed by a waiting period. The system ensures that it continues at the same stage as where it stopped. To reach the maximum efficiency, the end of the last switching cycle can be fine-tuned. For the ΔVSNSCAP dump level, values between 2.525 V and 2.7 V can be selected in steps of 25 mV. Minimum non-overlap time To ensure that the GATEHS is properly turned off before the GATELS is turned on, and vice versa, there is a minimum non-overlap time. For the minimum non-overlap time, the following values can be selected: 100 ns, 230 ns, 350 ns, 500 ns. Maximum non-overlap time When the system does not detect a valley at the HB node after turning off GATEHS, the system turns on the GATELS after the maximum non-overlap time. The same counts when a peak at the HB node is not detected after turning off the GATELS and turning on the GATEHS. For the maximum non-overlap time, the following values can be selected: Maximum on-time When the on-time of the GATELS or GATEHS exceeds the maximum on-time, the switch is turned off and the LLC converter starts the next cycle. For the maximum on-time, the following values can be selected: 10 μs, 20 μs, 30 μs, or 38 μs. Capacitive mode regulation When the voltage at the SNSCURLLC pin, which reflects the resonant current, drops to below a predefined value, the LLC converter starts the next switching cycle. In this way, the TEA2017AAT avoids that the converter operates in capacitive mode. For the capacitive mode regulation, the following values can be selected: 20 mV to 160 mV in steps of 20 mV. LLC maximum ringing time When the LLC operates in LP mode, it counts the amount of ringings. If a ringing is not detected, it assumes a peak after the timeout. This timeout can be set to 3 μs, 5 μs, 7.5 μs, or 10 μs. The appropriate value depends on the application. It must be chosen just above the maximum ringing period.

8.8.3.4 Feedback

To achieve a low no-load input power, the current through the optocoupler must be set at a low level. However, depending on the selected optocoupler, a higher optocoupler current may be requested. So, the optocoupler current can be set to different values ranging from 80 μA to 1.2 mA. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8.3.5 Operation modes

When the output power drops to below a predefined level, the system switches from the HP to the LP mode. The HP-LP transition level can be set to different values ranging from 10 % to 54 %. HP-LP transition hysteresis When the system operates in LP mode, it switches over to HP mode when the output power exceeds the selected HP-LP transition level plus a hysteresis. For the hysteresis, the following values can be selected: 10 %, 20 %, 30 %, or 40 % of the selected HP-LP transition level. So, if the rated output at 100 % is 100 W, the HP-LP transition level is set at 30 % and the hysteresis is set at 10 %. The eventual hysteresis is 3 W. LP-BM transition level When the output power drops below the LP-BM transition level, the system enters burst mode. The LP-BM transition level can be set to different values ranging from 1 % to 25 %. The actual LP-BM transition level can deviate from the selected value due to delays in the system. The deviation is most noticeable at low LP-BM transition levels. In this case, the LP-BM transition level can be fine-tuned in steps of 1 %. BM-LP transition level When the system operates in burst mode and output power increases to exceed the LP- BM transition level plus a hysteresis level, the system enters low-power mode. For the hysteresis, levels in the range from 5 % to 50 % can be selected, which are related to the selected LP-BM transition level. So, if the rated output at 100 % is 100 W, the LP- BM transition is set at 10 %, and the hysteresis at 50 %, the system switches from burst mode to low-power mode at a level of 15 W. BM-LP transition level filter When the output power slowly increases, the system ensures a smooth transition when leaving burst mode and entering low-power mode by setting a burst-mode-to-low-power- mode transition filter. When the output power exceeds the BM-LP transition level plus hysteresis for 2, 4, 8, or 16 burst cycles, it leaves the burst mode and enters the low- power mode. At a large transient at the output, the system immediately leaves burst mode. BM repetition frequency When the system operates in burst mode, it is regulated to a fixed frequency. This frequency can be set to different values ranging from 20 Hz to 3.2 kHz. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller BM E/C (Energy-per-cycle) increase As the TEA2017AAT regulates the output via the primary capacitor voltage, it offers the ability to increase the output power per switching cycle when it enters burst mode. For the increase of output power per switching cycle, also called E/C (Energy-per-cycle), different values can be set ranging from 1 to 4. When, for instance, the E/C is set to 4, the system increases the E/C with a factor of 4 when it enters burst mode. The initial duty cycle is then 25 %. Increasing the E/C in burst mode increases the efficiency of the system, but at the cost of a higher output voltage ripple. BM soft start/soft stop To minimize the audible noise in burst mode, a soft start and a soft stop can be added. The soft start and soft stop can be independently initialized, whereas the number of soft- start/soft-stop cycles can be set between 0 and 4. In this way, the soft-start and soft-stop cycle can be optimized depending on the selected transformer. BM minimum cycles As additional soft-start and soft-stop cycles reduces the audible noise, it increases the switching losses. To optimize the number of normal switching cycles in relation to the added soft-start and soft-stop switching cycles, the minimum number of normal switching cycles that can be selected ranges from 1 to 12. Burst end SNSFB current When the system operates in burst mode, it adjusts the number of switching cycles such that burst frequency corresponds to the selected burst frequency. If during these switching cycles the output load decreases, the output voltage increases as the system has calculated the number of required switching cycles. If the measured optocoupler current at the SNSFB pin exceeds a certain level, the system ends the burst switching cycle. This level can be between a factor of 2.5, 3.75, 5, or 7.5 times the selected optocoupler current level. Burst delay Entering the burst mode can be postponed with a delay from 0.2 s to 4 s. The delay can also be set to 0, implying that when the output power drops to below the burst mode entry level, the system immediately enters burst mode. The burst mode delay can also be set to infinite. The system does not enter burst mode and remains switching. Burst-mode exit delay When the LLC is switching for a time that exceeds the burst-mode exit delay time and the output load exceeds the burst-mode level, the system leaves the burst mode. The burst- mode exit delay time (tburst-exit) can be set from 160 μs to 4 ms in 16 steps. Low-power frequency The frequency of the low-power mode can be selected by defining the ringing number at which the next low-power cycle must be started. The selection options are from 1 to 8 in steps of 1. SNSBOOST compensation A ripple at the input voltage of an LLC converter normally results in a ripple in the output voltage. To minimize the ripple at the output voltage, the TEA2017AAT measures the input voltage of the LLC via the SNSBOOST pin and compensates the SNSCAP voltage via a feed-forward compensation. As the required compensation depends on the external components, it can be set at 8 different compensation levels. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8.4 Protection settings

8.8.4.1 General protections

Fast latch reset delay time When the system does not detect a mains voltage for a programmed period, it assumes that the mains is disconnected and resets all protections. When the mains voltage exceeds the brownin level again, the system restarts. The delay between detecting a brownout (including the brownout delay time) and resetting all protections can be programmed to different values ranging from 0 s to 10 s. Safe restart time When the system is in protection mode and the triggered protection is programmed as safe restart, it restarts after a safe-restart time. This time can be set at different values ranging from 0.5 s to 10 s. Fast disable When the SNSBOOST voltage is pulled below the Vscp(stop) level, the system enters the protection state. The response can be set to on/off, latched, or safe restart. External OTP level The external application temperature is measured via an NTC connected to the SNSMAINS pin. To be able to set the appropriate NTC value and OTP level, the internal current used to measure the external NTC value can be set between 150 µA and 1050 µA in steps of 150 µA. To avoid false triggering, an internal delay occurs before the system enters protection. This delay can be set to different values between 0.5 s and 8 s. The response of the external OTP can be latched, safe restart, or latched after safe restart. The external OTP function can also be disabled. Internal OTP level The internal OTP is fixed at 135 °C. When the internal OTP is triggered, it follows the same response as selected for the external OTP, being either latched, safe restart, or latched after safe restart.

8.8.4.2 PFC general protections

For the brownin level, several values can be selected ranging from 67 V (AC) to 185 V (AC). For the hysteresis between the brownin and brownout level several values can be selected from 2 V (AC) to 17 V (AC). The given values depend on the resistor values in the application and their tolerances. When the mains voltage is below the brownout period for a selectable amount of time, the system enters the brownout state. For this time, several values can be selected ranging from 25 ms to 1.2 s. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller PFC OCP level The PFC OCP level is fixed to Vocp(PFC). The external sense resistor can select the corresponding current value. PFC maximum on-time The maximum on-time of the PFC equals 1 / minimum frequency. Where the minimum frequency set by the MTP and the possible additional frequency jitter defines the minimum frequency. PFC coil short protection When the PFC continuously triggers the OCP for a selectable number of switching cycles, the system enters the protection state. The number of switching cycles can be set to 2500 cycles, 5000 cycles, or 12500 cycles. This function can also be disabled. PFC output OVP The PFC output voltage is measured via the SNSBOOST pin and the DRAINPFC pin. For the OVP at the SNSBOOST pin, the following values can be selected: 2.60 V, 2.63 V, 2.65 V, or 2.70 V. When an OVP is detected at the SNSBOOST pin, the PFC stops switching and continues again when its voltage drops below the regulation level. For the OVP at the DRAINPFC pin, the following values can be selected: 475 V, 500 V, 525 V, or 550 V. To avoid false triggering, a delay can be selected of 100 cycles, 250 cycles, or 1000 switching cycles. During this delay, the output voltage of the PFC is limited to this maximum value. The response of an OVP at the DRAINPFC pin can be latched, safe restart, or latched after safe restart. This function can also be disabled. Valley detection timeout When the PFC MOSFET is off and the current through the PFC coil becomes zero, the coil is demagnetized. Normally, shortly after the demagnetization, the drain voltage starts to ring and a valley is detected. When the system detects demagnetization but does not detect a valley shortly after, the ringing may be too small to detect a valley. So, when demagnetization is detected, it assumes a valley within a specified time. For this time, the following values can be selected: 2 μs, 3 μs, 5 μs, or 7 μs. PFC minimum off-time To avoid false triggering of the demagnetization and valley detection, a minimum off- time of the PFC driver output can be selected. The available values are 500 ns, 750 ns, 1000 ns, and 1500 ns. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8.4.3 LLC general protections

When the LLC starts switching, it expects that its output voltage reaches the regulation level within a maximum start-up time. For the maximum start-up time, the following values can be selected: 25 ms, 50 ms, 100 ms, and 200 ms. LLC brownout level (SNSBOOST) When the voltage at the SNSBOOST drops below a predefined level, the LLC converter enters the protection state. When the SNSBOOST voltage exceeds the brownin level, the LLC converter starts switching again. For the LLC brownout level at the SNSBOOST, a level in the range from 1.0 V to 2.05 V can be selected. LLC brownin level (SNSBOOST) The LLC brownin level defines the minimum voltage at the SNSBOOST pin before the LLC starts switching. For this level, a value ranging from 1.5 V to 2.4 V can be selected. LLC brownout timer (SNSMAINS) When the mains is disconnected, the PFC stops switching after its brownout delay. Normally, the LLC converter continues switching until the input voltage of the LLC drops to below a minimum (Vuvp(SNSBOOST)) level. Especially at a minimum load at the output, the LLC dropping to the minimum level can take a long time. A timer can be initialized that also disables the LLC converter when a brownout is detected at the mains input. For this time, a value can be selected ranging from 125 ms to 6 s. The option that the LLC converter remains switching until its input voltage drops to below a minimum level can also be selected. LLC maximum input voltage (SNSBOOST) When an OVP is detected on the SNSBOOST pin, the PFC always stops switching. The response of the LLC can be set to either continue operation or stop switching until the voltage the SNSBOOST drops to below the PFC output voltage regulation level. A delay can be set to either 5 ms, 50 ms, or 1250 ms. Power limit The maximum output power of the converter is limited by the controller. The limitation ensures that the applied load is below the maximum rating-selected components. For the maximum output power, several levels between 100 % and 200 % of the rated power can be selected. OPP level 1 When the output power exceeds a first OPP level, a first counter is started. When the output power continuously exceeds this OPP level for a selected period, the system enters protection state. For the OPP level, a level between 0 % and −50 % below the selected power limit can be selected. For the time, a value between 50 ms to 40 s can be selected. The response of this protection can be latched, safe restart, or latched after safe restart. This OPP level can also be disabled. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller OPP level 2 When the output power exceeds a second OPP level, a second counter is started. When the output power continuously exceeds this OPP level for a selected period, the system enters protection state. For the OPP level, a level in the range from −10 % to −50 % below the selected power limit can be selected. For the time, a value ranging from 50 ms to 3 s can be selected. The response of this protection follows the selected response of the OPP level 1. This OPP level can also be disabled. OPP duty cycle When the output power exceeds the OPP with a duty cycle of 50 %, the OPP may or may not be triggered. So, the duty cycle at which the OPP is triggered eventually can be set using a parameter to 11 %, 20 %, 33 %, or 50 %. OVP protection In a resonant converter, the voltage at the SUPIC pin reflects the output voltage. When the SUPIC voltage exceeds a defined level, the OVP protection is triggered. The level can be set between 1 V and 16 V above the start level in steps of 1 V. To avoid false triggering, a delay can be set at different values ranging from 10 μs to 800 μs. The response of this protection can be latched, safe restart, or latched after safe restart. This OVP function can also be disabled. OVP duty cycle To minimize the sensitivity of the OVP function, a duty cycle can be set at which the OVP is eventually triggered. This parameter can be set to 11 %, 20 %, 33 %, or 50 %. If, for example, the OVP delay is set to 800 μs, the duty cycle to 50 %, and the SUPIC voltage exceeds the OVP level for 300 μs and drops to below the OVP level for 500 μs, the OVP is never triggered. OCP protection The current in the resonant tank is measured at the SNSCURLLC pin. When the voltage at this pin exceeds the OCP level, the corresponding switch (GATELS or GATEHS) is turned off and the system starts the next cycle. So, the LLC current is limited cycle-by- cycle. If the OCP occurs for a defined number of cycles, the OCP protection is triggered. The number of cycles can be set to different values between 5 and 1000. The response of this protection can be latched, safe restart, or latched after safe restart. The OCP protection function can also be disabled. However, the LLC current remains limited cycle-by-cycle. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

8.8.5 Power good settings

The power good function gives a prewarning to the load that the converter is switched off due to disconnected mains or a triggered protection. Power good time The power good time is the time between the power good signal indicating that the converter is about to be switched off and the time the converter eventually stops switching. This delay can be set to 4 ms, 6 ms, 8 ms, or 10 ms. Power good at OTP The power good signal can give a prewarning when the converter is switched off due to an OTP detection. The OTP can be either an internal or an external OTP. This function can be enabled or disabled. The delay between the transition of the power good signal and the moment that the converter stops switching equals the power good time. Power good at OPP The power good signal can give a prewarning when the converter is switched off due to an OPP detection. The prewarning can be given when the output power exceeds the OPP level1 or OPP level2 for the defined time. This function can be enabled or disabled. The delay between the transition of the power good signal and the moment that the converter stops switching equals the power good time. Power good at mains brownout The power good signal can give a prewarning when the LLC converter is switched off due to a brownout detection at the mains input of the converter. This function can be enabled or disabled. The delay between the transition of the power good signal and the moment that the converter stops switching equals the power good time. Power good at LLC brownout level (SNSBOOST) When the measured voltage at the SNSBOOST pin drops to below the selected LLC brownout level, the LLC converter stops switching. It normally occurs due to a disconnected mains. The power good signal can give a prewarning when the converter is switched off due to this LLC brownout detection. When the voltage at the SNSBOOST drops to below a selectable value, the power good feature is triggered. The level can be selected between 1 V and 2.05 V. Power good at OVP (SNSBOOST) The TEA2017AAT offers a setting option to stop the LLC operation at an SNSBOOST OVP. When the LLC converter is switched off due to an SNSBOOST OVP, the power good signal can give a prewarning. This function can be enabled or disabled. The delay between the transition of the power good signal and the moment the converter stops switching equals the power good time. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller Power good ready delay When the output voltage is in regulation after start-up, power good indicates that the output voltage is in regulation. A delay can be set between the time the output voltage reaches the regulation level and the transition of the power good signal. This delay can be set at different values between 0 s and 1 s. Power good transition time The power good function is combined with the feedback network connected at the SNSFB pin. To avoid that a trigger of the power good function disturbs the regulation loop, its transition time must have a predefined value. This time can be set at 0.85 ms, 1.8 ms, 2.6 ms, or 3.5 ms. Product data sheet Rev. 1 — 14 June 2021

9 Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

0.1 Hz interval

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Table 5. Limiting values...continued

10 Thermal characteristics

107 K/W

60 K/W

Table 6. Thermal characteristics

11 Characteristics

IC; unless otherwise specified. Table 7. Characteristics

IC; unless otherwise specified. Table 7. Characteristics...continued

IC; unless otherwise specified.

IC; unless otherwise specified.

IC; unless otherwise specified.

IC; unless otherwise specified. always be lower than 6.8 mA.

IC; unless otherwise specified. [1] The Vuvp(SUPIC) and Vrst(SUPIC) overlap. When SUPIC drops to below the Vuvp(SUPIC), a general reset may follow. [3] As the minimum limit determines the application design, the maximum limit is not relevant. Figure 29. application diagram

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

Figure 30. Package outline SOT109-1 (SO16)

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

14 Appendix: Ringo parameter settings

A table containing the Ringo parameter settings/IC parameter settings is available in the TEA2017AAT data sheet addendum. The data sheet addendum can be requested from NXP Semiconductors. Product data sheet Rev. 1 — 14 June 2021

Table 8. Revision history

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller

16 Legal information

16.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Product data sheet Rev. 1 — 14 June 2021

NXP Semiconductors TEA2017AAT/2 Digital configurable LLC and multimode PFC controller No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. NXP — wordmark and logo are trademarks of NXP B.V. Product data sheet Rev. 1 — 14 June 2021