TEA1401T

TEA1401T PHILIPS | Alldatasheet

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Technical content

Preliminary specification Supersedes data of 1996 Sep 27 File under Integrated Circuits, IC03

1997 Mar 07

Power plug for the universal mains

1997 Mar 07 2

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T

FEATURES

• Designed for compact power plugs supplying up to 20 W
• Integrated high-voltage power DMOS FET 625 V/1 A
• Operates from all mains supplies (90 to 280 V AC)
• Major design: current regulation at the primary side (no opto-coupler, no secondary electronics)
• Low external/peripheral component count
• Combines accurate constant-voltage source (for supply) and accurate constant-current source (for charging) in one IC
• Foldback feature
• Requires simple input filter as a result of good EMC design
• Overshoot protection (output voltage)
• Protects against under-voltage input, over-current and over-temperature
• 20-pin SO medium-power package. GENERAL DESCRIPTION The TEA1401T is a Self Oscillating Power Supply (SOPS) controller IC that operates directly from the rectified universal mains. It is implemented in the BCD power logic

750 V process and includes the high voltage power switch

making an integrated single-switch flyback converter. Dedicated circuitry for high power efficiency is built-in, which makes a slim-line electronic power plug concept possible. The basic function is a galvanically isolated, combined current and voltage source. No electronics are required at the secondary side of the transformer. Implementation of the TEA1401T renders a simple, small and accurate battery charger system. The TEA1401T is capable of self starting directly from the high voltage mains line. QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V 20 output voltage at pin 20 (DRAIN) 20 times −− 625 V I20 current in MOS switch peak value −− 1A fsw operating switching frequency range CCPFM = 470 pF 5 − 150 kHz I1 input current at pin 1 (Vin), from the high input voltage. VAT can supply from the low voltage auxiliary winding V AT < 10 V (peak) −− 3m A VAT > 10 V (peak); fsw = 90 kHz − 430 530 µA VAT > 10 V (peak); fsw = 150 kHz − 560 660 µA I17 average input current at pin 17 (VAT)V AT < 10 V (peak) −− 300 µA VAT > 10 V (peak) −− 3m A Tamb operating ambient temperature −20 − +85 °C TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TEA1401T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1997 Mar 07 3

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T BLOCK DIAGRAM handbook, full pagewidth MBH570 BAND-GAP TEA1401T VOLTAGE SETTING R OUT COMPENSATION low voltage over voltageIref G OUT COMPENSATION 1/6G OUT 7R I 12R V auxiliary winding V I Jref Jref Jref/3 D RESET maximum on time TEMPERATURE PROTECTION POR SUPPLY TIMING FET turn-off Vin from mains rectifier and filter 1 17 Vin 14313 VICC PFMFOLDBACK C V mains hard wired R ref Vgap VAT secondary stroke primary winding secondary winding C y SINGLE-SHOT D-TYPE FLIP-FLOP foldbackclock TR ITOP REGULATOR LEADING EDGE BLANKING TP 25 µA I U 8 2, 18, 19 5, 6, 15, 16 n.c. GNDC I S R Q Q DRAIN output

4 SOURCE

Q temp max over temperature MINIMUM TRACK- AND- HOLD PEAK DETECTOR IPEAK CORRECTIONCURRENT SETTING LIMITER out 130 µA 2.5 µA inout 1.2 V 90 mV in R I Igm = Fig.1 Block diagram.

1997 Mar 07 4

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T PINNING SYMBOL PIN DESCRIPTION Vin 1 input for rectified and filtered mains voltage for initial powering n.c. 2 not connected C PFM 3 frequency range setting for the pulse frequency modulation SOURCE 4 source of internal MOS switch GND1 5 ground 1 GND2 6 ground 2 R I 7 setting of nominal output current C I 8 frequency compensation of current control loop R ref 9 setting of reference current C V 10 frequency compensation of voltage control loop G OUT 11 nulling of the output conductance of the current source function R V 12 setting of the nominal output voltage FOLDBACK 13 enabling of the foldback feature in the output characteristic VIC 14 buffering of internal supply voltage GND3 15 ground 3 GND4 16 ground 4 V AT 17 input for voltage and power from auxiliary winding for timing and powering n.c. 18 not connected n.c. 19 not connected DRAIN 20 drain of internal MOS switch Fig.2 Pin configuration. handbook, halfpage TEA1401T MBH571 Vin C PFM R I C I R ref C V SOURCE GND1 GND2 n.c. DRAIN GND4 n.c. n.c. VAT GND3 FOLDBACK VIC R V G OUT

1997 Mar 07 5

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T FUNCTIONAL DESCRIPTION The TEA1401T is the heart of a compact flyback DC-to-DC converter, with the IC placed at the primary side. An auxiliary primary winding of the transformer is used for indirect feedback to control the isolated output. This extra winding also powers the device. Control of the converted power is carried out by current mode control and Pulse Frequency Modulation (PFM), as illustrated in Fig.1. The primary current is sensed by a comparator. The frequency is determined by the maximum of the transformer demagnetizing time and the time of the voltage controlled monostable multivibrator (single-shot). The TEA1401T senses signals at the primary side of the transformer to reconstruct the current and voltage which are present at the secondary side. Comparison of these reconstructions with the internal reference leads to adaptation of the turn-off current level for the primary switch and also to adaptation of the single-shot time. Current control(see Fig.3) The current through the main switch is measured by the peak detector shown in Fig.1. The timing block generates a signal ‘secondary stroke’ which is logic 1 when the voltage of the auxiliary winding is negative. The measured peak current, multiplied by the ratio of the resistors connected to pins 4 (SOURCE) and 7 (R I), is integrated by a capacitor during the secondary stroke. In this way a reconstruction is made of the secondary charge transfer. The charge estimation Q-pulse’ (see Fig.3) is drawn from the capacitor at pin 8 (C I) for each pulse. Also this capacitor, the charge error memory, is continuously charged with the reference current. In this way the real (reconstructed) current is compared with the reference yielding the voltage V CI at pin 8. The VCI level provides the turn-off current level for the main switch and the single-shot time. Input from the voltage part of the loop is used to improve the current reconstruction, resulting in a lower output conductance of the complete converter. In the block diagram this is denoted as ‘G OUT compensation’. The block ‘IPEAK correction’ is able to increase the output from the peak detector to improve line regulation. Voltage control The voltage from the auxiliary winding is sensed as a measure of the secondary voltage. During the secondary stroke the auxiliary winding delivers a negative voltage. This voltage is converted into a current by an external resistor at the R V pin between the transformer winding and virtual ground. This current is compared with a reference current. The difference between the reconstructed voltage and the reference is integrated during the secondary stroke by a capacitor on the C V pin. The voltage on the CV pin is transferred, via a ‘track-and-hold’ circuit, to the connection point of the current and the voltage loop. The ‘track-and-hold’ output provides the turn-off current level for the main switch and the single-shot time. The ‘track-and-hold’ circuit itself is present for loop stability. Input from the current part of the loop is used to improve the voltage reconstruction, resulting in lower output impedance of the complete converter (analog to the current control). In the block diagram this is denoted as OUT compensation’. Combined control The two loops, I loop and V loop, each request their own turn-off current level for the main switch and single-shot time. The block ‘minimum’ in the block diagram outputs the lowest value of the two, preventing the output voltage or current from exceeding its nominal value. The output characteristics of the power plug are displayed in Fig.4 (with enabled foldback option). Optional foldback(see Fig.4) The optional foldback feature of the TEA1401T is performed by sensing the voltage of the auxiliary winding at the end of the flyback stroke. It is actually not a voltage, but the current through pin 12 (R V) that is measured. When this voltage is low, the reference current in the current control loop is set to the low level J ref/3. The steep foldback enables a turn-down of the converter by short-circuiting the output on the secondary side, for example by a switch-transistor.

1997 Mar 07 6

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T Overshoot protection Sensing the voltage during the previously mentioned flyback stroke is also used to signal a voltage overshoot. A voltage overshoot will delay and minimize the next active stroke. This is achieved by discharging the capacitor in the ‘track-and-hold’ circuit (see Fig.1). In this way the power level of the converter is turned down to its minimum immediately in case of a voltage overshoot. Minimum output power Under no-load condition an additional external pre-load resistor (or Zener diode) is necessary to keep the output voltage at its nominal value (or at the Zener diode voltage). This is due to the fact that under no-load condition and also at voltage overshoot the converter will keep operating instead of being switched off. Although the converter then will operate with a short active stroke and a low frequency, energy is still being converted to the output. To prevent excessive output voltage this energy has to be dissipated. The advantage of a pre-load resistor over a Zener diode is that the converter will stay in regulation, maintaining its fast response to load variations. Duty cycle control The momentary power level required by the I/V control loop is achieved by controlling the duty cycle of the converter by two actions. First the peak value of the primary current is controlled using a cycle-by-cycle current control. Secondly the pulse frequency is modulated. There is a broad region in which both regulation principles are active simultaneously. Both controls have a minimum and a maximum value which are set by the resistor on the SOURCE pin and the capacitor on the C PFM pin. SOPS and PFM The switching frequency fsw is set by the transformer demagnetizing time or the frequency control block within the IC (block ‘single-shot’ in Fig.1). At a high power level the transformer determines the frequency. This mode of operation is called Self Oscillating Power Supply (SOPS), and provides maximum efficiency (for a non-continuous conducting flyback converter). In SOPS the next primary stroke is started right after the previous secondary stroke has ended. Timing information is collected from the auxiliary winding. The SOPS frequency will increase when the power level decreases. The frequency however is limited by the PFM controller (single-shot). When the PFM controller takes over, the frequency will be proportional to the required power level. Thus the frequency is reduced when the power level decreases. In PFM there is a variable dead time after the secondary stroke. The next primary stroke is started after the single-shot time has ended. Supply Initially the IC is powered by a high DC input voltage at pin 1 (V in). In operation the auxiliary winding takes over. In the event that the auxiliary winding delivers insufficient power for the internal circuitry of the IC, this deficit is supplemented again via pin 1 (V in). The supply voltage for the internal circuitry is buffered with an external capacitor at pin 14 (VIC). When the auxiliary winding powers the IC, energy is stored during the active stroke. The rest of the time energy is supplied by the buffer capacitor. Protections The IC has a cycle-by-cycle current regulation, with a built-in setting for the absolute maximum voltage across the current sense resistor. Also a maximum time is set for the duration of the active stroke. A provision for temperature shut down has been implemented.

1997 Mar 07 7

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T Fig.3 Reconstruction of secondary charge transfer. handbook, halfpage MBH580 Vauxiliary (−Vsecondary) t t Iprimary x n Q pulse' Q pulse Isecondary Fig.4 V/I ideal characteristics. handbook, halfpageVOUT (V) Vnominal MBH575 IFOLDBACK Inominal IOUT (A)

1997 Mar 07 8

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltages are measured with respect to ground; positive currents flow into the chip; pins 7, 9, 11 and 12 are not allowed to be voltage driven. The voltage ratings are valid provided other ratings are not being violated; current ratings are valid provided the maximum power rating is not violated. QUALITY SPECIFICATION According to “SNW-FQ-611E” . This specification can be found in the“Quality reference Handbook”. The handbook can be ordered using the code 9397 750 00192. HANDLING Every pin withstands the ESD test in accordance with the ‘Human Body Model’ except for pins Vin and DRAIN of which the performance is:

• Pin Vin: 1000 V in accordance with the ‘Human Body Model’
• Pin DRAIN: 1500 V in accordance with the ‘Human Body Model’. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Voltages V1 pin 1 (Vin) continuous −0.4 +400 V V3 pin 3 (CPFM ) −0.4 − V V4 pin 4 (SOURCE) −0.4 +2 V V8 pin 8 (CI) −0.4 − V V10 pin 10 (CV) −0.4 − V V13 pin 13 (FOLDBACK) −0.4 V IC + 0.4 V V14 pin 14 (VIC) −− V V17 pin 17 (VAT) −20 +60 V V20 pin 20 (DRAIN) continuous − +550 V Currents I3 pin 3 (CPFM ) − 0.2 mA I4 pin 4 (SOURCE) −1+ 1A I7 pin 7 (RI) −0.2 0 mA I9 pin 9 (Rref) −0.2 0 mA I11 pin 11 (GOUT ) −0.2 0 mA I12 pin 12 (RV) −0.2 0 mA I14 pin 14 (VIC) −300 +1 mA I20 pin 20 (DRAIN) −1+ 1A General Ptot total power dissipation T amb <5 0°C − 1.4 W Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −20 +85 °C Tvj virtual junction temperature −20 +145 °C

1997 Mar 07 9

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T THERMAL CHARACTERISTICS Note 1. Pins GND1, GND2, GND3 and GND4 connected to sufficient copper area on the printed-circuit board. CHARACTERISTICS Vin= 330 V; VAT = 36 V; RRref=3 1kΩ ; Tamb =2 5°C; IC not in current foldback mode; no over-voltage; no over-temperature; unless otherwise specified. All voltages are measured with respect to ground; currents are positive when flowing into the IC. SYMBOL PARAMETER VALUE UNIT R th j-a thermal resistance from junction to ambient in free air(1) 65 K/W SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply Vin input voltage 60 − 400 V input voltage limit 20 times 500 −− V Iin input supply current to VIC and gate V AT = 3 V 1.7 2.3 2.9 mA Iin(gate) input supply current to gate only VAT =3 6V ; non-switching 130 230 330 µA VIC regulated supply voltage at VIC VAT = 3 V 6.7 7.2 7.7 V VAT = 36 V 7.2 7.9 8.6 V ΔVIC/ΔR O voltage decrease at VIC due to its output impedance VAT =2 0V ; IVIC =0t o−100 mA −− 200 mV VPOR power-on reset voltage level, with respect to regulated VIC −0.7 −0.5 −0.1 V ILI(VAT) leakage current into pin VAT VAT =6V −− 2 µA VVAT VAT input voltage −20 − +60 V IVAT VAT input current V AT = 70 V; IVIC = 0 m A 1 11 41 7m A Pulse peak modulator VSOURCE(max) maximum peak voltage at pin SOURCE VCV =V CI =4V ; 1.09 1.19 1.29 V VCV =V CI =4V ; 1.05 1.15 1.25 V VSOURCE(min) minimum peak voltage at pin SOURCE VCV =V CI =0V ; ton >ton(min) 75 95 120 mV ΔVCV-SOURCE level shift voltage VCI to VSOURCE VCV =4V − 2 − V ΔVCI-SOURCE level shift voltage VCV to VSOURCE VCI =4V − 2 − V ton(min) minimum on-time (the minimum time duration of the active stroke) V-mode 490 550 610 ns I-mode 675 750 825 ns dV SOURCE dV SOURCE

1997 Mar 07 10

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T Pulse (maximum) frequency modulator R discharge discharge resistance to ground V CPFM = 1.0 V 0.3 0.6 0.9 k Ω Icharge(min) minimum charge current V CV =V CI =0V − 2.5 −µ A Icharge(max) maximum charge current V CV =V CI =4V − 130 −µ A Icharge(fix) fixed charge current active stroke − 25 −µ A G transferCI transfer from pin CI to pin CPFM VCI = 2.1 to 3.1 V −− 104 −µ A/V G transferCV transfer from pin CV to pin CPFM VCV = 2.1 to 3.1 V −− 104 −µ A/V Vsw(high) high switching voltage level at pin CPFM − 1.0 − V Vsw(low) low switching voltage level at pin CPFM DC at pin CPFM − 0.17 − V Vton(max) maximum on-time ton(max) switching voltage level at pin CPFM − 0.54 − V ΔfPFM frequency spread of the internal oscillator; ; VCI =V CV = 2.1 to 3.1 V 93 104 115 µA/V2 Δton(max) spread of ton(max); VCI =V CV =4V ; VSOURCE <1V 19 22 25 V/mA SOPS Vdemag demagnetization recognition voltage level −250 −130 −10 mV Current regulation Vi(pkc) VPEAK -I converter input voltage 0.6 − 1.4 V Vi(pkc)(slope) VPEAK -I converter input voltage slope 0.1 − 1.0 V/ µs Vpkc(offset) VPEAK -I converter systematic offset −− 13 − mV Itransfer(RI-CI) R Ito CI current transfer I GOUT =0 −− 0.99 − A/A Itransfer(GOUT-CI) G OUT to CI current transfer I RI =0 − 0.17 − A/A IPEAKcor current through sense capacitor in block ‘IPEAK correction’ (see Fig.1); sunk by pin FOLDBACK under test conditions: in lasting active stroke 71 0 1 3 µA Ichain(CI) C I chain error current −3.3 −1.0 +1.3 µA Ictrl(error) current control total measured error −5 − +5 % SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT G transferCI V sw(high) G transferCV V sw(high) V ton(max) Icharge(fix) dV SOURCE

1997 Mar 07 11

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T Voltage regulation Itransfer(RV-CV) R V to CV current transfer V RI < 0.5 V −− 1.00 − A/A Vthres(RI) R OUT converter voltage threshold at pin RI − 0.65 − V gm(ROUT) R OUT converter transconductance ICV /VRI VRI > 0.7 V − 4.4 −µ A/V Ichain(CV) C V chain error current I CV measurement, analogue to that of Ichain(CI) −1.2 0 +1.2 µA Vctrl(error) total error of voltage control loop in IC −4 − +4 % Current foldback; FOLDBACK (pin 13) connected to VIC (pin 14) IRV /IRref current ratio discrimination level 0.05 0.1 0.2 A/A ICI(foldback)/ICI(normal) current ratio 0.26 0.33 0.4 A/A Voltage overshoot IRV /IRref current ratio discrimination level 1.1 1.2 1.3 A/A V4(overshoot) peak voltage at pin 4 at overshoot; ton >ton(min) 75 95 120 mV Icharge(overshoot) C PFM charge current at overshoot; VCPFM =1V − 2.5 −µ A References Vref R ref reference voltage 1.24 1.28 1.32 V Itransfer(Rref-CI) R refto CI current transfer − 0.99 − A/A Itransfer(Rref-CV) R refto CV current transfer − 0.99 − A/A Output stage ILO DRAIN output leakage current V DRAIN = 550 V −− 100 µA VDRAIN(cont) DRAIN output voltage continuous 0 − 550 V VDRAIN(lim) DRAIN output voltage limit 20 times 625 −− V ΔVDRAIN-SOURCE DRAIN-SOURCE voltage drop T amb =2 5°C; IDRAIN = 500 mA −− 6V Tamb = 125°C; IDRAIN = 500 mA −− 11 V tf DRAIN fall time V in= 300 V; no external capacitor at pin DRAIN − 100 − ns Temperature protection T prot(max) maximum temperature threshold 132 139 146 °C Tprot(hyst) hysteresis temperature −± 1 −° C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Mar 07 12

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T OUTPUT CHARACTERISTICS OF COMPLETE POWER PLUG Output power Maximum switching frequency is approximately 150 kHz. Internal MOS maximum switch current is 0.5 to 1 A. Maximum handled power with universal mains is approximately 10 W. Accuracy of current regulation The accuracy of the IC itself is±5%. Accuracy of the complete converter is approximately±7%, depending on the transformer and other components. Accuracy of voltage regulation The voltage loop inside the IC has an accuracy of±4%. Accuracy of the complete converter is approximately±7%. Voltage overshoot When voltage overshoot is detected (during the secondary stroke), the IC first has to wait until this stroke is finished in the normal way. After that the power level of the converter is set to the minimum level within one cycle. Voltage overshoot is triggered at 20% above nominal output voltage. If at the moment that overshoot is detected, the transformer still contains energy; this energy can cause some further increase of the output voltage. In case of a pre-load resistor across the output, the converter keeps the output voltage under static conditions on its nominal value. Voltage overshoot will only be a dynamic phenomenon in this situation. When only a Zener diode is applied, the Zener voltage will appear at the output continuously under no-load conditions. Efficiency An efficiency of 72 to 75% at maximum output power can be achieved for a complete 8 W converter designed for universal mains. Ripple The magnitude of the ripple in output voltage is determined by the duty cycle of the converter, the output current level and the value and Electrical Series Resistance (ESR) of the output capacitor. A minimal ripple is obtained in a system designed on a maximum duty cycle of 50% under normal operating conditions and a minimized dead time. Ripple is inversely proportional to input and output voltages. INPUT CHARACTERISTICS OF COMPLETE POWER PLUG Input voltage The input voltage range comprises the universal AC-mains (90 to 280 V). The input transient voltage must be filtered to a maximum of 450 V.

1997 Mar 07 13

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T

APPLICATION INFORMATION

A converter with the TEA1401T consists of an input filter, a transformer with a third winding (auxiliary), a secondary diode with a capacitor plus other external components as illustrated in Fig.5. The load (user) determines the operating mode of the power plug, current or voltage source. The capacitor at V IC (pin 14) buffers the internal supply voltage of the IC which is powered via Vin and/or VAT . A sense resistor converts the primary current into a voltage at SOURCE (pin 4). The voltage of the auxiliary winding is converted into a current through resistor RRV and fed to pin RV. Nominal current and voltage are set by resistors RRI and R RV . Output conductance of the current is nullified by resistor RRGOUT . The band-gap voltage is converted into a reference current by resistor RRref. Capacitor CCPFM determines the frequency in non-SOPS mode. There are two loop capacitors, one for current control (CI), and the other for voltage control (CV). The impedance at C V (pin 10) can be made more complex, if required for stability. The secondary diode also protects the power plug against a short-circuited output (during the primary stroke), and must therefore be placed inside the power plug cabinet. A pre-load resistor or a Zener diode is required to handle an open output which will cause an excessively high output voltage. This is because the power plug continues operating, provided it is connected to the mains, and thus continuously converts energy to the secondary side, even though it is a low, predefined level. If a Zener diode is used, the Zener voltage must be selected with care, because the over-voltage protection of the IC should not be blocked. If the Zener diode voltage is too close to the nominal output voltage of the converter no voltage overshoot will be detected by the IC, causing increased dissipation in the Zener during switching of the load. A complete diagram with preliminary component values is shown in Fig.6. More detailed information can be found in the “Application Note AN96096”.

1997 Mar 07 14

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T handbook, full pagewidth MBH573 GND FOLDBACK VIC C VIC 5, 6, 15, 16 C I C CI R I R RI C PFM C CPFM R ref R Rref R sense G OUT R GOUT9 SOURCE DRAIN POWER PLUG Vin C V C CV R V VAT VOUT TEA1401T R RV USER VOUT USER mains hard wired C y Fig.5 Power plug with TEA1401T.

1997 Mar 07 15

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T handbook, full pagewidth MBH574 GND 1 µF (10%) 8.2 nF (10%) 10 nF (10%) 470 pF (5%) FOLDBACK VIC C I R I C PFM R ref R sense G OUT SOURCE DRAIN BZD27C150 BYD33J mains filter VDC <450 V (also transient) BYD77B Vin C f1 rectifier bridge 800 V at 0.5 A C f2 C V R V VAT VOUT TEA1401T C1 Z2 USER (1) mains hard wired kΩ (1%) 30 kΩ (1%) 2.2 Ω (1%) 2.2 nF 100 kΩ (1%) 240 kΩ (1%) C VIC 5, 6, 15, 16 C CI R RI C CPFM R Rref R GOUT C CV R RV C y Fig.6 Power plug with TEA1401T; completed circuit diagram. (1) Optional short-circuit provision based on FOLDBACK feature. C1 = 330µF 16 V 10%; Cf1=C f2= 6.8µF 385 V 10%. L1 = inductance filter = 560µH 10%; L2 = 62 turns 0.14 copper inductance; L3 = 8 turns 0.4 copper inductance; L4 = 8 turns 0.14 copper inductance; core EF16/16/5 gap 130µ. R1 = Rfuse=1 8Ω 5% at 0.5 W. Z2 = BZV55B12 2% at 0.4 W.

1997 Mar 07 16

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T PACKAGE OUTLINE UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 SOT163-1 92-11-17 95-01-24 w M bp detail X Z e D y 0.25 075E04 MS-013AC pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.050 1.4 0.0550.42 0.39 0.043 0.039 0.035 0.0160.01 0.25 0.01 0.0040.043 0.0160.01 0 5 10 mm scale X θ AA 1 A 2 H E Lp Q E c L v M A (A )3 A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1997 Mar 07 17

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow.
• The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150°C within 6 seconds. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

1997 Mar 07 18

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Where application information is given, it is advisory and does not form part of the specification.

1997 Mar 07 19

Philips Semiconductors Preliminary specification Power plug for the universal mains TEA1401T NOTES

Internet: http://www.semiconductors.philips.com Philips Semiconductors – a worldwide company © Philips Electronics N.V. 1997 SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria:Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil:see South America Bulgaria:Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

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