TEA1065T

TEA1065 PHILIPS | Alldatasheet

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Product specification File under Integrated Circuits, IC03A March 1994 INTEGRATED CIRCUITS TEA1065 Versatile telephone transmission circuit with dialler interface

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065

FEATURES

• Current and voltage regulator mode with adjustable static resistances
• Provides supply for external circuitry
• Symmetrical high-impedance inputs for piezoelectric microphone
• Asymmetrical high-impedance input for electret microphone
• DTMF signal input with confidence tone
• Mute input for pulse or DTMF dialling
• Power-down input for pulse dial or register recall
• Digital pulse input to drive an external switch transistor
• Receiving amplifier for magnetic, dynamic or piezoelectric earpieces
• Large gain setting range on microphone and earpiece amplifiers
• Line loss compensation facility, line current dependent (on microphone and earpiece amplifiers)
• Adjustable gain control
• DC line voltage adjustment facility GENERAL DESCRIPTION The TEA1065 is a bipolar integrated circuit which performs all speech and line interface functions that are required in fully electronic telephone sets with adjustable DC mask. The circuit performs electronic switching between dialling and speech internally.

ORDERING INFORMATION

1. SOT101-1; 1998 Jun 18. 2. SOT137-1; 1998 Jun 18. QUICK REFERENCE DATA EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE TEA1065 24 DIL plastic SOT101L TEA1065T 24 SO24 plastic SOT137A SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V LN line voltage I line= 15 mA 4.25 4.45 4.65 V Iline normal operation line current range 10 − 150 mA ICC internal supply consumption power-down input LOW − 1.14 1.5 mA power-down input HIGH − 73 105 µA VCC supply voltage for peripherals Iline= 15 mA; MUTE input HIGH IP = 1.2 mA 2.7 −− V IP = 1.55 mA 2.5 −− V G V voltage gain range microphone amplifier 30 − 46 dB earpiece amplifier 20 − 45 dB ΔG V line loss compensation gain control range −5.5 −5.9 −6.3 dB Tamb operating ambient temperature range −25 −+ 75 °C

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Fig.1 Block diagram. handbook, full pagewidth MBA557 CURRENT REFERENCE LINE CURRENT CONTROL CONTROL CURRENT SUPPLY AND REFERENCE 2216 VEE REG AGC STAB CURL GAS2 GAS1 QR − QR + GAR 19 dB 23 9 15 VSI DPI IR MIC + MIC − DTMF MUTE PD VCC −TEA1065 SLPE24 LN1 BANDGAP REFERENCE DOC REFI13 VBG11

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 PINNING SYMBOL PIN DESCRIPTION LN 1 positive line terminal GAS1 2 gain adjustment; sending amplifier GAS2 3 gain adjustment; sending amplifier QR − 4 inverting output; receiving amplifier QR + 5 non-inverting output; receiving amplifier GAR 6 gain adjustment; receiving amplifier MIC − 7 inverting microphone input MIC + 8 non-inverting microphone input STAB 9 current stabilizer DPI 10 digital pulse input VBG 11 bandgap output reference DOC 12 drive current output REFI 13 reference voltage input VSI 14 voltage sense input CURL 15 current limitation input V EE 16 negative line terminal IR 17 receiving amplifier input PD 18 power-down input DTMF 19 dual-tone multifrequency input MUTE 20 MUTE input V CC 21 positive supply decoupling REG 22 voltage regulator decoupling AGC 23 automatic gain control input SLPE 24 slope (DC resistance) adjustment Fig.2 Pinning diagram. handbook, halfpage DPI VBG DOC CURL VSI REFI TEA1065 MBA551 LN GAS1 GAS2 QR − QR + GAR MIC − MIC + STAB SLPE AGC REG VCC DTMF PD MUTE IR VEE

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 FUNCTIONAL DESCRIPTION Supply: VCC , LN, SLPE, REG and STAB The circuit and its peripherals are usually supplied from the telephone line. The circuit develops its own supply voltage at V CC (pin 21) and regulates its voltage drop between LN and SLPE (pins 1 and 24). The internal supply requires a decoupling capacitor between V CC and VEE (pin 16); the internal voltage regulator has to be decoupled by a capacitor from REG (pin 22) to V EE . The internal current stabilizer is set by a 3.6 kΩ resistor connected between STAB (pin 9) and VEE . The TEA1065 can be set either in a DC voltage regulator mode or in a DC current regulator mode. The DC mask can be selected by connecting the appropriate external components to the dedicated pins (VSI, REFI, DOC, VBG). When the DC current regulator mode is not required it can be cancelled by connecting pin VSI to V EE ; pins REFI, VBG and DOC are left open-circuit. Voltage regulator mode The voltage regulator mode is achieved when the line current is less than the current Iknee as illustrated in Fig.3. With R13 = R14 = 30 kΩ , the current Iknee = 30 mA (Ip = 0 mA). This line current value will be reached when the voltage on pin VSI (almost equal to the voltage on pin SLPE) exceeds the voltage on pin REFI (equal to the voltage on pin VBG divided by the resistor tap R13, R14). For other values of R13 and R14, the I knee current is given by the following formula: Iknee =ICC + IP + (VBG/R9)× {R14/(R14+ R13)} − (R15/R9)× IO (VSI) ICC is the current required by the circuit itself (typ. 1.14 mA). IP is the current required by the peripheral circuits connected between VCC and VEE . IO(VSI)is the output current from pin VSI (typ. 2.5µA). The DC slope of the Vline/Ilinecurve is, in this mode, determined by R9 (R9 = R9a+ R9b) in series with the rds of the external line current control transistor (see Fig.4; rds = ∂VGS /∂ID at VGS =V DS ). Current regulator mode The current regulator mode is achieved when the line current is greater than Iknee. In this mode, the slope of the Vline/Ilinecurve is approximately 1300Ω with R9 = 20Ω , R16 = 1 MΩ , R13 = R14 = 30 kΩ . For other values of these resistances, the slope value can be approximated by the following formula: Fig.3 Voltage and current regulator mode. handbook, full pagewidth MBA567 line current Iknee voltage regulator mode current regulator mode set voltage 0 0

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 The DC current flowing into the set is determined by the exchange supply voltage (Vexch), the DC resistance of the subscriber line (Rline) and the DC voltage on the subscriber set (see Fig.4). If the line current exceeds I CC + 0.3 mA, required by the circuit itself (ICC ≈ 1.14 mA), plus the current Ip required by the peripheral circuits connected to VCC then the voltage regulator will divert the excess current via LN. VLN =V ref+ ISLPE × R9 = Vref+ (Iline− ICC − 0.3× 10−3 − Ip)× R9 where: Vrefis an internally generated temperature compensated reference voltage of 4.18 V and R9 is an external resistor connected between SLPE and V EE . The preferred value of R9 is 20Ω . Changing R9 will influence the microphone gain, gain control characteristics, sidetone and the maximum output swing on LN. In this instance, the voltage on the line (excluding the diode rectifier bridge; see Fig.4) is: V line=V LN + VGS + R16 × IDOC where: VGS is the voltage drop between the gate and source terminal of the external line current control transistor and I DOC is the current sunk by pin DOC (IDOC = 0 in the voltage regulator mode and increases with Ilinein the current regulator mode). Under normal conditions ISLPE >> ICC + 0.3 mA+ Ip and for the voltage regulator mode (Iline< Iknee), the static behaviour of the circuit is equal to a 4.18 V voltage regulator diode with an internal resistance of R9 in series with the V GSon of the external line current control transistor. For the current regulator mode (Iline> Iknee), the static behaviour of the circuit is equal to a 4.18 V voltage regulator diode with an internal resistance of R9 in series with the V GSon of the external line current control transistor and also in series with a DC voltage source R16 × I DOC (the preferred value of R16 is 1 MΩ at this value the current IDOC is negligible compared to Iline). In the audio frequency range the dynamic impedance between LN and VEE is equal to R1 (see Fig.8). The internal reference voltage Vrefcan be adjusted by means of an external resistor RVA . This resistor, connected between LN and REG, will decrease the internal reference voltage. When R VA is connected between REG and SLPE the internal reference voltage will increase. The maximum allowed line current is given in Figs 5 and 6, where the current is shown as a function of the required reference voltage, ambient temperature and applied package. Fig.4 Supply arrangement. handbook, full pagewidth MBA550 SLPESTABREG V EE IpLNDOC 12 112 24 1622 9 TEA1065 AC DC peripheral circuitsC10.3 mA ISLPE + 0.5 mA R line R16 R exch Vexch Iline Vline R1 VCC ICC C3 R5 R9 IDOC

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 The current Ip, available from VCC for supplying peripheral circuits, depends on the external components and on the line current. Fig.7 shows this current for V CC > 2.2 V and for VCC > 3 V, where 3 V is the minimum supply voltage for most CMOS circuits including a diode voltage drop for a back-up diode. If MUTE is LOW the available current is further reduced when the receiving amplifier is driven (earpiece amplifier supplied from V CC ). Fig.5 TEA1065 safe operating area. Tamb (1) 65 °C (2) 75 °C Ptot 1.2 W 1.0 W handbook, halfpage 21 2 170 150 110 130 MBA570 46 8 1 0 VLN -VSLPE (V) (2) (1) ILN (mA) Fig.6 TEA1065T safe operating area. Tamb (1) 35 °C (2) 45 °C (3) 55 °C (4) 65 °C (5) 75 °C Ptot 1.2 W 1.07 W 0.93 W 0.8 W 0.67 W handbook, halfpage 21 2 170 150 110 130 MBA571 46 8 1 0 VLN -VSLPE (V) (2) (1) (3) (4) (5) ILN (mA)

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Fig.7 Maximum current Ip available from VCC for external (peripheral) circuitry with VCC > 2.2 V and VCC > 3 V. Curve (1) and (3) are valid when the receiving amplifier is not driven or when MUTE = HIGH, curves (2) and (4) are valid when MUTE = LOW and the receiving amplifier is driven, Vo(rms)= 150 mV, RL = 150Ω (asymmetrical). Iline= 15 mA at VLN = 4.45 V R1 = 620Ω R9 = 20Ω handbook, halfpage 012 4 MBA569 VCC (V) IP (mA) (2) (3) (4) (1) Fig.8 Equivalent circuit impedance between LN and VEE . Leq =C 3 × R9 × R p R p = 17.5 kΩ handbook, halfpage MBA552 20 Ω REG LN 4.7 µF R p Vref Leq SLPE VCC VEE

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Microphone inputs MIC+ and MIC− and gain adjustment connections GAS1 and GAS2 The TEA1065 has symmetrical microphone inputs, its input impedance is 40.8 kΩ (2× 20.4 kΩ ) and its voltage gain is typ. 38 dB with R7 = 68 kΩ . Either dynamic, magnetic or piezoelectric microphones can be used, or an electret microphone with a built-in FET buffer. Arrangements for the microphones types are illustrated in Fig.9. The gain of the microphone amplifier is proportional to external resistor R7, connected between GAS1 and GAS2, which can be adjusted between 30 dB and 46 dB to suit the sensitivity of the transducer. An external 100 pF capacitor (C6) is required between GAS1 and SLPE to ensure stability. A larger value of C6 may be chosen to obtain a first-order low-pass filter. The “cut-off” frequency corresponds with the time constant R7 × C6. Fig.9 Microphone arrangements. (a) magnetic or dynamic microphone, the resistor (1) may be connected to reduce the terminating impedance, or for sensitive types a resistive attenuator can be used to prevent overloading the microphone inputs; (b) electret microphone; (c) piezoelectric microphone. handbook, full pagewidth MBA553 VEE VCC (1) (a) (b) (c) MIC + MIC − MIC − MIC + 7MIC − MIC +

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 MUTE input When MUTE = HIGH the DTMF input is enabled and the microphone and receiving amplifier inputs are inhibited. When MUTE = LOW or open-circuit the DTMF input is inhibited and the microphone and receiving amplifier inputs are enabled. Switching the MUTE input will cause negligible clicks at the earpiece outputs and on the line. An electrostatic discharge protection diode is connected between pin MUTE and pin V CC (pins 20 and 21). Dual-tone multifrequency input DTMF When the DTMF input is enabled, dialling tones may be sent onto the line. The voltage gain from DTMF to LN is typ. 12.5 dB less than the gain of the microphone amplifier and varies with R7 in the same way as the gain of the microphone amplifier. This means that the tone level at the DTMF input has to be adjusted after setting the gain of the microphone amplifier. When R7 = 68 kΩ the gain is typically 25.5 dB. The signalling tones can be heard in the earpiece at a low level (confidence tone). Receiving amplifiers: IR, QR+, QR− and GAR The receiving amplifier has one input IR and two complementary outputs, QR+ (non-inverting) and QR − (inverting). These outputs may be used for single-ended or differential drive, depending on the type and sensitivity of the earpiece used (see Fig.10). Gain from IR to QR+ is typically 31 dB with R4 = 100 kΩ , which is sufficient for low-impedance magnetic or dynamic earpieces which are suitable for single-ended drive. By using both outputs (differential drive) the gain is increased by 6 dB. Differential drive can be used when earpiece impedance exceeds 450Ω as with high impedance dynamic, magnetic or piezoelectric earpieces. The output voltage of the receiving amplifier is specified for continuous-wave drive. The maximum output voltage will be higher under speech conditions where the ratio of peak and RMS value is higher. The gain of the receiving amplifier can be adjusted over a range of−11 dB to+8 dB to suit the sensitivity of the transducer that is used. The gain is proportional to external resistor R4 connected between GAR and QR+. Two external capacitors, C4 = 100 pF and C7 = 1 nF, are necessary to ensure stability. A larger value of C4 may be chosen to obtain a first-order low-pass filter. The “cut-off” frequency corresponds with the time constant R4× C4. Fig.10 Alternative receiver arrangements: (a) dynamic earpiece with an impedance less than 450Ω ; (b) dynamic earpiece with an impedance more than 450Ω ; (c) magnetic earpiece with an impedance more than 450Ω , resistor (1) may be connected to prevent distortion (inductive load); (d) piezoelectric earpiece, resistor (2) is required to increase the phase margin (stability with capacitive load). handbook, full pagewidth MBA554 (1) QR − QR +5 VEE16 QR − QR +5

4 QR −

(2) QR − QR +5 (a) (b) (c) (d)

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Automatic gain control Automatic compensation of line loss is obtained by connecting a resistor (R6) between AGC and VEE . The automatic gain control varies the gain of the microphone amplifier and receiving amplifier in accordance with the DC line current (see DTMF gain is not affected by this feature. If automatic line loss compensation is not required the AGC pin can be left open-circuit, the amplifiers then give their maximum gain. Fig.11 Typical 0.5 km line cell model used for automatic gain control optimization. handbook, full pagewidth MBA572 34.8 Ω34.8 Ω 75 µH75 µH 34.8 Ω34.8 Ω 75 µH75 µH 24.3 nF 24.3 nF 13 nF Fig.12 Variation of gain as a function of line current with R6 as a parameter; R9 = 20Ω . handbook, full pagewidth MBA549 ΔG v (dB) Iline (mA) 806040200 118 kΩ 147 kΩ86.6 kΩ R6 = ∞ R6 = 187 k Ω

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Power-down input PD During pulse dialling or register recall (timed-loop-break) the telephone line is interrupted, consequently it provides no supply for the transmission circuit and the peripherals connected to V CC . These gaps have to be bridged by the charge in the smoothing capacitor C1. The requirement on this capacitor is relaxed by applying a HIGH level to the PD input during the loop-break. This reduces the internal supply current from typ. 1.14 mA to 73µA. A HIGH level at PD also disconnects the capacitor at REG which results in the voltage stabilizer having no switch-on delay after line interruptions. This results in no contribution of the IC to the current waveform during pulse dialling or register recall. When this facility is not required PD may be left open-circuit or connected to V EE . An electrostatic discharge protection diode is connected between pin PD and V CC . Digital pulse input DPI A HIGH level at DPI creates a current which flows from pin DOC to VEE in order to interrupt the line current by the external line current control transistor (see Fig.18; MOSFET BUK554). A LOW level (or pin left open-circuit) disables this current to provide the normal DC regulation (voltage or current). A simple application without regulation of current in pulse dialling mode is given in Fig.18. When DPI is activated (HIGH level), the external line current control transistor is switched off resulting in no current in the TEA1065. The voltage on pin SLPE becomes zero and capacitor C15 discharges cancelling the current regulation when DPI becomes inactive (LOW level). To provide a constant regulation (in speech mode and pulse mode), an external transistor is required to keep C15 charged during DPI active (see Fig.19 in which the Field Effect Transistor BSJ177 is directly driven by the DPI signal). An electrostatic discharge protection diode is connected between pin DPI and pin V CC . Voltage sense input and reference voltage input VSI and REFI The voltage on pin VSI represents the DC voltage of pin SLPE. The RC filter (R15× C15) is also intended to disable the DC regulation when C15 is shunted or not yet charged (especially directly after hook-off). The time constant R15× C15 determines approximately the time when no regulation (except CURL pin limitation) is activated. The voltage applied on pin REFI represents a fraction of the bandgap reference voltage given by pin VBG (resistor tap R13 and R14) in order to determine I knee. Drive current output DOC Pin DOC drives the external line current control transistor in order to achieve line interruption during pulse dialling (or register recall) and also the DC slope when I line> Iknee. The current sunk by pin DOC is determined by the voltage on pin VSI in comparison with the voltage on pin VBG divided by the resistor tap R13 and R14. When pin DPI is activated, pin DOC changes to a low voltage (by trying to sink typ. 900µA to V EE ) to switch off the external line current control transistor. Bandgap reference output VBG This output provides a voltage reference to set the knee line current with the following formula: Iknee =ICC + IP + In order to improve stability, a capacitive load is not allowed on this output. Current limit input CURL This input is applied to the base of an internal NPN transistor which has its collector connected to pin DOC and its emitter to V EE (see Fig.13). The transistor limits the line current just after hook-off or during line transients to a value given by the following formula: I hook-off= I(R1)+ VBE /R9b VBE is the base-emitter voltage of the transistor (typ. 700 mV at 25°C). I(R1) is the current flowing through R1 to charge C1 just after hook-off. Fig.13 Internal current limiting transistor. handbook, halfpage MBA556 DOC VEE IC (collector current) CURL

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 The maximum hook-off current then becomes: Ihook-off=V Z/R1 + VBE × (R9a + R9b + R1)/(R1× R9b) where VZ is the Zener voltage of diode D5 (see Fig.18). Side-tone suppression Suppression of the transmitted signal in the earpiece is obtained by the anti-sidetone network comprising R1//Zline, R2, R3, R9 and Zbal(see Fig.18). Maximum compensation is obtained when the following conditions are fulfilled: c) Zbal=k × Zline The scale factor k is chosen to meet the compatibility with a standard capacitor from the E6 or E12 range for Zbal. In practice Zlinevaries considerably with the line length and line type. Therefore, the value chosen for Zbalshould be for an average line length giving satisfactory sidetone suppression with long and short times. The suppression also depends on the accuracy of the match between Z baland the impedance of the average line. Example With k = 1, R1 = 619Ω , R9 = 20Ω and an average line impedance represented by 270Ω+ (120 nF // 1100Ω ), the calculation results in:

• R2 = 130 kΩ
• R3 = 3650Ω
• R8 = 715 Ω The anti-sidetone network for the TEA1060 family, shown in Fig.15, attenuates the signal received from the line by 32 dB before it enters the receiving amplifier. The attenuation is almost constant over the whole audio-frequency range. Note More information on the balancing of the anti-sidetone bridges can be obtained in our publication “Versatile speech transmission ICs for electronic telephone sets”, order number 9398 341 10011. Fig.14 Example of line current shape in pulse dialling mode (see also Fig.18). handbook, full pagewidth MBA568Iline Ihook-off hook-off speech mode pulse dialling mode time

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 LIMITING VALUES In accordance with the absolute maximum system (IEC 134) THERMAL RESISTANCE Note 1. TEA1065T is mounted on glassy epoxy board 28.5× 19.1× 1.5 mm HANDLING Every pin withstands the ESD test in accordance with MIL-STD-883C class 2, method 3015 (HBM 1500Ω , 100 pF, 3 positive pulses and 3 negative pulses on each pin as a function of pin VEE . SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VLN positive line voltage continuous − 12 V VDOC positive DOC voltage continuous − 12 V VLN repetitive line voltage during switch-on or line interruption − 13.2 V ILN line current (see also Fig.5 and 6) − 150 mA VI input voltage on pins other than LN, DOC, VSI, REFI and CURL VEE − 0.7 V CC + 0.7 V Ptot total power dissipation see Figs 5 and 6 Tstg storage temperature range −40 + 125 °C Tamb operating ambient temperature range −25 +75 °C Tj junction temperature −+ 125 °C SYMBOL PARAMETER TYP. MAX. UNIT R th j-a from junction to ambient in free air; TEA1065 − 50 K/W R th j-a from junction to ambient in free air; TEA1065T(1) − 75 K/W Fig.15 Equivalent circuit of TEA1060 family anti-sidetone bridge. handbook, full pagewidth MBA555 R1 R2 IR VEE SLPE LN Zline R t im Zbal

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 CHARACTERISTICS ILN = 10 to 150 mA; VEE = 0 V; f = 800 Hz; Tamb =2 5°C; R9 = 20Ω ; unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply LN and VCC (pins 1 and 21) VLN voltage drop over circuit I line= 5 mA 3.95 4.25 4.55 V Iline= 15 mA 4.25 4.45 4.65 V Iline= 100 mA 5.4 6.1 6.7 V Iline= 140 mA −− 7.5 V ΔVLN /ΔT variation with temperature I line= 15 mA −3 −1 +1 mV/K VLN voltage drop over circuit I line= 15 mA R VA =R 1-22 = 68 kΩ 3.6 3.9 4.15 V R VA =R 22-24 = 39 kΩ 4.7 5.0 5.3 V ICC supply current PD = LOW; V CC = 2.8 V − 1.14 1.5 mA PD = HIGH; VCC = 2.8 V − 73 105 µA Microphone inputs MIC+ and MIC− (pins 8 and 7)  ZI input impedance 18.5 20.4 24.3 k Ω G v voltage gain I line= 15 mA; R7 = 68 kΩ 37 38 39 dB ΔG vf variation with frequency I line= 15 mA; −0.5 ±0.2 +0.5 dB referred to 800 Hz f = 300 to 3400 Hz ΔG vT variation with temperature I line= 50 mA; −± 0.5 − dB referred to 25°CT amb = −25 to 75°C; without R6 Dual-tone multi-frequency input DTMF(pin 19)  ZI input impedance 16.8 20.7 24.6 k Ω G v voltage gain I line= 15 mA; R7 = 68 kΩ 24.5 25.5 26.5 dB ΔG vf variation with frequency I line= 15 mA −0.5 ±0.2 +0.5 dB referred to 800 Hz f = 300 to 3400 Hz ΔG vT variation with temperature I line= 50 mA; −± 0.5 − dB referred to 25°CT amb = −25 to+75 °C Gain adjustment GAS1 and GAS2(pin 2 and 3) ΔG v gain variation with R7 −8 −+ 8d B connected between pins 2 and 3; transmitting amplifier

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Transmitting amplifier output LN(pin 1) VLN(rms) output voltage (RMS value) I line= 15 mA dtot= 2% 1.9 2.3 − V dtot= 10% − 2.6 − V Vno(rms) noise output voltage (RMS I line= 15 mA; −− 68 − dBmp value) R7 = 68 k Ω ; pin 7 and 8 open-circuit psophometrically weighted (P53 curve); control transistor included (MOS BUK554 type see Fig.18) Receiving amplifier input IR(pin 17) Z I input impedance 17 21 25 k Ω Receiving amplifier outputs QR+ and QR− (pin 5 and 4) ZO output impedance − 4 −Ω G v voltage gain I line= 15 mA; R4 = 100 kΩ single-ended; RT = 300Ω 30 31 32 dB differential; RT = 600Ω 36 37 38 dB ΔG vf variation with frequency f = 300 to 3400 Hz −0.5 ±0.2 +0.5 dB referred to 800 Hz ΔG vT variation with temperature referred to 25°C without R6; Iline= 50 mA; −± 0.2 − dB Tamb = −25 to+75 °C VO(rms) output voltage (RMS value) I line= 15 mA; THD = 2%; sinewave drive; R4 = 100 kΩ single-ended; RT = 150Ω 0.3 0.38 − V differential; RT = 450Ω 0.56 0.72 − V differential; CT = 60 nF; 0.87 1.07 − V (1500Ω series resistor); f = 3400 Hz I line= 30 mA; differential; 1.02 1.22 − V CT = 60 nF; (1500Ω series resistor); f = 3400 Hz V O(rms) noise output voltage (RMS I line= 15 mA; value) R4 = 100 k Ω single-ended; RT = 300Ω− 50 −µ V differential; RT = 600Ω− 100 −µ V SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Gain adjustment GAR(pin 6) ΔG v receiving amplifier, gain −11 −+ 8d B adjustment range Mute input MUTE(pin 20) VIH input voltage HIGH 1.5 − VCC V VIL input voltage LOW −− 0.3 V IMUTE input current − 81 5 µA ΔG v change of microphone amplifier MUTE = HIGH −− 70 − dB gain G v voltage gain from DTMF input MUTE = HIGH; −19 −17 −15 dB to QR+ or QR− R4 = 100 kΩ single-ended; RT = 300Ω Power-down input PD(pin 18) VIH input voltage HIGH 1.5 - V CC V VIL input voltage LOW - - 0.3 V IPD input current - 2.5 5.0 µA Automatic gain control input AGC(pin 23) ΔG v controlling the gain from IR to R6 = 118 kΩ− 5.5 −5.9 −6.3 dB QR +, QR− and the gain from MIC +, MIC− to LN; gain control range with respect to I line= 15 mA Iline highest line current for − 28 − mA maximum gain Iline lowest line current for minimum − 50 − mA gain ΔG v change of gain between − -1.5 − dB Iline= 15 and 35.5 mA Current limiting input CURL(pin 15) VBE base-emitter voltage drop of see Fig.13; − 0.7 − V internal transistor I C =5 0µA=I DOC H FE current gain of internal see Fig.13; 60 120 − transistor I C =5 0µA=I DOC IC(max) maximum collector current of see Fig.13 −− 2m A internal transistor Bandgap reference voltage output VBG(pin 12) VBG reference voltage − 1.22 − V IBG output drive capability note 1 −100 - +50 µA ZO output impedance − 12 −Ω SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 Note 1. No capacitive load on the VBG output. Positive current is defined as conventional current flow into a device. Negative current is defined as conventional current flow out of a device. Voltage sense input VSI(pin 14) IO output current pin VSI connected to V EE −− 2.5 −µ A Reference input REFI(pin 13) IO output current −− 2.0 mA Drive current output DOC(pin 11) IO output current REFI connected to V EE ; 120 300 −µ A VSI not connected; DPI = LOW REFI not connected; 200 900 −µ A VSI connected to V EE ; DPI = HIGH Digital pulse input DPI(pin 10) VIH input voltage HIGH 1.5 − VCC V VIL input voltage LOW −− 0.3 V IDPI input current − 2.5 5 µA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 handbook, full pagewidth MBA558 VCC LN VSI PD MUTE DTMF MIC − MIC + IR 620 Ω TEA1065 100 kΩ R L 600 Ω Iline 100 pF C7 1 nF 5 to 140 mA 100 µF C1 100 µF kΩ C6 100 pF 10 µF QR − QR + GAR GAS1 GAS2 CURL 15 DPI 10 REFI VBG DOC 12 1 Vi Vi VEE REG AGC STAB 20 Ω 232216 9 3.6 kΩ 118 kΩ 4.7 µF SLPE Vo Fig.16 Test circuit for defining voltage gain of MIC+, MIC− and DTMF inputs. Voltage gain is defined as Gv = 20 Log Vo/Vi. For measuring the gain from MIC+ and MIC− the MUTE input should be LOW or open-circuit, for measuring the DTMF input MUTE should be HIGH. Inputs not under test should be open-circuit except VSI that should be connected to V EE .

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 handbook, full pagewidth MBA559 VCC LN VSI PD MUTE DTMF MIC − MIC + IR 620 Ω TEA1065 100 kΩ R L 600 Ω Iline 100 pF C7 1 nF 5 to 140 mA 100 µF C1 100 µF kΩ C6 100 pF 10 µF ZL QR − QR + GAR GAS1 GAS2 CURL 15 DPI 10 REFI VBG DOC 12 1 3Vi Vo VEE REG AGC STAB 20 Ω 232216 9 3.6 kΩ 118 kΩ 4.7 µF SLPE Fig.17 Test circuit for defining voltage gain of the receiving amplifier. Voltage gain is defined as Gv = 20 Log V o/Vi.

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth MBA561 620 Ω MIC − MIC + GAR6 QR − IR QR + SLPE DPI VEE AGC GAS1 DOC LN VCC GAS2 VSI REFI VBG CURL STAB REG from dial and control circuits DTMF MUTE PD 715 Ω 15 kΩ R15 R16 1 MΩ 3.6 kΩ R13 kΩ R14 kΩ C15 6.8 µF R9a 15 Ω R9b 5 Ω 68 kΩ 100 nF Zbal 100 pF 3.65 kΩ 130 kΩ MOSN1 BUK554 BZX79c BV2 BAS11 (4×) telephone line 100 µF 4.7 µF TEA1065 100 kΩ R11 100 pF C7 1 nF Fig.18 Typical application of the TEA1065, with a piezoelectric earpiece and DTMF dialling.

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth MBA560 620 Ω MIC − MIC + GAR6 QR − IR QR + SLPE DPI VEE AGC GAS1 DOC LN VCC GAS2 VSI REFI VBG CURL STAB REG from dial and control circuits DTMF MUTE PD 715 Ω 15 kΩ R15 R16 1 MΩ 3.6 kΩ R13 kΩ R14 kΩ C15 6.8 µF R9a 15 Ω R9b 5 Ω 68 kΩ JFP1 BSJ177 100 nF Zbal 100 pF 3.65 kΩ 130 kΩ MOSN1 BUK554 BZX79c BV2 BAS11 (4×) telephone line 100 µF 4.7 µF TEA1065 100 kΩ R11 100 pF C7 1 nF Fig.19 Typical application of the TEA1065, with a piezoelectric earpiece and pulse dialling. DTMF dialling requires a different protection arrangement.

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 PACKAGE OUTLINES UNIT A max. 1 2 b1 cD E e M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT101-1 92-11-17 95-01-23 A min. A max. b wM Ee1 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 3.9 15.24 17.15 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.15 0.60 0.68 051G02 MO-015AD M H c (e )1 M E A L seating plane w M e D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Z max. (1)(1)(1) DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 UNIT A max. A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 SOT137-1 X w M θ AA 1 A 2 bp D H E Lp Q detail X E Z c L v M A (A )3 A y 0.25 075E05 MS-013AD pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.0550.419 0.394 0.043 0.039 0.035 0.0160.01 0.25 0.01 0.0040.043 0.0160.01 e 0 5 10 mm scale SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 95-01-24 97-05-22

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. R EPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300°C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400°C, contact may be up to 5 seconds. SO R EFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. W AVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow.
• The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150°C within 6 seconds. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. R EPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Semiconductors Product specification Versatile telephone transmission circuit with dialler interface TEA1065 NOTES

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