TCS4525 ETC | Alldatasheet
Document overview
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Technical content
The TCS4525 operates at 3-MHz fixed switching The TCS4525 is a high-frequency, high-current 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface
DESCRIPTION
synchronous step-down dc-dc converter optimized to supply the different sub systems of smart-phones, Tablets, and portable applications powered by one cell Li−Ion or three cell Alkaline/NiCd/NiMH batteries. The device is able to deliver up to 5A, with programmable output voltage from 0.6 V to 1.4V. frequency which allows the use of small low cost inductors and capacitors. During light load conditions, the regulator includes a PFM mode to enhance light-load efficiency. The regulator transitions smoothly between PWM and PFM modes. Synchronous rectification and automatic PWM/PFM transitions improve overall efficiency. The serial interface is compatible with Fast/Standard and High-Speed mode I C specification allowing transfers at up to 3.4 Mbps. This communication interface is used for dynamic voltage scaling with voltage steps down to 6.25 mV, for reprogramming the mode of operation (PFM or Forced PWM) or disable/enabling the output voltage. Typical Application Circuit
FEATURES
/circle6 2.7V to 5.5V Input Voltage Range /circle6 3MHz Constant Switching Frequency /circle6 5A Available Load Current /circle6 I C Control Interface with Dynamic Voltage Scaling Support /circle6 Programmable Output Voltage: 0.6V to 1.4V in 6.25mV Steps /circle6 Small size, 0.33µH or 0.47µH Inductor Solution /circle6 52µA Typical Quiescent Current /circle6 PFM/PWM Operation for Optimum Increased Efficiency /circle6 Excellent Load and Line Transient Response /circle6 Short Circuit and Thermal Protection /circle6 Available in 2.0mm×1.6mm WCSP-20 Package /circle6 RoHS Compliant and 100% Lead(Pb)-Free Halogen-Free
APPLICATIONS
/circle6 Smart Phones /circle6 Tablets /circle6 Low-Voltage DSPs and Processors Core Power Supplies Figure 1. TCS4525 Ver.1.0 May.26,2015 Page 1
Package Type Pin Configurations WCSP-20 Pin Description Name WCSP-20 DESCRIPTION PVIN D2,E1,E2 Power Input V oltage. Connect to input power source. The connection from this pin to C IN should be as short as possible. AVIN D1 Analog Input V oltage. Connect to input power source as close as possible to the input bypass capacitor. SW D3,D4,E3,E4 Switching Node. Connect to the inductor. PGND B2,C1,C2, C3,C4 Power GND. Connect to the (-) terminal of output capacitor and (-) terminal of input capacitor. AGND B4 Analog GND. This is the signal ground refer ence for the IC. SDA B1 SDA. I C interface serial data. There is an internal pull down resistor on this pin; could be left open if not used. SCL A3 SCL. I C interface serial clock. There is an internal pull down resistor on this pin; could be left open if not used. VSEL A1 Output voltage and mode selection. This pin determines which of the two programmable configurations to utilize. This behavior can be overridden through I C register settings. There is an internal pull down resistor on this pin; could be left open if not used. EN A2 Enable. When HIGH, the circuit is enabled. There is an internal pull down resistor on this pin. FB A4 Feedback V oltage Input. Tie this pin to the o utput voltage. PGND/PG B3 Power Good open drain output. If not used has to be connected to ground. 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface TCS4525_WT
Ordering Information
Order Number Package Type Marking Quantity per Reel Operating Temperature Range WCSP-20 xxx Y00 3000 -40°C to +85°C Ver.1.0 May.26,2015 Page 3 TCS4525
Absolute Maximum Ratings (1) /square6 /square6 /square6 /square6 Package Thermal Resistance WCSP-20, θ JA /square6 /square6 /square6 /square6 Recommended Operating Conditions (2) /square6 /square6 Note (1): Stress beyond those listed under “Absolute Maximum Ratings” may damage the device. Note (2): The device is not guaranteed to function outside the recommended operating conditions.
Electrical Characteristics
(The ● denote the Spec. apply over the full operating temperature range, otherwise Spec. are T A =+25°C. V IN =3.6V unless otherwise specified. ) Symbol Parameter Conditions Min. Typ. Max. Unit V IN Input V oltage Range -40°C ≤T A ≤+85°C ● 2.7 5.5 V UVLO Input Undervoltage Lockout Rising 2.2 V Output V oltage Load Regulation I O = 0 to 5A, V OUT =1.15V , PWM Mode 0.1 %/A OUT Output V oltage Line Regulation I O = 0A, V IN =2.7V to 5.5V , V OUT =1.15V , PWM Mode 0.1 %/V V IH High-Level Input V oltage 1.2 V V IL Low-Level Input V oltage EN,VSEL,SCL,SDA 0.4 V I O =0mA, PFM mode, no switching 52 µA I Q Quiescent Current I O =0mA, PWM mode, switching 14 mA I SHDN OFF Mode Current EN,VSEL,SLEEP_mode bit low ● 0.3 5 µA I SLEEP SLEEP Mode Current EN high, DC-DC off (or EN low, VSEL low, SLEEP_mode bit high) 17 µA I PEAK Peak Inductor Current 8 A f OSC Oscillator Frequency 2.65 3 3.35 MHz EN=0V , SW=0V 5 µA I LSW SW Leakage Current EN=0V , SW=3.6V 5 µA R PFET R DS(ON) of P-Channel FET I SW =500mA, VIN=5V 31 m Ω R NFET R DS(ON) of N-Channel FET I SW =500mA, VIN=5V 17 m Ω T SD Thermal Shutdown 150 °C T SD -Hys Thermal Shutdown Hysteresis 20 °C 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 4 TCS4525
I C Timing Specifications Symbol Parameter Conditions Min. Typ. Max. Unit Standard Mode 100 kHz Fast Mode 400 kHz High-Speed Mode, C B ≦100pF 3.4 MHz f SCL SCL Clock Frequency High-Speed Mode, C B ≦400pF 1.7 MHz Standard Mode 4.7 µs t BUF Bus-Free Time between STOP and START Conditions Fast Mode 1.3 µs Standard Mode 4 µs Fast Mode 100 ns t HD;STA START or Repeated-START Hold Time High-Speed Mode 160 ns Standard Mode 4.7 µs Fast Mode 1.3 ns High-Speed Mode, C B ≦100pF 160 ns t LOW SCL LOW Period High-Speed Mode, C B ≦400pF 320 ns Standard Mode 4 µs Fast Mode 600 ns High-Speed Mode, C B ≦100pF 60 ns t HIGH SCL HIGH Period High-Speed Mode, C B ≦400pF 120 ns Standard Mode 4.7 µs Fast Mode 600 ns t SU;STA Repeat-START Setup Time High-Speed Mode 160 ns Standard Mode 250 ns Fast Mode 100 ns t SU;DAT Data Setup Time High-Speed Mode 10 ns Standard Mode 0 3.45 µs Fast Mode 0 900 ns High-Speed Mode, C B ≦100pF 0 70 ns t HD;DAT Data Hold Time High-Speed Mode, C B ≦400pF 0 150 ns Standard Mode 20+0.1C B 1000 ns Fast Mode 20+0.1C B 300 ns High-Speed Mode, C B ≦100pF 10 80 ns t RCL SCL Rise Time High-Speed Mode, C B ≦400pF 20 160 ns Standard Mode 20+0.1C B 300 ns Fast Mode 20+0.1C B 300 ns High-Speed Mode, C B ≦100pF 10 40 ns t FCL SCL Fall Time High-Speed Mode, C B ≦400pF 20 80 ns Standard Mode 20+0.1C B 1000 ns Fast Mode 20+0.1C B 300 ns High-Speed Mode, C B ≦100pF 10 80 ns t RCL1 Rise Time of SCL After a Repeated START Condition and After ACK Bit High-Speed Mode, C B ≦400pF 20 160 ns Standard Mode 20+0.1C B 1000 ns Fast Mode 20+0.1C B 300 ns High-Speed Mode, C B ≦100pF 10 80 ns t RDA SDA Rise Time High-Speed Mode, C B ≦400pF 20 160 ns 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 5 TCS4525
Typical Operating Characteristics (A VIN=PVIN=3.6V , L=0.47µH, C OUT =2×22µF) 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 7 TCS4525
Typical Operating Characteristics (continued) (A VIN=PVIN=3.6V , L=0.47µH, C OUT =2×22µF) 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 8 TCS4525
Typical Operating Characteristics (continued) (A VIN=PVIN=3.6V , L=0.47µH, C OUT =2×22µF) 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 9 TCS4525
Typical Operating Characteristics (continued) (A VIN=PVIN=3.6V , L=0.47µH, C OUT =2×22µF) 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 10 TCS4525
Typical Operating Characteristics (continued) (A VIN=PVIN=3.6V , L=0.47µH, C OUT =2×22µF) 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 11 TCS4525
small ceramic input and output capacitors. and register description section. output of error amplifier and the sawtooth ramp. Forced PWM operation provides low ripple noise. Figure 6. Operation in PFM mode and transfer to mode with smooth transition. will set the output voltage. synchronous switches under undervoltage state. 150°C typical, the device goes into thermal shutdown. TSD. To restart, an EN pin toggle is required. temperature falls below 130°C typical again. default the discharge path is disabled.
The TCS4525 device supports 7-bit addressing. The 7 The EN pin controls TCS4525 start up. EN pin Low The TCS4525 device works as a slave and supports free way to change TCS4525 configuration: operating Enabling to High transition starts the power up sequencer. If EN is made low, the DC-DC converter is turned off and device enters: /circle6 In Sleep Mode if Sleep_Mode I C bit is high or VSEL is high. /circle6 In Off Mode if Sleep_Mode I C bit and VSEL are low. When EN pin is set to high level, the DC-DC converter can be enabled/disabled by writing the ENVSEL0 or ENVSEL1 bit of the PROGVSEL0 and PROGVSEL1 registers: If ENVSELx bit is high, DC-DC is activated. If ENVSELx bit is low, DC-DC converter is turned off and device enters in Sleep Mode. A built in pull down resistor disables the device when this pin is left unconnected or not driven. Dynamic Voltage Scaling (DVS) This converter supports dynamic voltage scaling (DVS) allowing the output voltage to be reprogrammed via I C commands and provides the different voltages required by the processor. The change between set points is managed in a smooth fashion without disturbing the operation of the processor. When programming a higher voltage, output raises in equidistant steps, which are 6.25mV/0.166us, such that the dV/dt is controlled. When programming a lower voltage, output will decrease in equidistant steps per defined time period such that the dV/dt is controlled (default 6.25mV/2.666us) by writing DVS[1..0] bits in TIME register. DVS sequence is automatically initiated by changing output voltage settings. There are two ways to change these settings: /circle6 Directly change the active setting register value (V outVSEL0[6..0] of PROGVSEL0 register or V outVSEL1[6..0] of the PROGVSEL1 register) via I C command. /circle6 Change the VSEL internal signal level by toggling VSEL pin. The second method eliminates the I C latency and therefore faster. VSEL Pin By changing VSEL pin levels, the user has a latency mode (Auto or PWM forced), the output voltage as well as enable. VSEL pin action can be masked by writing 0 to the VSELGT bit in the COMMAND register. In that case I C bit corresponding to VSEL high will be taken into account. Power Good Pin (Optional) To indicate the output voltage level is established, a power good signal is available. The power good pin is pulled down when the DC-DC converter is off. Once the output voltage reaches 93% of the expected output level, the power good logic signal becomes high and the open drain output becomes high impedance. During operation when the output drops below 90% of the programmed level, the power good logic signal goes low and the open drain signal transitions to a low impedance state, which indicates a power failure. When the voltage rises again to above 93% the power good signal goes high again. During a positive DVS sequence, when target voltage is higher than initial voltage, the Power Good logic signal will be set low during output voltage ramping and transition to high once the output voltage reaches 93% of the target voltage. When the target voltage is lower than the initial voltage, Power Good pin will remain at high level during transition. Power Good signal during normal operation can be disabled by clearing the PGDCDC bit in PGOOD register. Power Good operation during DVS can be controlled by setting / clearing the bit PGDVS in PGOOD register. In order to generate a Reset signal, a delay can be programmed between the output voltage gets 93% of its final value and Power Good pin is released to high level. The delay is set through the TOR[1..0] bits in the TIME register. The default delay is 0 ms. I C interface I C is a 2-wire serial interface developed by Philips Semiconductor (see I C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I C compatible devices connect to the I C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. the following data transfer modes, as defined in the I C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. The data transfer protocol for standard and fast modes is exactly the same. Therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is identical with the F/S-mode except the bus speed, and it is referred to as HS-mode. MSBs are 0011100. 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 13 TCS4525
devices should recognize a start condition. acknowledge can continue as long as necessary. Figure 7. This releases the bus and stops the compatible devices must recognize the stop condition. start condition followed by a matching address. pulled high by the pull-up devices. stop condition ends the HS-mode.
Default values of TCS4525 are shown below: C address selects the TCS4525. TCS4525 performs an update. After the receipt of each byte, the TCS4525 The TCS4525 requires a start condition, a valid I Figure10.Bus Protocol Read and Write transactions C address, a register address byte, and a data byte for a single device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I update on the falling edge of the LSB byte. When EN pin is tied to ground, the registers can be updated via the I C interface. Figure11. "Write" Data Transfer Format in F/S-Mode Figure12. "Read" Data Transfer Format in F/S-Mode Configurations /circle6 I C Address: 0011100 /circle6 VOUT_VSEL1: 1.15V /circle6 VOUT_VSEL0: 1.025V /circle6 MODE_VSEL1: Forced PWM /circle6 MODE_VSEL0: PWM/PFM Auto Mode /circle6 IPEAK: 8A TCS4525 TCS4525 TCS4525 TCS4525 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 15 TCS4525 TCS4525 TCS4525 TCS4525 TCS4525
5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 16 TCS4525
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5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 18 TCS4525
5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 19 TCS4525
operation of the TCS4525. pulsed current drawn by the TCS4525. A low ESR To avoid the TCS4525 from exceeding the maximum The TCS4525 typically uses a 0.33µH or 0.47µH Applications Information Inductor Selection inductor. The output inductor is selected to limit the ripple current to some predetermined value, typically 20%~40% of the full load current at the maximum input voltage. Large value inductors lower ripple currents. Higher V IN or V OUT also increases the ripple current as shown in equation. The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. The DC resistance of the inductor directly influences the efficiency of the converter. Therefore for better efficiency, choose a low DC-resistance inductor. CIN and COUT Selection In continuous mode, the source current of the P-Channel MOSFET is a square wave of duty cycle V OUT IN . The primary function of the input capacitor is to provide a low impedance loop for the edges of input capacitor sized for the maximum RMS current must be used. The size required will vary depending on the load, output voltage and input voltage source impedance characteristics. A typically C IN value is around 10µF. If the wire of supply is too long, larger input capacitor should be used, 22µF is preferred. The input capacitor RMS current varies with the input voltage and the output voltage. The equation for the maximum RMS current in the input capacitor is: The output capacitor C OUT has a strong effect on loop stability. The selection of C OUT is driven by the required effective series resistance (ESR). ESR is a direct function of the volume of the capacitor; that is, physically larger capacitors have lower ESR. Once the ESR requirement for C OUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆V OUT in PWM mode is determined by: When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Thermal Considerations junction temperature, the user will need to do a thermal analysis. The goal of the thermal analysis is to determine whether the operating conditions exceed the maximum junction temperature of the part. The temperature rise is given by: T R =(P D )(θ JA Where P D LOAD × R DS(ON) is the power dissipated by the regulator ; θ JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, T J , is given by: T J A R Where T A is the ambient temperature. TJ should be below the maximum junction temperature of 150°C. PC Board Layout Checklist For all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI problems. When laying out the printed circuit board, the following guidelines should be used to ensure proper The input capacitor C IN should connect to V IN as closely as possible. This capacitor provides the AC current to the internal power MOSFETs. The power traces, consisting of the GND trace, the SW trace and the V IN trace should be kept short, direct and wide. For good thermal coupling, PCB vias are required from the Pad for the thermal paddle to the ground plane. INV OUTV 1OUTV (f)(L) L∆I INV OUTV 1OUTV (f)(L) L∆I OUT8fC 1ESRL∆IOUT∆V 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 20 TCS4525
MIN. MAX. MIN. MAX. A - 0.60 - 0.024 A1 0.15 0.23 0.006 0.009 D 1.60 1.66 0.063 0.065 D1 0.40 REF 0.016 REF E 2.00 2.06 0.079 0.081 E1 0.40 REF 0.016 REF 5A, 3MHz Synchronous Step-Down DC-DC with I C Compatible Interface Ver.1.0 May.26,2015 Page 21 TCS4525