TCM9001MD

TCM9001MD TOSHIBA | Alldatasheet

Document overview

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Technical content

Features

• Input Clock : 9.0 to 26MHz (with PLL, selectable)
• Frame rate : 30fps (max.) @ VGA output
• Data formats : YUV422/RAW
• Output format : Parallel output
• Power supply : Analog 2.8V -/+ 0.2V Digital 1.8V -/+ 0.1V I/O 1.8V -/+0.1V or 2.8V -/+0.2V
• Operating temperature : -20 to +60 degree C
• Storage temperature : -30 to +85 degree C Sensor
• Optical format : 1/10 inch
• Effective pixel numbers : 648(H) x 492(V)
• Pixel pitch : 2.2µm(H) x 2.2µm(V) (square pixel)
• Image area size : 1425.6 μm(H) x 1082.4 μm(V)
• Color filter : Primary color filter, Bayer arrangement
• Image sizer and window of interest (QVGA, QQVGA)
• Picture flip (Horizontal flip and Vertical flip)
• Picture effects (monochrome, negative, sepia, sketch, emboss)
• Fixed output format (VGA, QVGA, QQVGA)
• Auto luminance control (=Auto exposure)
• Auto white balance
• Blemish correction
• Auto flicker detection and correction
• Gamma correction
• Lens shading correction
• Power down mode for low power consumption TOSHIBA C 2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TCM9 0 01 MD V0.21 Dec 12, 2008

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 2/40 Key Specifications Item Contents Optical format 1/10 inch Effective pixel numbers 648(H) x 492(V) Image area size 1425.6 μm(H) x 1082.4 μm(V) Pixel pitch 2.2 μm(H) x 2.2 μm(V) Aspect ratio 4(H) : 3(V) Input clock frequency range 9 to 26 MHz (with PLL, selectable) Signal output order Progressive scanning Color filter RGB primary color filter Bayer arrangement (G checked, R/B in line sequence) Output data YUV422 or RAW parallel output Frame rate 30fps (max.) @ VGA Package Camera Module Table 1 Key specifications

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 3/40 Table of Contents

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 4/40

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 5/40 1. List of Abbreviation Abbreviation Description ISP Image Signal Processor CDS Correlated Double Sampling ADC Analog to Digital Converter PLL Phase Locked Loop VCO Variable Controlled Oscillator PPRO Pre PROcessor MPRO Main PROcessor APRO After signal PROcessor ALC Auto Luminance Control ( ≒ AE) AE Auto Exposure AF Auto Focus UXGA Ultra XGA (1600 x 1200) SXGA Super XGA (1280 x 1024) Quad VGA Quad VGA (1280 x 960) XGA eXtended Graphics Array (1024 x 768) SVGA Super VGA (800 x 600) VGA Video Graph Array (640 x 480) CIF Common Intermediate Format (352 x 288) QVGA Quarter VGA (320 x 240) QCIF Quarter CIF (176 x 144) QQVGA Quarter Quarter VGA (160 x 120) subQCIF subQCIF (128 x96) Image area Aperture area of the sensor Effective pixel area It is the pixel area that is the signal output is available. Table 2 Abbreviation

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 6/40 2. Block Diagram 2.1. Block Diagram PPRO MPRO Linear Color Separation Gamma Correction Linear Matrix Color Correction Auto White Balance Auto Luminance Controol (Auto Exposure) Flicker Correction Statistical Data for ALC, AWB Dizital Zoom RGB Matrix UV LPF Output Format selector Parallel output VSYNC HSYNC DCLK APRO CDS ADC Monitoring Image Area (648x492) Sensor Core Test pattern generator DATA0 DATA7 Signal Generator YUV Matrix Timing Generator for Image Area PLL Register Table I2C I/F SCL SDA GND RESET PWRDWN AVDD DVDD Timing Generator for ISP Regulator IOVDD Blemish Correction Noise Reduction Lens Shading Correction High luminance Correction Edge Enhancement Carrier Boost Correction Some functional blocks, circuits or constants may be omitted or simplified in the block diagram for explanatory purposes. Figure 1 Block diagram

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 7/40 2.2. I/O circuits Pin No. / Pin name I/O Interface circuit B5: EXTCLK I GND C6: PWRDWN I GND D3: RESET I IOVDD GND 140kΩ IOVDD D6: SCL I GND C5: SDA I/O GND GND A3: DCLK D1: HSYNC D2: VSYNC B1: DATA1 B2: DATA2 B3: DATA0 B4: DATA3 C1: DATA4 C2: DATA5 C3: DATA6 D4: DATA7 O IOVDD GND The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. Table 3 I/O circuits

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 8/40 3. Pin Layout Pin No. Pin name I/O Description A2 IOVDD - Power supply for I/O circuits (1.7 to 3.0V) A3 DCLK O Data clock output A4 GND - System ground A5 VDD15 - Capacitor connection for internal regulator B1 DATA1 O Image data output 1 B2 DATA2 O Image data output 2 B3 DATA0 O Image data output 0 B4 DATA3 O Image data output 3 B5 EXTCLK I External clock input B6 DVDD - Power supply for digital circuits (1.8V -/+ 0.1V) C1 DATA4 O Image data output 4 C2 DATA5 O Image data output 5 C3 DATA6 O Image data output 6 C4 GND - System ground C5 SDA I/O Serial data input/output for I 2 C C6 PWRDWN I System power down signal input D1 HSYNC O Horizontal synchronization signal output D2 VSYNC O Vertical synchronization signal output D3 RESET I System reset signal input (Reset = L) D4 DATA7 O Image data output 7 D6 SCL I Serial data input/output for I 2 C E2 GND - System ground E3 GND - System ground E4 VDD15 - Capacitor connection for internal regulator E5 AVDD - Power supply for analog circuits (2.8V -/+ 0.2V) Install the product correctly. Otherwise, it may result in break down, damage and/or degradation to the product or equipment. Table 4 Pin description Orientation <Top view> A2A3A4A5 B2B3B4B5 B1B6 C2C3C4C5 C1C6 D2D3D4 D1D6 E2E3E4E5

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 10/40 4.2. Slave address TCM9001MD has one address table. Slave address is 7Ch. W : 7Ch R : 7Dh Bit Data A6 0 A5 1 A4 1 A3 1 A2 1 A1 1 A0 0 R/W 1/0 Table 5 Slave address

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 11/40 5. Power supply Analog and digital circuits). And IOVDD also require a power supply, 1.8V or 2.8V, for I/F. Pin name I/O Description AVDD - Power supply for analog circuits (2.8V -/+ 0.2V) IOVDD - Power supply for I/O circuits (1.8V -/+ 0.1V or 2.8V -/+ 0.2V) DVDD - Power supply for regulator (1.8V -/+ 0.1V) Table 6 Power supply pins

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 12/40 6. Input clock frequency The input clock frequency between 9MHz and 26MHz is acceptable to TCM9001MD. 6.1. Clock setting The clock system diagram is shown below. CKREF Divider 0h: 1/5 Fh: 1/20 EXTCLK VCO Divider 0h: 1/8 1h: 1/4 2h: 1/2 3h: 1/1 VCO_DIV[1:0] CKVAR_DIV[8:0] REGCK CKREF_DIV[3:0] CLK Selector 0h: VCO 1h: Reserved 2h: EXTCLK 3h: Reserved CLK_SEL[1:0] DCLK Internal circuits 1Fh(D0), 1Eh(D7-D0) 1Bh(D3-D0) 20h(D7-D6) Phase Comparator VCO 20h(D5-D4) PLL Divider 010h: 1/16 1FFh: 1/511 1Dh(D4) EXTCLK_THROUGH Divider EXTCLK Selector 0h: VCO 1h: EXTCLK Divider x1/2 500 to 720MHz Some functional blocks, circuits or constants may be omitted or simplified in the block diagram for explanatory purposes. Figure 4 Clock diagram 7. Frame rate TCM9001MD can operate 30 fps or less in VGA output mode. 8. Data Formats The following data formats are available. Data format is selectable by I 2C commands. The data output supports parallel. Available parallel output: YUV422 and Raw

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 13/40 9. Functions 9.1. Window of interest The window of interest function enables the user to select a part of the image from the whole image area with specified location (2 pixel step) and specified size (8 pixel step). The available maximum size is 648 x 492 in RAW output or 640 x 480 (VGA) in YUV output mode and the available minimum size is 128 x 96 (subQCIF). 9.2. Image sizer The image sizer function enables the monitoring (sub sampling) mode on given image with scale factors of 1, 1/2, and 1/4. The available minimum image output is 128 x 96 (subQCIF). Monitoring (sub sampling) mode has a limited output format. This function can be used like a zoom function. Digital x2 zoom is available under QVGA or less monitoring operation and digital x2 and x4 zoom is available under QQVGA or less monitoring operation. 9.3. Picture flip Horizontal and vertical flip modes are controlled by I 2C commands. Each flip mode is selectable separately as below. No. Mode

0 Original

1 Horizontal flip

2 Vertical flip

3 Vertical and Horizontal flip (180 deg rotation)

9.4. Picture effects The picture effect function supports some kind of pictures with special effects as below. It is controlled by I 2 C bus commands. Normal / Monochrome / Negative / Sepia / Emboss / Sketch 9.5. Dynamic range adjustment Dynamic range adjustment function supports programmable black level adjustment, high luminance level signal compression and others. 9.6. Gamma correction Gamma correction function supports fixed gamma tables only. Fixed gamma table coefficients are 0.45, 0.55, and 0.65.

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 14/40 9.7. Auto luminance control Auto luminance control (ALC) function is also called Auto Exposure (AE) control. It enables the system to adjust the electrical shutter speed, digital gain and analog gain to adapt to the ambient light automatically to achieve proper brightness of the image. The luminance convergence level, sampling location, EV shift and others can be controlled via I 2 C bus. It also has manual mode. 9.8. Analog gain control Analog gain control is used to adjust the gain of the amplifier of pixel cell. It is often used in dark environment to increase brightness of the image automatically. It also has manual mode. 9.9. White balance Two modes are available for white balance control under different lighting conditions; manual white balance control and auto white balance control. In manual white balance control mode, it can specify the gain for each color to achieve special effects. In auto white balance control mode, the system supports the gain setting for the white balance based on limit conditions (such as sampling area and range of gain) specified by the user via I 2 C bus. 9.10. Auto flicker detection and correction Auto flicker detection and correction function can correct a fluorescent flicker for both AC 50Hz and 60Hz automatically. However, it is impossible to detect a flicker when shutter speed is faster than 1/100s (Very brighter condition). 9.11. Statistical data output ALC statistical data are calculated in ISP every frame continuously. The region for calculating is selectable from all area, center only and center weighted mode. The statistical data can be read via I 2 C bus in read mode. AWB statistical data is also calculated in ISP every frame continuously. 9.12. Color separation Color separation function separates color from sensor bayer arrangement. 9.13. Color matrix Color matrix can adjust each color via I 2 C bus. It can control 6 factors. 9.14. Edge enhancement Edge enhancement can emphasize edges in an image. It can be set V edge and H edge independently. It also can adjust an enhancement level via I 2 C bus.

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 15/40 9.15. Brightness and contrast Brightness and Contrast can be adjusted via I 2 C bus. 9.16. Lens shading correction The lens shading function can change the pixel gain of off center area to compensate the loss caused by lens shading effect. The correction gain and starting location are programmable across the shading area via I2 C bus. It can be set V and H separately. 9.17. Blemish correction Blemish correction supports to correct fixed white and black pixels automatically. 9.18. Test charts For connection test, it has built-in color bar charts, color/grayscale ramp charts and others. 9.19. Test pattern output For connection test of input/output terminals, it is available to output 1/0 value via I 2 C bus.

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 16/40 10. Timing Chart 10.1. Power management modes OPERATING MODE POWER OFF MODE 1. IOVDD : On 2. DVDD : On 3. AVDD : On 4. PWRDWN : L => H 1. AVDD : Off 2. DVDD : Off 3. PWRDWN : H => L 4. IOVDD : Off STANDBY MODE 1. STANDBY : 0h => 1h 2. SLEEP : 0h => 1h 3. I2C Command Initial Setting 1. SLEEP : 1h => 0h 2. STANDBY : 1h => 0h POWER DOWN MODE 1. EXTCLK : On 2. PWRDWN : H => L 3. RESET : L => H 1. RESET : H => L 2. PWRDWN : L => H 3. EXTCLK : Off Figure 5 Power management states Mode All circuits are active. Comment Internal digital circuits and clock control circuits are Disable for low power consumption while STANDBY and SLEEP registers are set to “0”. All power supplies are turned off . OPERATING MDOE POWER OFF MDOE STANDBY MODE All power are set. Clock is not provided.POWER DOWN MODE Table 8 Power management mode

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 18/40 10.3. Output signal waveform It can be output DCLK during blanking pulse low. It means DCLK is output continuously. Figure 7 Example of output waveform (VGA output)

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 19/40 11. Register descriptions Slave address = 7Ch/7Dh Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex)

00 D7-0 VER_NUM [7:0] R 48

01 D7-0 VER_NUM[15:8]

Chip version identification R 10 02 D7-0 ALCDATA[7:0] Shows internal ALC accumulated data. (Lower bits) R 00 D7 ALC_AC5060 Shows internal detection result on Flicker detection. 0h: 50Hz detected 1h: 60Hz detected D6-4 ALC_LES_MODE[2:0] Shows current LES mode. D3-2 Reserved Reserved D1-0 ALCDATA[9:8] Shows internal ALC accumulated data. (Upper bits) R 00 04 D7-0 ALC_AGOUT[7:0] Shows the analog gain status of ALC. (Lower bits) R 00 D7-4 Reserved Reserved 05 D3-0 ALC_AGOUT[11:8] Shows the analog gain status of ALC. (Upper bits) R 00 06 D7-0 ALC_DGOUT[7:0] Shows the digital gain status of ALC. R 00 07 D7-0 ALC_ESOUT[7:0] Shows the accumulated number of electrical shutter lines. (Lower bits) R 00 D7-6 Reserved Reserved 08 D5-0 ALC_ESOUT[13:8] Shows the accumulated number of electrical shutter lines. (Upper bits) R 00

09 D7-0 AWB_UOUT[7:0] R 00

0A D7-0 AWB_UOUT[15:8] R 00 0B D7-0 AWB_UOUT[23:16] Shows the accumulated value of U signal referred as AWB. (Lower bits) R 00 D7-6 Reserved Reserved 0C D5-0 AWB_UOUT[29:24] Shows the accumulated value of U signal referred as AWB. (Upper bits) R 00 0D D7-0 AWB_VOUT[7:0] R 00 0E D7-0 AWB_VOUT[15:8] R 00 0F D7-0 AWB_VOUT[23:16] Shows the accumulated value of V signal referred as AWB. (Lower bits) R 00 D7-6 Reserved Reserved 10 D5-0 AWB_VOUT[29:24] Shows the accumulated value of V signal referred as AWB. (Upper bits) R 00

11 D7-0 AWB_PIXOUT[7:0] R 00

12 D7-0 AWB_PIXOUT[15:8]

Shows the number of pixels referred as AWB. (Lower bits) R 00 D7-3 Reserved Reserved 13 D2-0 AWB_PIXOUT[18:16] Shows the number of pixels referred as AWB. (Upper bits) R 00 14 D7-0 AWB_RGOUT[7:0] Shows the R gain for white balance. R 00 15 D7-0 AWB_GGOUT[7:0] Shows the G gain for white balance. R 00 16 D7-0 AWB_BGOUT[7:0] Shows the B gain for white balance. R 00

17 D7-0 Reserved Reserved R 00

D7 STANDBY Software standby mode SW 0h: Standby 1h: Normal D6-0 Reserved Reserved R/W 9C

19 D7-0 Reserved Reserved R/W 04

D7 VCO_STP_X VCOPLL core SW 0h: Stop 1h: Active D6-0 Reserved Reserved R/W 90 D7-4 Reserved Reserved 1B D3-0 CKREF_DIV[3:0] PLL divider control for reference clock (EXTCLK) 0h: 1/5 Fh: 1/20 R/W 00 1C D7-0 Reserved Reserved R/W 00

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 20/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) D7-5 Reserved Reserved D4 EXTCLK_THROUGH EXTCLK through mode to MRCK and SPCK 0h: OFF 1h: ON (Through) D3-0 Reserved Reserved R/W 00 1E D7-0 CKVAR_DIV[7:0] PLL divider control (Lower bits) 000h-00Fh: Not available 010h: 1/16 1FFh: 1/511 R/W 64 D7-1 Reserved Reserved 1F D0 CKVAR_DIV[8] PLL divider control (MSB). See Sub-address 1Eh. R/W 01 D7-6 VCO_DIV[1:0] VCO clock divider control 0h: 1/8 1h: 1/4 2h: 1/2 3h: 1 D5-4 CLK_SEL[1:0] Clock SW to MRCK divider 0h: VCO (Normal) 1h: Reserved 2h: EXTCLK (for test) 3h: Reserved D3-0 Reserved Reserved R/W C0

21 D7-0 Reserved Reserved R/W 0B

D7 VFLIP Vertical flip mode SW 0h: OFF 1h: ON D6 HFLIP Horizontal flip mode SW 0h: OFF 1h: ON D5-3 Reserved Reserved D2-0 HV_INTERMIT[2:0] Horizontal and vertical resize setting 0h-2h: x1/4 3h-6h: x1/2 7h: x1 R/W 07

23 D7-0 H_COUNT[7:0] Total number of horizontal pix els per line, including effective

and blanking pixels (Lower bits) [Total H-pix / line] = H_COUNT[8:0] x 8 000h-095h: Not available 096h: 1200 pixels (Default) 1FFh: 4088 pixels R/W 96 D7-1 Reserved Reserved 24 D0 H_COUNT[8] Total number of horizontal pix els per line, including effective and blanking pixels (MSB) See Sub-address 23h. R/W 00

25 D7-0 V_COUNT[7:0] Total number of vertical lines per frame, including effective

and blanking lines (Lower bits) [Total V-line / frame] = V_COUNT[10:0] x 8 000h-041h: Not available 042h: 528 lines (Default) 7FFh: 16376 lines R/W 42 D7-3 Reserved Reserved 26 D2-0 V_COUNT[10:8] Total number of vertical lines per frame, including effective and blanking lines (Upper bits) See Sub-address 25h. R/W 00

27 D7-0 Reserved Reserved R/W 00

28 D7-0 Reserved Reserved R/W 00

29 D7-0 Reserved Reserved R/W 83

2A D7-0 Reserved Reserved R/W 84 2B D7-0 Reserved Reserved R/W AE 2C D7-0 Reserved Reserved R/W 21 2D D7-0 Reserved Reserved R/W 00 2E D7-0 Reserved Reserved R/W 04 2F D7-0 Reserved Reserved R/W 7D

30 D7-0 Reserved Reserved R/W 19

31 D7-0 Reserved Reserved R/W 88

32 D7-0 Reserved Reserved R/W 88

33 D7-0 Reserved Reserved R/W 09

34 D7-0 Reserved Reserved R/W 6C

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 21/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex)

35 D7-0 Reserved Reserved R/W 00

36 D7-0 Reserved Reserved R/W 0C

37 D7-0 Reserved Reserved R/W 22

38 D7-0 Reserved Reserved R/W 0B

39 D7-0 Reserved Reserved R/W AA

3A D7-0 Reserved Reserved R/W 0A 3B D7-0 Reserved Reserved R/W 84 3C D7-0 Reserved Reserved R/W 03 3D D7-0 Reserved Reserved R/W 10 3E D7-0 Reserved Reserved R/W 4C 3F D7-0 Reserved Reserved R/W 1D

40 D7-0 Reserved Reserved R/W 14

41 D7-0 Reserved Reserved R/W 05

42 D7-0 Reserved Reserved R/W 12

43 D7-0 Reserved Reserved R/W B0

44 D7-0 Reserved Reserved R/W 3F

45 D7-0 Reserved Reserved R/W 7F

46 D7-0 Reserved Reserved R/W 44

47 D7-0 Reserved Reserved R/W 44

48 D7-0 Reserved Reserved R/W 00

49 D7-0 Reserved Reserved R/W E8

4A D7-0 Reserved Reserved R/W 00 4B D7-0 Reserved Reserved R/W 9F 4C D7-0 Reserved Reserved R/W C0 4D D7-0 Reserved Reserved R/W 24 4E D7-0 Reserved Reserved R/W 52 4F D7-0 Reserved Reserved R/W 71

50 D7-0 Reserved Reserved R/W 0E

51 D7-0 Reserved Reserved R/W 00

52 D7-0 Reserved Reserved R/W 00

D7-3 TP_MODE[4:0] Test pattern selection 00h : Normal 01h-06h : Normal picture + Cross line 07h : Reserved 08h : Frame 09h-10h : Color-bar 11h-17h : Gray scale (with color) 18h : Color-bar (Horizontal ramp) 19h-1Fh : Horizontal and vertical ramp D2-1 Reserved Reserved D0 TPG_LINE_SW Test pattern of Center cross line 0h: OFF 1h: ON R/W 0E

54 D7-0 Reserved Reserved R/W 08

55 D7-0 Reserved Reserved R/W 14

56 D7-0 Reserved Reserved R/W 84

57 D7-0 Reserved Reserved R/W 30

58 D7-0 Reserved Reserved R/W 80

59 D7-0 Reserved Reserved R/W 80

5A D7-0 Reserved Reserved R/W 00 5B D7-0 Reserved Reserved R/W 06 D7-4 LINE_RLV[3:0] Red level setting for Center cross test pattern 0h: Min. Ch-Fh: Max. D3-0 Reserved Reserved R/W 50

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 22/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) D7-4 LINE_GLV[3:0] Green level setting for Center cross test pattern 0h: Min. Ch-Fh: Max. D3-0 Reserved Reserved R/W A5 D7-4 LINE_BLV[3:0] Blue level setting for Center cross test pattern 0h: Min. Ch-Fh: Max. D3-0 Reserved Reserved R/W 5A 5F D7-0 Reserved Reserved R/W B0

60 D7-0 Reserved Reserved R/W 00

61 D7-0 Reserved Reserved R/W 1B

62 D7-0 Reserved Reserved R/W 4E

63 D7-0 Reserved Reserved R/W 04

D7 LDNR_SW Random noise reduction SW 0h: OFF 1h: ON D6-0 Reserved Reserved R/W 90

65 D7-0 AGMIN_LDNR_WIDTH[7:0] Slice level setting for Noise reduction while Analog gain

condition is min. (=under high light) 00h: Min. FFh: Max. R/W 30

66 D7-0 AGMAX_LDNR_WIDTH[7:0] Slice level setting for Noise reduction while Analog gain

condition is max. (=under low light) 00h: Min. FFh: Max. R/W 30

67 D7-0 AGMIN_LDNR_MP[7:0] Gain setting for Noise reduction while Analog gain condition

is min. (=under high light) 00h: Min. FFh: Max. R/W 66

68 D7-0 AGMAX_LDNR_MP[7:0] Gain setting for Noise reduction while Analog gain condition

is max. (=under low light) 00h: Min. FFh: Max. R/W 66

69 D7-0 Reserved Reserved R/W C0

6A D7-0 Reserved Reserved R/W 30 6B D7-0 Reserved Reserved R/W 30 6C D7-0 Reserved Reserved R/W 10 6D D7-0 Reserved Reserved R/W 30 6E D7-0 Reserved Reserved R/W AB 6F D7-0 Reserved Reserved R/W 30

70 D7-0 AGMIN_BLACK_ADJ[7:0] Fine setting for Black level while Analog gain condition is

min. 00h: Min. FFh: Max. R/W 80

71 D7-0 AGMAX_BLACK_ADJ[7:0] Fine setting for Black level while Analog gain condition is

max. 00h: Min. FFh: Max. R/W 80

72 D7-0 IDR_SET[7:0] Saturation level setting

00h: 100% 55h: 130% FFh: 200% R/W 55

73 D7-0 PWB_RG[7:0] Preset WB setting for R pixels

00h: x1 80h: x2 FFh: x3 R/W 00

74 D7-0 PWB_GRG[7:0] Preset WB setting for Gr pixels

00h: x1 80h: x2 FFh: x3 R/W 04

75 D7-0 PWB_GBG[7:0] Preset WB setting for Gb pixels

00h: x1 80h: x2 FFh: x3 R/W 04

76 D7-0 PWB_BG[7:0] Preset WB setting for B pixels

00h: x1 80h: x2 FFh: x3 R/W 62

77 D7-0 Reserved Reserved R/W 00

D7 LSSC_SW Lens shading correction SW 0h: OFF 1h: ON D6-0 Reserved Reserved R/W 80

79 D7-0 Reserved Reserved R/W 52

7A D7-0 Reserved Reserved R/W 4F

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 23/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) 7B D7-0 LSSC_LEFT_RG[7:0] R gain on the left side for Lens shading correction 00h: Min. FFh: Max. R/W 00 7C D7-0 LSSC_LEFT_GG[7:0] G gain on the left side for Lens shading correction 00h: Min. FFh: Max. R/W 00 7D D7-0 LSSC_LEFT_BG[7:0] B gain on the left side for Lens shading correction 00h: Min. FFh: Max. R/W 00 7E D7-0 LSSC_RIGHT_RG[7:0] R gain on the right side for Lens shading correction 00h: Min. FFh: Max. R/W 00 7F D7-0 LSSC_RIGHT_GG[7:0] G gain on the right side for Lens shading correction 00h: Min. FFh: Max. R/W 00

80 D7-0 LSSC_RIGHT_BG[7:0]

B gain on the right side for Lens shading correction 00h: Min. FFh: Max. R/W 00

81 D7-0 LSSC_TOP_RG[7:0]

R gain on the top side for Lens shading correction 00h: Min. FFh: Max. R/W 00

82 D7-0 LSSC_TOP_GG[7:0]

G gain on the top side for Lens shading correction 00h: Min. FFh: Max. R/W 00

83 D7-0 LSSC_TOP_BG[7:0]

B gain on the top side for Lens shading correction 00h: Min. FFh: Max. R/W 00

84 D7-0 LSSC_BOTTOM_RG[7:0]

R gain on the bottom side for Lens shading correction 00h: Min. FFh: Max. R/W 00

85 D7-0 LSSC_BOTTOM_GG[7:0]

G gain on the bottom side for Lens shading correction 00h: Min. FFh: Max. R/W 00

86 D7-0 LSSC_BOTTOM_BG[7:0]

B gain on the bottom side for Lens shading correction 00h: Min. FFh: Max. R/W 00 D7-2 Reserved Reserved 87 D1-0 LSSC_MP_MODE[1:0] Gain setting for Lens shading correction 0h: x1/8 1h: x1/4 2h: x1/2 3h: x1 R/W 01

88 D7-0 Reserved Reserved R/W 00

89 D7-0 Reserved Reserved R/W 00

8A D7-0 PP_BLACK_ADJ[7:0] Black level setting after Lens shading correction 00h: Min. FFh: Max. R/W 40 8B D7-0 Reserved Reserved R/W 09 8C D7-0 Reserved Reserved R/W E0 8D D7-0 Reserved Reserved R/W C0 8E D7-0 Reserved Reserved R/W 80 8F D7-0 Reserved Reserved R/W C0

90 D7-0 Reserved Reserved R/W 80

D7 ANR_SW Noise reduction SW 0h: OFF 1h: ON D6-0 Reserved Reserved R/W 80

92 D7-0 AGMIN_ANR_WIDTH[7:0] Slice level setting for Noise reduction while Analog gain

condition is min. 00h: Min. FFh: Max. R/W 80

93 D7-0 AGMAX_ANR_WIDTH[7:0] Slice level setting for Noise reduction while Analog gain

condition is max. 00h: Min. FFh: Max. R/W 80

94 D7-0 AGMIN_ANR_MP[7:0] Gain setting for Noise reduction while Analog gain condition

is min. 00h: Min. FFh: Max. R/W 40

95 D7-0 AGMAX_ANR_MP[7:0] Gain setting for Noise reduction while Analog gain condition

is max. 00h: Min. FFh: Max. R/W 40 D7 DTL_SW Edge enhancement SW 0h: OFF 1h: ON D6-0 Reserved Reserved R/W 80

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 24/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex)

97 D7-0 AGMIN_HDTL_NC[7:0] Coring level setting for Horizontal edge enhancement while

Analog gain condition is min. 00h: Min. FFh: Max. R/W 07

98 D7-0 AGMIN_VDTL_NC[7:0] Coring level setting for Vertical edge enhancement while

Analog gain condition is min. 00h: Min. FFh: Max. R/W 03

99 D7-0 AGMAX_HDTL_NC[7:0] Coring level setting for Horizontal edge enhancement while

Analog gain condition is max. 00h: Min. FFh: Max. R/W 07 9A D7-0 AGMAX_VDTL_NC[7:0] Coring level setting for Vertical edge enhancement while Analog gain condition is max. 00h: Min. FFh: Max. R/W 03 9B D7-0 AGMIN_HDTL_MG[7:0] Edge enhancement gain setting to Horizontal edges toward black while Analog gain condition is min. 00h: Min. FFh: Max. R/W 80 9C D7-0 AGMIN_HDTL_PG[7:0] Edge enhancement gain setting for Horizontal edges toward white while Analog gain condition is min. 00h: Min. FFh: Max. R/W 20 9D D7-0 AGMIN_VDTL_MG[7:0] Edge enhancement gain setting for Vertical edges toward black while Analog gain condition is min. 00h: Min. FFh: Max. R/W 40 9E D7-0 AGMIN_VDTL_PG[7:0] Edge enhancement gain setting for Vertical edges toward white while Analog gain condition is min. 00h: Min. FFh: Max. R/W 10 9F D7-0 AGMAX_HDTL_MG[7:0] Edge enhancement gain setting for Horizontal edges toward black while Analog gain condition is max. 00h: Min. FFh: Max. R/W 80 A0 D7-0 AGMAX_HDTL_PG[7:0] Edge enhancement gain setting for Horizontal edges toward white while Analog gain condition is max. 00h: Min. FFh: Max. R/W 20 A1 D7-0 AGMAX_VDTL_MG[7:0] Edge enhancement gain setting for Vertical edges toward black while Analog gain condition is max. 00h: Min. FFh: Max. R/W 40 A2 D7-0 AGMAX_VDTL_PG[7:0] Edge enhancement gain setting for Vertical edges toward white while Analog gain condition is max. 00h: Min. FFh: Max. R/W 10 A3 D7-0 PE_HVDTL_G[7:0] Edge enhancement gain setting for Picture effect mode. It’s valid while PIC_EFFECT = 5h, 6h or 7h. 00h: Min. FFh: Max. R/W 80 D7 HCBC_SW Horizontal carrier boost correction SW 0h: OFF 1h: ON D6-0 Reserved Reserved R/W 82 A5 D7-0 AGMIN_HCBC_G[7:0] Gain setting for Horizontal carrier boost correction while Analog gain condition is min. 00h: Min. FFh: Max. R/W 55 A6 D7-0 AGMAX_HCBC_G[7:0] Gain setting for Horizontal carrier boost correction while Analog gain condition is max. 00h: Min. FFh: Max. R/W 55 A7 D7-0 Reserved Reserved R/W 80 A8 D7-0 Reserved Reserved R/W 80 A9 D7-0 Reserved Reserved R/W 80

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 25/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) D7 LMCC_BMG_SEL B-G coefficient polarity SW for Color matrix 0h: B-G 1h: G-B D6 LMCC_BMR_SEL B-R coefficient polarity SW for Color matrix 0h: B-R 1h: R-B D5 Reserved Reserved D4 LMCC_GMB_SEL G-B coefficient polarity SW for Color matrix 0h: G-B 1h: B-G D3 LMCC_GMR_SEL G-R coefficient polarity SW for Color matrix 0h: G-R 1h: R-G D2 Reserved Reserved D1 LMCC_RMB_SEL R-B coefficient polarity SW for Color matrix 0h: R-B 1h: B-R AA D0 LMCC_RMG_SEL R-G coefficient polarity SW for Color matrix 0h: R-G 1h: G-R R/W 09 AB D7-0 LMCC_RMG_G[7:0] R-G gain setting for Color matrix 00h: x0/256 FFh: x255/256 R/W 04 AC D7-0 LMCC_RMB_G[7:0] R-B gain setting for Color matrix 00h: x0/256 FFh: x255/256 R/W 10 AD D7-0 LMCC_GMR_G[7:0] G-R gain setting for Color matrix 00h: x0/256 FFh: x255/256 R/W 04 AE D7-0 LMCC_GMB_G[7:0] G-B gain setting for Color matrix 00h: x0/256 FFh: x255/256 R/W 08 AF D7-0 LMCC_BMR_G[7:0] B-R gain setting for Color matrix 00h: x0/256 FFh: x255/256 R/W 40 B0 D7-0 LMCC_BMG_G[7:0] B-G gain setting for Color matrix 00h: x0/256 FFh: x255/256 R/W 40 D7-6 GAM_SW[1:0] Gamma correction SW and gain setting 0h: OFF 1h: 0.65 2h: 0.55 3h: 0.45 D5-2 Reserved Reserved D1 YUVM_AWBDISP_SW AWB test display SW. This register is used with IPIX_DISP_SW=1. 0h: OFF 1h: ON D0 Reserved Reserved R/W 40 D7 Reserved Reserved B2 D6-0 R_MATRIX[6:0] R matrix coefficient for Y signal generating Y = (R_MATRIX[6:0] / 256) R + (B_MATRIX[6:0] / 256) B + ((256 - R_MATRIX[6:0] - B_MATRIX[6:0]) / 256) G The value When 00h is as same as one when 01h. R/W 4D D7 Reserved Reserved B3 D6-0 B_MATRIX[6:0] B matrix coefficient for Y signal generating Y = (R_MATRIX[6:0] / 256) R + (B_MATRIX[6:0] / 256) B + ((256 - R_MATRIX[6:0] - B_MATRIX[6:0]) / 256) G The value When 00h is as same as one when 01h. R/W 1C D7 UVG_SEL UV gain SW 0h: x0.5 1h: x1.0 D6 BRIGHT_SEL Brightness adjusting range SW D5-3 Reserved Reserved D2-0 PIC_EFFECT[2:0] Picture effect mode SW 0h: Normal 1h: Monochrome 2h: Sepia (Mono) 3h: Sepia (Color) 4h: Negative 5h: Emboss 6h: Black board sketch 7h: White board sketch R/W C8 B5 D7-0 CONTRAST[7:0] Contrast setting for Y signal00h: x0 FFh: x4 R/W 40

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 26/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) B6 D7-0 BRIGHT[7:0] Brightness setting for Y signal R/W 80 B7 D7-0 Reserved Reserved R/W 00 B8 D7-0 Reserved Reserved R/W FF B9 D7-0 U_GAIN[7:0] Gain setting for U signal U = (B - Y) / 128 x U_GAIN[7:0] R/W 48 BA D7-0 V_GAIN[7:0] Gain setting for U signal V = (R - Y) / 128 x V_GAIN[7:0] R/W 5B BB D7-0 SEPIA_US[7:0] DC offset level setting for U signal for Sepia effect picture R/W 78 BC D7-0 SEPIA_VS[7:0] DC offset level setting for V signal for Sepia effect picture R/W 90 BD D7-0 U_CORING[7:0] Coring level setting for U signal (small signal will be compressed) 00h: Min. FFh: Max. R/W 03 BE D7-0 V_CORING[7:0] Coring level setting for V signal (small signal will be compressed) 00h: Min. FFh: Max. R/W 03 D7 YDTL_SW Edge enhancement SW for high frequency components of Y signal 0h: OFF 1h: ON D6 UVLPF_SW LPF SW for UV signals 0h: OFF 1h: ON BF D5-0 Reserved Reserved R/W C0 C0 D7-0 YDTL_G[7:0] Edge enhancement gain setting for high frequency components of Y signal 00h: Min. FFh: Max. R/W 00 C1 D7-0 Reserved Reserved R/W 00 D7 ALC_SW ALC SW 0h: OFF 1h: ON D6 ALC_LOCK Holds the exposure condition of ALC 0h: OFF 1h: ON (Lock) D5-0 Reserved Reserved R/W 80 C3 D7-0 MES[7:0] Manual exposure adjusting (Lower bits). It’s valid while ALC_SW = OFF. 0000h: Min. 3FFFh: Max. R/W 2C D7-6 Reserved Reserved C4 D5-0 MES[13:8] Manual exposure adjusting (Upper bits). See Sub-address C3h. R/W 01 C5 D7-0 MDG[7:0] Manual Digital gain setting 00h: Min. FFh: Max. R/W 00 C6 D7-0 MAG[7:0] Manual Analog gain setting (Lower bits). It’s valid while ALC_SW = OFF. 000h: Min. FFFh: Max R/W 20 D7-6 AGCONT_SEL[1:0] Gain range setting for the changing gains according to AG condition. This setting affects AGMAX/MIN *** G registers. 0h: Min. 3h: Max. D5-4 Reserved Reserved D3-0 MAG[11:8] Manual Analog gain setting (Upper bits). See Sub-address C6h. R/W 80 C8 D7-0 AG_MIN[7:0] Min. limiter setting for Analog gain for ALC 00h: Min. FFh: Max. R/W 20 C9 D7-0 AG_MAX[7:0] Max. limiter setting for Analog gain for ALC 00h: Min. FFh: Max. R/W 0F

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 27/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) D7 AUTO_LES_SW Auto long exposure SW 0h: OFF 1h: ON D6-4 AUTO_LES_MODE[2:0] Time setting for Auto long exposure mode 0h: Min. (1V) 4h: Max. (16V) 5h-7h: Not available D3-2 ALC_WEIGHT[1:0] Weighted ALC measuring mode setting 0h: All pixels 1h: Central pixels only 2h: Not available 3h: Central pixels weighted CA D1-0 FLCK_ADJ[1:0] This register should be set according to the frame rate for flicker less condition. 0h: Frame rate < 3.75 fps 1h: 3.75 =< Frame rate < 7.5 fps 2h: 7.5 =< Frame rate < 15 fps 3h: 15 =< Frame rate < 30 fps R/W 03 CB D7-0 ALC_LV[7:0] ALC convergence level setting (Lower bits) 000h: Min. 3FFh: Max. R/W E0 D7-2 Reserved Reserved CC D1-0 ALC_LV[9:8] ALC convergence level setting (Upper bits) See Sub-address CBh. R/W 11 CD D7-0 ALC_LVW[7:0] Insensitive range setting for ALC convergence level 00h: Min. FFh: Max. R/W 0A CE D7-0 L64P600S[7:0] Sets the number of lines for 8/100 sec. (for AC 50Hz) or 8/120 sec (for AC 60Hz) (Lower bits) 866h: 2150 Line (Default) 867h–FFFh: Invalid R/W 99 D7 Reserved Reserved D6-4 ALC_VWAIT[2:0] Waiting time setting to stop ALC for a certain time at condition change 0h: Min. 7h: Max. CF D3-0 L64P600S[11:8] Sets the number of lines for 8/100 sec. (Upper bits). See Sub-address CEh. R/W 06 D0 D7-0 UPDN_SPD[7:0] ALC convergence speed setting 00h: Min. FF Max. R/W 80 D1 D7-0 Reserved Reserved R/W 20 D2 D7-0 NEAR_SPD[7:0] ALC convergence speed setting near the convergence level 00h: Min. FF Max. R/W 80 D3 D7-0 Reserved Reserved R/W 30 D7 AC5060 Manual setting for AC50/60Hz. While ACFDET = ON, this register is set as the initial AC mode setting for Auto flicker detection. 0h: AC 50Hz mode 1h: AC 60Hz mode D6 Reserved Reserved D5-0 ALC_SAFETY[5:0] Continuous alteration detection period setting to avoid ALC restarting for an instant luminance alternation 00h: Min. 3Fh: Max. R/W 8A D5 D7-0 Reserved Reserved R/W 02 D6 D7-0 Reserved Reserved R/W 4F D7-4 Reserved Reserved D3 ACFDET Auto flicker detection SW 0h: OFF (Manual setting by AC5060) 1h: ON (The initial condition is given by AC5060) D2-0 Reserved Reserved R/W 08 D8 D7-0 Reserved Reserved R/W 08 D9 D7-0 Reserved Reserved R/W FF DA D7-0 Reserved Reserved R/W 01 DB D7-0 Reserved Reserved R/W 00

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 28/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) DC D7-0 Reserved Reserved R/W 14 DD D7-0 Reserved Reserved R/W 00 D7 AWB_SW Auto white balance SW 0h: OFF 1h: ON D6 AWB_LOCK Holds Auto white balance condition 0h: OFF (AWB active) 1h: ON (AWB freeze) DE D5-0 Reserved Reserved R/W 80 DF D7-0 WB_MRG[7:0] R gain setting for manual WB 00h: Min. FFh: Max. R/W 80 E0 D7-0 WB_MGG[7:0] G gain setting for manual WB 00h: Min. FFh: Max. R/W 80 E1 D7-0 WB_MBG[7:0] B gain setting for manual WB 00h: Min. FFh: Max. R/W 80 E2 D7-0 WB_RBMIN[7:0] Lower limit gain setting for RB gain on AWB 00h: Min. FFh: Max. R/W 40 E3 D7-0 WB_RBMAX[7:0] Upper limit gain setting for RB gain on AWB 00h: Min. FFh: Max. R/W FF D7 HEXA_SW Hexagonal color detection gate SW 0h: OFF 1h: ON (Hexagonal gate active) D6 Reserved Reserved D5-4 COLGATE_RANGE[1:0] Range SW for Hexagonal color detection gate setting 0h: 1 pixel/step (total range: -127 to 127 pixels) 1h: 2 pixel/step (total range: -254 to 254 pixels) 2h: 4 pixel/step (total range: -508 to 508 pixels) 3h: 8 pixel/step (total range: -1016 to 1016 pixels) D3-1 Reserved Reserved D0 COLGATE_OPEN Opens the color detection gate 0h: OFF (Color gate active) 1h: ON (Opens gate, Color gate setting invalid) R/W 90 D7 Reserved Reserved E5 D6-0 RYCUTM[6:0] Lower limit level setting for R-Y of Hexagonal color detection gate 00h: Narrowest FFh: Widest R/W 20 D7 Reserved Reserved E6 D6-0 RYCUTP[6:0] Upper limit level setting for R-Y of Hexagonal color detection gate 00h: Narrowest FFh: Widest R/W 50 D7 Reserved Reserved E7 D6-0 BYCUTM[6:0] Lower limit level setting for B-Y of Hexagonal color detection gate 00h: Narrowest FFh: Widest R/W 38 D7 Reserved Reserved E8 D6-0 BYCUTP[6:0] Upper limit level setting for B-Y of Hexagonal color detection gate 00h: Narrowest FFh: Widest R/W 20 E9 D7-0 RBCUTL[7:0] Lower cross point on R-Y axis setting for Hexagonal color detection gate 80h: Widest 00h: Center 7Fh: Narrowest R/W F0 EA D7-0 RBCUTH[7:0] Upper cross point on R-Y axis setting for Hexagonal color detection gate 80h: Narrowest 00h: Center 7Fh: Widest R/W 18

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 29/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) D7 SQ_SW Square color detection gate SW 0h: OFF 1h: ON D6 SQ_POL Color detection mode SW for Square color detection gate 0h: Subtracts Square gate area from Hexagonal one 1h: Adds Square gate area to Hexagonal one D5-1 Reserved Reserved EB D0 YGATE_SW Luminance detection gate SW 0h: OFF (Opens gate) 1h: ON R/W 01 EC D7-0 RYCUTL[7:0] Lower R-Y level setting for Square color detection gate 80h: Widest 00h: Center 7Fh: Narrowest R/W 00 ED D7-0 RYCUTH[7:0] Upper R-Y level setting for Square color detection gate 80h: Narrowest 00h: Center 7Fh: Widest R/W 00 EE D7-0 BYCUTL[7:0] Lower B-Y level setting for Square color detection gate 80h: Widest 00h: Center 7Fh: Narrowest R/W 00 EF D7-0 BYCUTH[7:0] Upper B-Y level setting for Square color detection gate 80h: Narrowest 00h: Center 7Fh: Widest R/W 00 F0 D7-0 YGATE_L[7:0] Lower luminance level setting for Luminance detection gate 00h: Lowest (Widest) FFh: Highest (Narrowest) R/W 30 F1 D7-0 YGATE_H[7:0] Upper luminance level setting for Luminance detection gate 00h: Lowest (Narrowest) FFh: Highest (Widest) R/W FF D7-6 Reserved Reserved D5 IPIX_DISP_SW Displays the pixels for AWB accumulation. This register is used with YUVM_AWBDISP_SW=1. 0h: OFF 1h: ON D4-0 Reserved Reserved R/W 00 D7-5 Reserved Reserved F3 D4-0 AWB_U_UPDNLV[4:0] Coring level setting for Up/Down detection on B gain of AWB 00h: Low level 1Fh High level R/W 08 D7-5 Reserved Reserved F4 D4-0 AWB_V_UPDNLV[4:0] Coring level setting for Up/Down detection on R gain of AWB 00h: Low level 1Fh High level R/W 08 F5 D7-0 AWB_WAIT[7:0] Waiting time setting for Auto white balance 00h: No waiting time 80h: 128 frames FEh 254 frames FFh: Not available R/W 10 F6 D7-0 AWB_SPDDLY[7:0] Controls AWB convergence time. 00h: Short FFh: Long R/W 00 D7-6 Reserved Reserved F7 D5-0 AWB_SPD[5:0] AWB convergence speed setting 00h: Slow FFh: Fast R/W 20 D7 AWB_HUE_COR Locks AWB to prevent WB from being unbalance when RB gain reach upper or lower limit. 0h: OFF 1h: ON D6 Reserved Reserved D5 AWBSPD_FIX Fixed AWB convergence speed SW 0h: Slower near convergence level 1h: Constant speed D4-0 Reserved Reserved R/W 86 F9 D7-0 Reserved Reserved R/W 00 FA D7-0 H_START[7:0] Horizontal picture start position setting [H start point] = H_START[7:0] x 2 + 1 R/W 41

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 30/40 Sub Add. (Hex) bit Register name Description Read only or R/W Default (Hex) D7 Reserved Reserved FB D6-0 H_WIDTH[6:0] Horizontal picture size setting [H width] = H_WIDTH[6:0] x 8 R/W 50 FC D7-0 V_START[7:0] Vertical picture start position setting [V start point] = V_START[7:0] x 2 + 1 R/W 0C D7-6 Reserved Reserved FD D5-0 V_HEIGHT[5:0] Vertical picture size setting [V height] = V_HEIGHT[5:0] x 8 R/W 3C D7-4 PIC_FORMAT[3:0] Picture output format setting 0h: Raw-6 (Time shared 10bit) 1h: YUV422 (6bit) 4h: Raw-8 (Time shared 10bit) 5h: YUV422 (8bit) 8h: Raw-8 (8bit) 2h, 3h, 6h, 7h, 9h-Fh: Reserved FE D3-0 Reserved Reserved R/W 50 D7 SLEEP Software standby setting. Set this register with STANDBY. 0h: ON (Standby) 1h: OFF (Normal) D6 Reserved Reserved D5-4 PARALLEL_OUTSW[1:0] Data output test mode SW 0h: Normal 1h: All L 2h: All H 3h: All High-Z D3 DCLK_POL DCLK output polarity SW 0h: Normal 1h: Inverted FF D2-0 Reserved Reserved R/W 35

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 31/40 12. Electrical Characteristics 12.1. Absolute Maximum Ratings Items Symbol Rating Unit AVDD DVDD IOVDD -0.3 to 3.6 Power supply voltage DVDD15 AVDD15 -0.3 to 3.0 Input voltage V in -0.3 to IOVDD+0.3 V Input current of protection diode Iin +/- 20 mA Storage temperature T stg -30 to 85 ℃ The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with exceeded ratings may cause break down, damage and/or degradation to any other equipment. Applications using the device should be designed such that each maximum rating will never be exceeded in any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this documents. 12.2. Operating Conditions Rating Item Symbol Min. Typ. Max. Unit AVDD 2.6 2.8 3.0 DVDD 1.7 1.8 1.9 Power supply voltage DVDD15 *4 AVDD15 *4 1.4 1.5 1.6 Input voltage V in 0 - IOVDD V Operating temperature *1 Topr -20 to 60 Functional temperature *2 Tfunc -30 to 70 ℃ Notes: *1: Operating temperature is the temperature range that performance is guaranteed. *2: Functional temperature is the temperature range that function is guaranteed, however performance is not guaranteed. *4 In case the build-in regulator is not used.

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 32/40 12.3. DC Characteristics Condition: Ta=25 degree C AVDD=2.8V, DVDD =1.8V, IOVDD=1.8V Rating Items Symbol Conditions Min. Typ. Max. Unit DVDD I DVDD NORMAL - - 30 mA IOVDD I IOVDD NORMAL - - 5.1 mA AVDD I AVDD NORMAL Normal, 30fps, VGA - - 8 mA DVDD I DVDD SW STBY - - 500 μA IOVDD I IOVDD SW STBY - - 50 μA AVDD I AVDD SW STBY Standby mode (Software standby) - - 50 μA DVDD I DVDD HW STBY - - 10 μA IOVDD I IOVDD HW STBY - - 10 μA Current consumption AVDD I AVDD HW STBY Power down mode (Hardware standby) - - 10 μA EXTCLK input voltage (sine wave)* Peak to peak voltage Vpp CLK - 0.5 - 1.2 V Low level input voltage VIL CLK - - - IOVDDx0.2 V EXTCLK input (square wave) High level input voltage VIH CLK - IOVDDx0.8 - - V Low level output voltage VOL DOUT - - - IOVDDx0.2 V DATA output High level output voltage VOH DOUT - IOVDDx0.8 - - V Low level output voltage VOL SYNC - - - IOVDDx0.2 V HSYNC, VSYNC output High level output voltage VOH SYNC - IOVDDx0.8 - - V Low level output voltage VOL DCLK - - - IOVDDx0.2 V DCLK output High level output voltage VOH DCLK - IOVDDx0.8 - - V Low level input voltage VIL RESET - - - IOVDDx0.2 V RESET input High level input voltage VIH RESET - IOVDDx0.8 - - V Low level input voltage VIL PWRDWN - - - IOVDDx0.2 V PWRDWN input High level input voltage VIH PWRDWN - IOVDDx0.8 - - V Low level input voltage VIL SCL - - - IOVDDx0.2 V SCL input High level input voltage VIH SCL - IOVDDx0.8 - - V Low level input voltage VIL SDA - - - IOVDDx0.2 V High level input voltage VIH SDA - IOVDDx0.8 - - V SDA input/output Low level output voltage VOL SDA - - - 0.4 V *Note: In case of a sine wave using for EXTCLK, a coupling capacitor is required with the input terminal.

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 34/40 12.4.2. SDA and SCL Items Symbol Min. Max. Unit Notes Clock frequency fSCL 0 400 KHz Low period tLOW;SCL 1.3 - μs High period tHIGH;SCL 0.6 - μs Rise time t r;SCL - 300 ns SCL Fall time t f;SCL - 300 ns Rise time t r;SDA - 300 ns SDA Fall time t f;SDA - 300 ns Hold time(repeated) START condition After this period, the first clock pulse is generated tHD;STA 0.6 - μs Setup time for a repeated START condition tSU;STA 0.6 - μs Data hold time t HD;DAT 0 - ns Data setup time t SU;DAT 100 - ns Setup time for STOP condition tSU;STO 0.6 - μs Normal t SP1 0 50 ns Width of spike pulse Wake-up from sleep mode tSP2 0 20 ns *1) All values referred to V IHmin and V ILmax levels Table 10 SDA and SCL SDA SCL tf tr trtf tSP tHD;STA tLOW tHD;DAT tHIGH tSU;STA tHD;STA tSU;STO tBUF START RE-START STOP START tSU;DAT Figure 10 SDA and SCL

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 35/40 12.4.3. DATA7 to DATA0, DCLK, HSYNC and VSYNC Items Symble Min. Max. Unit Notes Rise time tr:DCLK - 6 ns DCLK Fall time tf:DCLK - 6 ns Rise time T r:DATA - 6 ns DATA0 to 7 HSYNC and VSYNC Fall time tf:DATA - 6 ns Setup time of data t pd:SU 10 - ns Hold time of data t pd:HD 10 - ns *1 All values referred to V OHmin and V OLmax levels. Table 11 DCLK and DATA out T pd:HD DCLK DATA T pd:SU T r;DCLK T f;DCLK T r;DATA ,T f;DATA V OH;DCLK V OL;DCLK V OH;DATA V OL;DATA Figure 11 DCLK and DATA out

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 36/40 13. Reference of Application Circuit Figure 12 Reference of application circuit TCM 9001 MD A 4 A 3 DCLK GND A 2 IOVDD A 5 VDD 15 E 4 VDD 15 C 4 GND B 3 DATA 0 B 1 DATA 1 B 2 DATA 2 B 4 DATA 3 C 1 DATA 4 C 2 DATA 5 C 3 DATA 6 D 4 DATA 7 B 6 DVDD E 2 GND E 3 GND C 6 PWRDWN D 1 HSYNC D 2 VSYNC D 3 RESET C 5 SDA D 6 SCL E 5 AVDD B 5 EXTCLK 0 . 1 μ F 0 . 1 μ F 0 . 1 μ F 0 . 1 μ F DCLK DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 HSYNC VSYNC ( 1 . 8 V typ . or 2 . 8 V typ .) IOVDD ( 1 . 8 V typ .) DVDD ( 2 . 8 V typ .) AVDD PWRDWN RESET SDA SCL EXTCLK

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 37/40 14. Characteristics of Lens ITEM VALUE UNITS Optical format 1/10 inch Horizontal - degree Vertical - degree Field of view Diagonal 67.0 degree F number F2.8 - TV distortion -0.6 % Focal length 1.3546 mm Manual focusing Fixed focus - Structure Doublet lens - Note: The optical values are obtained by simulation. Table 12 Characteristics of Lens

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 38/40 15. Module dimensions Unit: mm

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 39/40 16. Instruction for the Camera Module handling 1. Use a wrist strap for human body grounding while at work. 2. Do not touch the surface of lens with finger or hand to keep the lens clean. 3. Do not put stress on the lens block to keep optical performance. 5. Do not drop the camera module on the floor which causes breaking and flaw. 5. Pick up the edge of lens holder with fingers carefully if it is necessary for the assembly by direct handling. 6. Do not expose to strong light, such as the sun for long periods. These will be influence the optical characteristics. RESTRICTIONS ON PRODUCT USE ・The information contained herein subject to change without notice. ・The TOSHIBA is continuously working to improve the quality and reliability of its products. Nevertheless, semiconductor device in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in marking a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling guide for Semiconductor devices”, or “TOSHIBA Semiconductor Reliability Handbook” etc. ・The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliance, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all type of safety devices, etc.. Unintended Usage of TOSIHBA products listed in this document shall be made at the customer’s own risk. ・The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. ・The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. ・Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. ・The products described in this document are subject to foreign exchange and foreign trade control laws.

Preliminary Preliminary Preliminary Preliminary TCM9001MD V0.21 Dec. 12, 2008 40/40

Revision History

V0.1 Sep 29, 2008 New V0.21 Dec 12, 2008 Amended the Characteristics of Lens in page 37. Amended the Module dimensions in page 38.