TCM38C17IDL TI | Alldatasheet
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QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Single 5-V Supply /C0068Replaces Four TCM29C13-Type Combos (CODEC and Filters) /C0068Meets CCITT/(D3/D4) G.711 and G.714 Channel Bank Specifications /C0068Advanced Switched-Capacitor Filters and Sigma-Delta A/D and D/A Converter Technology With DSP Filtering /C0068m-Law or A-Law Companding — Pin-Selectable /C00682.048 MHz Operation /C00688 Vpp Full-Signal Differential Receiver Output /C0068Differential Signal Processing Architecture /C0068Low Crosstalk (< –100 dB), Low Idle-Channel Noise, and Good Power Supply Rejection /C0068Single PCM I/O for Simplified PCM Interface /C0068Reliable Submicron Silicon-Gate CMOS Technology
description
The TCM38C17IDL QCombo is a 4-channel single-chip PCM combo (pulse-code-modulated CODEC with a voice-band filtering) device. It performs the transmit encoding (A/D conversion) and receive decoding (D/A conversion), as well as the transmit and receive filtering functions required to meet CCITT G.711 and G.714 specifications in a PCM system. Each channel provides all the functions required to interface a full-duplex, 4-line voice telephone circuit with a TDM (time-division-multiplexed) system. The TCM38C17IDL is specifically designed for fixed-data-rate applications and is intended to replace four TCM29C13-type devices. Primary applications include digital transmission and switching of E1 carrier, PABX (private automatic branch exchange), and central office telephone systems and subscriber line concentrators. The device serves as the analog termination of a PCM line or trunk to the POTS (plain old telephone system) local-loop line. Other applications include any PCM digital-audio interface such as voice-band data storage systems and many digital signal processing applications that can benefit from the reduced footprint of a quad codec configuration and single-rail operation. Dynamic range and excellent idle-channel noise performance are maintained using the TI advanced 4Vt process technologies. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TI and QCombo are registered trademarks of Texas Instruments, Inc. DL PACKAGE (TOP VIEW) RBIAS AREF AVSS 0GSX 0ANLGIN– 0ANLGIN+ 0PWRO+ 0GSR 0PWRO– 1GSX 1ANLGIN– 1ANLGIN+ 1PWRO+ 1GSR 1PWRO– 0PDN 1PDN VSS DVSS DVDD DVDDPLL MCLK DVSSPLL ASEL REFLTR1 REFLTR2 AVDD 2GSX 2ANLGIN– 2ANLGIN+ 2PWRO+ 2GSR 2PWRO– 3GSX 3ANLGIN– 3ANLGIN+ 3PWRO+ 3GSR 3PWRO– 3PDN 2PDN 0FS 1FS 2FS 3FS PCMOUT RESET PCMIN
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
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description (continued) The TCM38C17IDL is available in a 48-pin plastic DL SSOP (shrink small-outline package) and is characterized for operation from –40°C to 85°C. functional block diagram SD ADC Digital Filter Compressor Output Register SD DAC Digital Filter Expander Input Register Frame Control Clock Buffer Switched- Capacitor Smoothing Filter Output Amplifier Inverting Amplifier PCMOUT MCLK (2.048 MHz) FS PCMIN GSX ANGLIN – ANGLIN + GSR PWRO + PWRO – Transmit Section Receive Section Antialias Filter Digital Input Digital Output Analog Input Analog Output NOTE A: One of four identical channels is depicted.
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AREF 2 Analog reference point (mid-supply). This voltage is generated internally at a nominal 2.375 V. An external decoupling capacitor (0.1 mF) should be connected from AREF to AVSS for filtering purposes. 0ANLGIN+ 6 I Noninverting analog input to uncommitted transmit operational amplifier for channel 0 0ANLGIN– 5 I Inverting analog input to uncommitted transmit operational amplifier for channel 0 1ANLGIN+ 12 I Noninverting analog input to uncommitted transmit operational amplifier for channel 1 1ANLGIN– 11 I Inverting analog input to uncommitted transmit operational amplifier for channel 1 2ANLGIN+ 43 I Noninverting analog input to uncommitted transmit operational amplifier for channel 2 2ANLGIN– 44 I Inverting analog input to uncommitted transmit operational amplifier for channel 2 3ANLGIN+ 37 I Noninverting analog input to uncommitted transmit operational amplifier for channel 3 3ANLGIN– 38 I Inverting analog input to uncommitted transmit operational amplifier for channel 3 ASEL 24 I A-law and m-law operation select. When ASEL is connected to ground, A-law is selected. When ASEL is connected to VDD, m-law is selected (digital). AVDD 46 Analog supply voltage, 5 V, ±5% AVSS 3 Analog ground return for AVDD supply DVDD 20 Digital supply voltage, 5 V, ±5% DVDDPLL 21 Phase-locked loop supply voltage, 5 V, ±5% DVSSPLL 23 Phase-locked loop ground return for DVDDPLL supply DVSS 19 Digital ground return for DVDD supply 0FS 31 I Frame synchronization clock input/time slot enable for channel 0 TX and RX (digital) 1FS 30 I Frame synchronization clock input/time slot enable for channel 1 TX and RX (digital) 2FS 29 I Frame synchronization clock input/time slot enable for channel 2 TX and RX (digital) 3FS 28 I Frame synchronization clock input/time slot enable for channel 3 TX and RX (digital) 0GSR 8 I Receive amplifier gain-set input (channel 0). The ratio of an external voltage divider network connected to 0PWRO– and 0PWRO+ determines the receive amplifier gain. Maximum gain occurs when 0GSR is connected to 0PWRO–, and minimum gain occurs when it is connected to 0PWRO+ (analog). 1GSR 14 I Receive amplifier gain-set input (channel 1). The ratio of an external voltage divider network connected to 1PWRO– and 1PWRO+ determines the receive amplifier gain. Maximum gain occurs when 1GSR is connected to 1PWRO–, and minimum gain occurs when it is connected to 1PWRO+ (analog). 2GSR 41 I Receive amplifier gain-set input (channel 2). The ratio of an external voltage divider network connected to 2PWRO– and 2PWRO+ determines the receive amplifier gain. Maximum gain occurs when 2GSR is connected to 2PWRO–, and minimum gain occurs when it is connected to 2PWRO+ (analog). 3GSR 35 I Receive amplifier gain-set input (channel 3). The ratio of an external voltage divider network connected to 3PWRO– and 3PWRO+ determines the receive amplifier gain. Maximum gain occurs when 3GSR is connected to 3PWRO–, and minimum gain occurs when it is connected to 3PWRO+ (analog). 0GSX 4 O Output terminal of internal uncommitted transmit operational amplifier for channel 0 (analog) 1GSX 10 O Output terminal of internal uncommitted transmit operational amplifier for channel 1 (analog) 2GSX 45 O Output terminal of internal uncommitted transmit operational amplifier for channel 2 (analog) 3GSX 39 O Output terminal of internal uncommitted transmit operational amplifier for channel 3 (analog) MCLK 22 I Master clock input (2.048 MHz) (digital) PCMIN 25 I Transmit PCM input (digital) PCMOUT 27 O Transmit PCM output (digital) 0PDN 16 I Power-down select for channel 0. This channel of the device is inactive with a CMOS low-level input to 0PDN and active with a CMOS high-level input to the terminal (digital). 1PDN 17 I Power-down select for channel 1. This channel of the device is inactive with a CMOS low-level input to 1PDN and active with a CMOS high-level input to the terminal (digital). 2PDN 32 I Power-down select for channel 2. This channel of the device is inactive with a CMOS low-level input to 2PDN and active with a CMOS high-level input to the terminal (digital).
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Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 3PDN 33 I Power-down select for channel 3. This channel of the device is inactive with a CMOS low-level input to 3PDN and active with a CMOS high-level input to the terminal (digital). 0PWRO+ 7 O Noninverting output of channel 0 power amplifier. 0PWRO+can drive a 600 W || 100 pF load differentially (analog). 0PWRO– 9 O Inverting output of channel 0 power amplifier. 0PWRO– can drive a 600 W || 100 pF load differentially (analog). 1PWRO+ 13 O Noninverting output of channel 1 power amplifier. 1PWRO+ can drive a 600 W || 100 pF load differentially (analog). 1PWRO– 15 O Inverting output of channel 1 power amplifier. 1PWRO– can drive a 600 W || 100 pF load differentially (analog). 2PWRO+ 42 O Noninverting output of channel 2 power amplifier. 2PWRO+ can drive a 600 W || 100 pF load differentially (analog). 2PWRO– 40 O Inverting output of channel 2 power amplifier. 2PWRO– can drive a 600 W || 100 pF load differentially (analog). 3PWRO+ 36 O Noninverting output of channel 3 power amplifier. 3PWRO+ can drive a 600 W || 100 pF load differentially (analog). 3PWRO– 34 O Inverting output of channel 3 power amplifier, 3PWRO– can drive a 600 W || 100 pF load differentially (analog). RBIAS 1 Bias current setting resistor. A 100 kW , ± 5% resistor should be connected between terminals RBIAS and AVSS to set the bias current of the device. REFLTR1 48 Voltage reference. A 1-mF external decoupling capacitor should be connected from REFLTR1 to AVSS for filtering purposes. REFLTR2 47 Voltage reference. A 1-mF external decoupling capacitor should be connected from REFLTR2 to AVSS for filtering purposes. RESET 26 I Reset. Reset for all internal registers is initiated when RESET is brought high (digital). VSS 18 Substrate bias. VSS should be externally connected to AVSS. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to AVSS. recommended operating conditions (see Notes 2 and 3) MIN NOM MAX UNIT Supply voltage, VDD 4.75 5 5.25 V High-level input voltage, VIH 0.8 × VDD V Low-level input voltage, VIL 0.2 × VDD V Load resistance between PWRO+ and PWRO– (differential), RL 600 W Load capacitance between PWRO+ and PWRO– (differential), CL 100 pF Operating free-air temperature, TA –40 85 °C NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed. 3. Voltages at analog inputs, outputs and the AVDD terminal are with respect to the AREF terminal. All other voltages are referenced to the DVSS terminal unless otherwise noted.
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current, total device, MCLK = 2.048 MHz, outputs not loaded, VDD = 5 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD Supply current from VDD Operating All channels 50† mA IDD Supply current from VDD Power down PDN (all channels) 11 mA † With 8 Vpp output digital interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage PCMOUT IOH = –3.2 mA 4.6 5 V VOL Low-level output voltage PCMOUT IOL = 3.2 mA 0 0.4 V IIH High-level input current, any digital input VI = 0.8 × VDD 10 mA IIL Low-level input current, any digital input VI = 0.2 × VDD 10 mA C i Input capacitance 5 pF C o Output capacitance 5 pF transmit amplifier input PARAMETER MIN TYP MAX UNIT Input current at ANLGIN+ and ANLGIN– ±100 nA Input offset voltage at ANLGIN+ and ANLGIN– ± 5 mV Common-mode rejection at ANLGIN+ and ANLGIN– 55 dB Open-loop voltage amplification at ANLGIN+ and ANLGIN– 60 dB Open-loop unity-gain bandwidth at ANLGIN+ and ANLGIN– 900 kHz Input resistance at ANLGIN+ and ANLGIN– 10 M W receive filter output PARAMETER TEST CONDITION MIN TYP ‡ MAX UNIT Output offset voltage at PWRO+/PWRO – Relative to AREF ± 80 mV Output resistance at PWRO+/PWRO – DC output 1 W ‡ All typical values are at VDD = 5 V, and TA = 25/C0095C.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) transmit and receive gain and dynamic range, VDD = 5 V, TA = 25°C (see Notes 4, 5, and 6) PARAMETER TEST CONDITION MIN TYP MAX UNIT Encoder milliwatt response (transmit gain tolerance)Signal input = 0 dBm0 ± 0.1 ± 0.18 dBm0 Encoder milliwatt response variation with temperature and power supplies TA = –40°C to 85°C, Supplies = ± 5% ± 0.08 dB Digital milliwatt response (receive tolerance gain) relative to zero-transmission-level point Signal input per CCITT G.711 ± 0.1 ± 0.18 dBm0 Digital milliwatt response variation with temperature and power supplies TA = –40°C to 85°C, Supplies = ± 5% ± 0.08 dB Zero-transmission–level point (0 dBm0), transmitm-law 0.747 Vrms() , channel A-law Input buffer configured for unity gain 0.75 Vrms Transmit overload signal level, peak-to-peak centered at AREF 3 Vpp Zero-transmission–level point (0 dBm0), receivem-law R L = 600 W at maximum gain 1.99 Vrms() , channel A-law R L = 600 W at maximum gain (Load is connected between PWRO d PWRO ) Vrms Receive overload signal level, fully differential PWRO+ and PWRO–) 7.8 8 Vpp NOTES: 4. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of the channel under test. 5. The input amplifier is set for noninverting unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder. 6. Receive output is measured single ended in the maximum-gain (unity) configuration. To set the output amplifier for maximum gain, GSR is connected to PWRO– and the output is taken at PWRO+. All output levels are (sin x)/x corrected. transmit and receive gain tracking over recommended ranges of supply voltage and operating free-air temperature, reference level = –10 dBm0 PARAMETER TEST CONDITION MIN TYP MAX UNIT 3 > input level ≥ –40 dBm0 ± 0.25 Transmit gain tracking error, sinusoidal input –40 > input level > –50 dBm0 ± 0.5 dB –50 ≥ input level ≥ –55 dBm0 ± 1.2 3 > input level ≥ –40 dBm0 ± 0.25 Receive gain tracking error, sinusoidal input –40 > input level > –50dBm0 ± 0.5 dB –50 ≥ input level ≥ –55 dBm0 ± 1.2 noise over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITION MIN TYP MAX UNIT Transmit noise, C-message weighted (m-law), PCMOUT ANLGIN+ = 0 V 10 12 dBrnC0 Transmit noise, psophometrically weighted (A-law), PCMOUT ANLGIN+ = 0 V –80 –75 dBm0p Receive noise, C-message-weighted quiet code at PWRO+ (m-law) PCMIN = 11111111 5 12 dBrnC0 Receive noise, psophometrically weighted at PWRO+ (A-law) PCMIN = 11010101 –85 –79 dBm0p
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITION MIN TYP † MAX UNIT VDD supply voltage rejection transmit channel 0 < f < 30 kHz Idle channel, Supply signal = 200 mVpp –40 dBVDD supply voltage rejection, transmit channel 30 < f < 50 kHz Supply signal = 200 mVpp , f measured at PCMOUT –45 dB VDD supply voltage rejection, receive channel0 < f < 30 kHz Idle channel, Suppl y signal = 200 mVpp, –40 dBDD yg j , (single-ended) 30 < f< 50 kHz Su ly signal 200 mV , narrow-band, f measured at PWRO+ –45 dB Crosstalk (same channel) attenuation, transmit-to-receive (single-ended) ANLGIN+ = 0 dBm0, f = 1.02 kHz, unity gain, PCMIN = lowest decode level, measured at PWRO+ ≤100‡ –75 dB Crosstalk (same channel) attenuation, receive-to-transmit (single-ended) PCMIN = 0 dBm0, f = 1.02 kHz, measured at PCMOUT ≤100‡ –75 dB Transmit to transmit ≤100‡ –76 Crosstalk (between channels) attenuation Transmit to receive 0 dBm0 300 Hz 3400 Hz ≤100‡ –78 dBCrosstalk (betw een channels) attenuation Receive to transmit 0 dBm0 , 300 H z – 3400 H z ≤100‡ –76 dB Receive to receive ≤100‡ –78 † All typical values are at VDD = 5 V, and TA = 25°C ‡ Actual levels were beneath the test equipment measurement floor. distortion over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN MAX UNIT T it i l t di t ti ti i id l i t (CCITT G 712 0 > ANLGIN > –30 dBm0 36 Transmit signal to distortion ratio, sinusoidal input (CCITT G.712 - Method 2) –30 > ANLGIN > –40 dBm0 30 dBMethod 2) –40 > ANLGIN > –45 dBm0 25 R i i l t di t ti ti i id l i t (CCITT G 712 0 > ANLGIN > –30 dBm0 36 Receive signal to distortion ratio, sinusoidal input (CCITT G.712 - Method 2) –30 > ANLGIN > –40 dBm0 30 dBMethod 2) –40 > ANLGIN > –45 dBm0 25 Transmit single-frequency distortion products Input signal = 0 dBm0 –46 dBm0 Receive single-frequency distortion products Input signal = 0 dBm0 –46 dBm0 CCITT G.712 (7.1) –35 Intermodulation distortion, end-to-end CCITT G.712 (7.2) –49 dBm0, Spurious out-of-band signals, end-to-end CCITT G.712 (6.1) –25 dBm0 CCITT G.712 (9) –40
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature (see Figure 1) PARAMETER TEST CONDITION MIN MAX UNIT
16.67 Hz –30
50 Hz –25
60 Hz –23
Gain (voltage amplification) relative to gain at 1 02 kHz Input amplifier set for unity gain, Noninverting maximum gain output 200 Hz –1.8 –0.125 dB1.02 kHz Noninverting maximum gain output, Input signal at ANLGIN is 0 dBm0 300 Hz to 3 kHz –0.15 0.15 dB g 3.3 kHz –0.35 0.15 3.4 kHz –1 –0.1 4 kHz –14 receive filter transfer over recommended ranges of supply voltage and operating free-air temperature (see Figure 2) PARAMETER TEST CONDITION MIN MAX UNIT Below 20 Hz 0.15 20 Hz 0.15 200 Hz –0.5 0.15 Gain (voltage amplification) relative to gain at 1.02 kHzInput signal at PCMIN 300 Hz to 3 kHz –0.15 0.15 dB(g ) g g is 0 dBm0 3.3 kHz –0.35 0.15 dB 3.4 kHz –1 –0.1 4 kHz –14 4.6 kHz and above –30 timing requirements clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 3 and 4) MIN NOM † MAX UNIT tc(MCLK) Clock period for MCLK 2.048 MHz systems 488.28 ns tr Rise time for MCLK 30 ns tf Fall time for MCLK 30 ns tw(MCLK) Pulse duration for MCLK (see Note 8) 220 ns Clock duty cycle [tw(MCLK) /tc(MCLK)] for MCLK 45% 50% 55% † All nominal values are at VDD = 5 V, and TA = 25°C. NOTE 7: FS clock must be phase-locked with MCLK.
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figures 3 and 4) MIN MAX UNIT tsu(FS) Setup time, frame sync, from FS↑ to MCLK↓ 100 tc (MCLK) –100 ns tsu(PCMIN) Setup time, receive data, from data valid to MCLK↓ 10 ns th(PCMIN) Hold time, receive data, from MCLK↓ to data invalid 60 ns th(RESET) Hold time, RESET terminal ↑ to reset activation 100 ns th(FS) Hold time, frame sync, from MCLK↑ to FS↓ 10 tc(MCLK) × 7 ns td(FS–FS) Delay time, between MCLK↓ while any channel FS high and MCLK↓ while next channel FS high (see Figure 6) tc(MCLK) × 64 ms switching characteristics propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see Figure 3) PARAMETER TEST CONDITION MIN MAX UNIT tpd1 Transmit clock↑ to bit 1 data valid at PCMOUT (data enable time on time slot entry) (see Note 8) C L = 0 to 100 pF 0 145 ns tpd2 Transmit clock↑ bit n to bit n data valid at PCMOUT (data valid time)C L = 0 to 100 pF 0 145 ns tpd3 Transmit clock↓ bit 8 to bit 8 hi-Z at PCMOUT (data float time on time slot exit) (see Note 9) C L = 0 pF 60 215 ns NOTE 8: Timing parameters tpd1 and tpd3 are referenced to the high-impedance state. absolute and relative delay times over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITION MIN TYP † MAX UNIT Transmit absolute delay time to PCMOUT Fixed data rate, MCLK = 2.048 MHz, Input to ANLGIN 1.02 kHz at 0 dBm0 500 ms f = 500 Hz – 600 Hz 170 Transmit differential envelope delay time f = 600 Hz – 1000 Hz 95 msy relative to transmit absolute delay time f = 1000 Hz – 2600 Hz 45 ms f = 2600 Hz – 2800 Hz 105 Receive absolute delay time to PWRO Fixed data rate, MCLK = 2.048 MHz, Digital input is digital milliwatt codes 190 ms f = 500 Hz – 600 Hz 45 Receive differential envelope delay time f = 600 Hz – 1000 Hz 35 msy relative to transmit absolute delay time f = 1000 Hz – 2600 Hz 85 ms f = 2600 Hz – 2800 Hz 110 † All typical values are at VDD = 5 V, and TA = 25°C.
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NOTE A: Gain (voltage amplification) is defined as gain relative to gain at 1 kHz –dB. Figure 1. Transmit-Filter Transfer Characteristics
NOTE A: Gain (voltage amplification) is defined as gain relative to gain at 1 kHz –dB. Figure 2. Receive-Filter Transfer Characteristics
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† Bit 1 = MSB = most significant bit and is clocked in first on the PCMIN terminal or is clocked out first on the PCMOUT terminal. ‡ Bit 8 = LSB = least significant bit and is clocked in last on the PCMIN terminal or is clocked out last on the PCMOUT terminal. Figure 3. PCM Transmit Timing † Bit 1 = MSB = most significant bit and is clocked in first on the PCMIN terminal or is clocked out first on the PCMOUT terminal. ‡ Bit 8 = LSB = least significant bit and is clocked in last on the PCMIN terminal or is clocked out last on the PCMOUT terminal. Figure 4. PCM Receive Timing
The TCM38C17IDL system reliability and design considerations are described in the following paragraphs. if supply current to the device is not limited. into a system with the power on. Figure 5. Latch-Up Protection Diode Connection
- Ensure that no signals are applied to the device before the power-up sequence is complete.
- Force a power down-condition in the device.
- Connect the master clock.
- Release the power-down condition.
- Apply FS synchronization pulses.
- Apply the analog signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
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system reliability and design considerations (continued) internal sequencing On the transmit channel, digital output PCMOUT is held in the high-impedance state for approximately four frames (500 ms) after power up. Frame sync must be applied to all four channels during this time. After this delay, PCMOUT is functional and occurs in the proper timeslot. Valid digital information, such as for on/off hook detection, is available almost immediately. To further enhance system reliability, PCMOUT is placed in a high-impedance state approximately 20 ms after an interruption of MCLK. This interruption could possibly occur with some kind of fault condition elsewhere in the system. power-down operation To minimize power consumption, a power-down mode is provided for each channel. To power down a channel, an external logic low signal is applied to the corresponding PDN terminal. In the power-down mode, the average power consumption is reduced to an average of 1 mW/channel. miscellaneous TCM38C17IDL timing and voltage references are described in the following paragraphs. data timing The TCM38C17IDL uses the 2.048 MHz master clock input to step data into and out of the device. An 8-kHz clock signal applied to the FS terminal sets the sampling frequency and indicates the beginning of data transfer. When MCLK goes low while FS is high, the frame sync is recognized. The next eight rising edges of MCLK step data out of PCMOUT, while data is received into PCMIN on the next eight falling edges of MCLK. It is recommended that frame sync pulses be one MCLK period in duration, but it is permissible for them to last up to seven MCLK periods from the recognition of the frame sync. Frame syncs for channels 0 through 3 must occur sequentially. When all four channels are in use, the frame syncs (downward edge of MCLK during frame sync high) must occur at nominal 64 MCLK pulse intervals, making the frame syncs evenly distributed. When one or more channels are not in use, the active frame syncs have greater timing flexibility, but still must be separated by a minimum of 64 MCLK periods (nominal 31.25 ms with 2.048 MHz MCLK). See Figure 6.
64 Clocks
2.048 MHz
8 Clocks
Figure 6. Frame Sync Timing
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The TCM38C17IDL transmit operation is described in the following paragraphs. than 50 pF. GSX also provides a means of sampling the amplified signal. Figure 7. Transmit Path Gain Setting Circuitry digital class 5 central office switching systems requirements. 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency noise. 200 Hz. This feature allows the use of low-cost transformer hybrids without external components.
The TCM38C17IDL receive operation is described in the following paragraphs. is a representation of the internal structure of the output amplifier. Figure 8. Output Amplifier Architecture
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
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APPLICATION INFORMATION
Various TCM38C17IDL output configurations are detailed in the following paragraphs. differential configuration For connection to a transformer, the fully differential configuration is recommended to provide maximum possible output, or voltage swing, to the primary of an attached transformer. Figure 9 shows the QCombo in a fully-differential mode. PWRO+ PWRO– GSR Vd R L VO+ VO– Figure 9. Fully Differential Gain-Setting Configuration R1 and R2, define a time constant that must be minimized to avoid inaccuracies in the gain calculations. determine the value of the attenuation constant is given in equation 1. which can also be expressed as shown in equation 2. 0.25 to unity (1), or approximately 12 dB of voltage adjustment.
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
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single-ended configuration Figure 13 illustrates the QCombo in a typical single-ended configuration. Gain is set by manipulating the resistor network in the same way as detailed for the differential mode. A SLIC should be ac-coupled to the TCM38C17. PWR+ PWR– GSR R L AREF Figure 13. Single-Ended Configuration
QCombo FOUR-CHANNEL (QUAD) PCM COMBO SLWS040C – JUNE 1996 – REVISED OCTOBER 1999 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040048/C 03/97
48 PIN SHOWN
0.730 (18,54) 0.720 (18,29) 4828 0.370 (9,40) (9,65) 0.380 Gage Plane DIM 0.420 (10,67) 0.395 (10,03) A MIN A MAX 0.006 (0,15) NOM PINS ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) Seating Plane 0.020 (0,51) 0.040 (1,02) 0.008 (0,203) 0.012 (0,305) 0.008 (0,20) MIN A 0.110 (2,79) MAX 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) M0.005 (0,13) 0.025 (0,635) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118
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