TCM3105DWL TI | Alldatasheet

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TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 Copyright  1994, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

  • Single-Chip Frequency-Shift-Keying (FSK) Modem
  • Meet Both Bell 202 and CCITT V23 Specifications
  • Transmit Modulation at 75, 150, 600, and

1200 Baud

  • Receive Demodulation at 5, 75, 150, 600, and 1200 Baud
  • Half-Duplex Operation Up to 1200 Baud Transmit and Receive
  • Full-Duplex Operation Up to 1200 Baud Transmit and 150 Baud Receive
  • On-Chip Group Equalization and Transmit/Receive Filtering
  • Carrier-Detect-Level Adjustment and Carrier-Fail Output
  • Single 5-V Power Supply
  • Low Power Consumption
  • Reliable CMOS Silicon-Gate Technology

description

The TCM3105 is a single-chip asynchronous frequency-shift-keying (FSK) voice-band modem that uses silicon-gate CMOS technology to implement a switched-capacitor architecture. It is pin selectable (TXR1, TXR2, and TRS) for a wide range of transmit/receive baud rates and is compatible with the applicable BELL 202 or CCITT V23 standards. Operation is fully reversible, thereby allowing both forward and backward channels to be used simultaneously. The transmitter is a programmable frequency synthesizer that provides two output frequencies (on TXA), representing the marks and spaces of the digital signal present on TXD. The receive section is responsible for the demodulation of the analog signal appearing at the RXA input and is based on the principle of frequency-to-voltage conversion. This section contains a group delay equalizer (to correct phase distortion), automatic gain control, carrier-detect-level adjustment, and bias-distortion adjustment, thereby optimizing performance and giving the lowest possible bit error rate. Carrier-detect information is given to the system by means of the carrier-detect circuits, which set a flag on the CDT output if the level of received in-band energy falls below a value set on the CDL input for a specified minimum duration. The TCM3105JE and TCM3105NE are characterized for operation from –40°C to 85°C.The TCM3105DWL, TCM3105JL, and TCM3105NL are characterized for operation from 0°C to 70°C. Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. VDD CLK CDT RXA TRS NC RXB RXD OSC2 OSC1 TXD TXR1 TXR2 TXA CDL V CC J OR N PACKAGE (TOP VIEW) VDD CLK CDT NC RXA NC TRS NC RXT NC RXB RXD OSC2 OSC1 TXD NC TXR1 NC NC TXR2 TXA NC CDL V SS DW PACKAGE (TOP VIEW) NC – No internal connection D package are available taped and reeled. Add the R suffix to device type (e.g., YCM3105DWLR). PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions TERMINAL DESCRIPTIONNAME NO. DESCRIPTIONNAME DW J OR N CDL 14 10 Carrier-detect-level adjust for external adjustment of carrier-detect threshold CDT 3 3 Carrier-detect output. A low-level output indicates carrier failure CLK 2 2 Output for a continuous clock signal at 16 times the highest selected (transmit or receive) bit rate NC 4, 6, 8, 10, 15, 18, 19, 21

6 No internal connection

OSC1, OSC2 23, 15, Oscillator connections. The crystal (typically 4.4336 MHz) is connected to OSC1 AND OSC2. If an external clock is used, OSC2 is left open and the clock is connected to OSC1. RXA 5 4 Receive analog input to which the received line signal must be ac coupled RXB 11 7 Receive bias adjust for external adjustment of the decision threshold of the comparator to minimize bias distortion RXD 12 8 Receiver digital output for the demodulated received data in positive logic. The high logic level is a mark and the low logic level is a space. RXT 9 – Receive test access. Output of limiter is available on RXT. (DW only) TRS 7 5 Transmit/receive standard select input, which with TXR1 and TXR2, sets the standard bit rates and mark/space frequencies TXA 16 11 Transmit analog output for the modulation signal, which must be ac coupled TXD 22 14 Transmit digital input for data to the transmitter in positive logic. The high logic level is a mark, and the low logic level is a space. The data can be accepted at any speed from zero to the selected speed and may be totally asynchronous. TXR1 20 13 Bit-rate select 1 input which along with TXR2 and TRS, sets the bit rates and mark/space frequencies TXR2 17 12 Bit rate select 2 input, which along with TXR1 and TRS, sets the bit rates and mark/space frequencies VDD 1 1 Positive supply voltage VSS 13 9 Most negative supply voltage (normally ground); connected to substrate

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram FSK Modulator Digital- to-Analog Converter XMT Filter Low-Pass Filter Automatic Gain Control Low-Pass Filter Receive Filter and Group Delay Equalizer Offset Compensation Comparator FSK Demodulator Comparator Carrier Detector Carrier- Detect Delay Timing and Control 4.4336-MHz Oscillator TXA RXD RXT CDT CLK TXD RXB RXA CDL OSC1 OSC2 TXE1 TXE2 TRS Transmit Digital Input Receive Bias Adjust Receive Analog Input Carrier-Detect Level Adjust Oscillator Connection Bit-Rate Select Transmit/Receive Standard Select Transmit Analog Output Receive Digital Output Receive Test Access Carrier- Detect Output Clock timing diagram Off/On Threshold On/Off Threshold RXA Input (amplitude of received signal) CDT Output td(off-on) td(on-off) t t

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) NOTE 1: Voltage values are with respect to VSS . recommended operating conditions TCM3105JE TCM3105NE TCM3105DWL TCM3105JL TCM3105NL UNIT MIN NOM MAX MIN NOM MAX Supply voltage, VDD 4 5 5.5 4 5 5.5 V High-level input voltage, VIH 2 VDD 2 VDD V Low-level input voltage, VIL 0 0.8 0 0.8 V Analog input level, peak to peak (ac coupled) 0.3 0.78 0.3 0.78 V Analog load impedance at TXA 50 50 kΩ Operating free-air temperature range, TA –40 85 0 70 °C

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TCM3105JE TCM3105NE TCM3105DWL TCM3105JL TCM3105NL UNIT MIN TYP † MAX MIN TYP † MAX VOH High-level output voltage RXD, CDT, CLK IOH = –100 µA 2.4 VDD 2.4 VDD V VOL Low-level output voltage RXD, CDT, CLK IOL = 1.6 mA VSS 0.4 VSS 0.4 V Analog output voltageTXA VDD = 4 V R5 0 k Ω 1.55 1.55 VAnalog output voltage level, peak to peak TXA VDD = 5 V R L = 50 kΩ , VDD = 5.5 V R L = 100 pF 2.1 2.1 Adjust voltage RXB VDD =5V VAdjust voltage CDL VDD = 5 V V Analog output dc offsetTXA VDD /2 VDD /2 V Digital input currentTXD, TRS, TRX1, TRX2 VI = 0 to VDD ± 1 ± 1 µA Analog input current RXA ± 15 ± 15 µA Bias input current RXB, CDL VI = 3 V ± 150 ± 150 µA I Sl VDD = 4 V 3 6 3 5 AIDD Supply current VDD = 5 V 5 10 5 8 mADD pp y VDD = 5.5 V 8 16 8 12 C i Input capacitance, all inputs f = 1 MHz 10 10 pF C o Output capacitance, all inputs f = 1 MHz 10 10 pF Phase jitter 200 200 µs Bias distortion‡ ± 15% ± 15% Carrier-detect threshold, off/on§ –45.5 –43 –45.5 –43 dBm Carrier-detect threshold, on/off§ –48 –45.5 –48 –45.5 dBm Carrier-detect hysteresis 2.5 2.8 2.5 2.8 dBm switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TCM3105JE TCM3105NE TCM3105DWL TCM3105JL TCM3105NL UNIT MIN TYP † MAX MIN TYP † MAX td(off on)Carrier-detect off-to-on delay time RX = 600 or 1200 b/s 12 25 12 25 mstd(off-on)C arrier-detect off-to-on delay time RX = 5, 75, or 150 b/s 48 80 48 80 ms td(on off)Carrier detect on to off delay time RX = 600 or 1200 b/s 12 20 12 20 mstd(on-off)Carrier-detect on-to-off delay time RX = 5, 75, or 150 b/s 48 75 48 75 ms Transmit frequency deviation from assignment (see Table 1) fclock = 4.4336 MHz ± 1 ± 1 Hz † All typical are at VCC = 5 V, TA = 25°C. ‡ Bias distortion is the departure from a 50% duty cycle when a series of alternating mark and space tones is received. § This is the threshold with the CDL input properly adjusted.

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a carrier detector, and control and timing (see Figure 1). Figure 1. TCM3105 System Partitioning input (TRS), the bit-rate select inputs (TXR1 and TXR2), and the digital data input (TXD). introduced by the transmit filter clock are removed by a continuous low-pass filter. converter to give a constant output level to the line. channel frequencies. These are typically present at much higher levels than the received signal. squarewave that is presented to the demodulator. by a switched-capacitor, low-pass, post-demodulator filter. comparator output is then the received data at RXD.

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 carrier detect The carrier-detect circuits comprise an energy detector and digital delay. The energy detector compares the total signal level at the output of the receive filter to an externally set threshold level on the CDL input. The comparator has a 2.5-dB hysteresis and a delay to allow for momentary signal loss and to prevent oscillation. The output detector is available on CDT where a high level indicates that a carrier is present. The data output is clamped to a mark condition when the carrier-detect output switches off at the end of transmission. control and timing An on-chip oscillator runs from an external 4.4336-MHz crystal connected between OSC1 and OSC2 or an external signal driving OSC1. A clock signal equal to 16 times the highest selected bit rate (transmit or receive) is available on the CLK output. The single-supply rail means that all analog functions are referenced to an internally generated reference. All analog inputs and outputs must be ac coupled. transmit and receive modes The various modes of operation of the TCM3105 are given in Table 1. The data convention is that a logic high is a mark and a logic low is a space.

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Table 1. Modes of Operation † In these modes, the modulation is controlled by TRS and TXR2. TXD is tied high.

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

APPLICATION INFORMATION

VDDVDD , VSS , or CLK 5 107 91615 Pin numbers shown are for the J and N packages. Figure 2. Typical System Configuration

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 A A _ A A 100 kΩ 100 kΩ 100 kΩ A 100 kΩ 100 kΩ 100 kΩ 100 kΩ100 kΩ A 100 kΩ 5 V 250 kΩ RX Gain Adj TX Gain Adj 250 kΩ 5 V 30 pF30 pF 100 kΩ TT R ZL ⇒ ZT 2 = 300 Ω ZT 2 = 300 Ω 1:1 50 kΩ ZT′ ZL′ 0.1 µF U1A U1B U1C U1D 0.1 µF VSS RXA Receive Data Transmit Data Carrier Detect Select Mode (bit rate and standard) 47 kΩ 5 V 47 kΩ 10 µF U1 = LM124 ZT ZL = ZT′ ZL′ 16 15 Pin numbers shown are for the J and N packages. Figure 3. Telephone Line Interface Circuit

TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 A A A 100 kΩ 100 kΩ 5 V 100 kΩ 30 pF30 pF T R ZL ⇒ U1A U1B 0.1 µF VSS U1 = 1/2LM124 ZT ZL = ZT′ ZL′ ZL′ A 47 kΩ 47 kΩ 10 µF 5 V ZT′ ZT = 600 Ω 0.1 µF 100 kΩ 100 kΩ 100 kΩ 5 V RXD CLK Receive Data Transmit Data Standard and Bit Rate Carrier Detect Clock 1615 Figure 4. Simplified Telephone Line Interface Circuit

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