TCM129C18N

TCM29C18 TI | Alldatasheet

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TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Reliable Silicon-Gate CMOS Technology /C0068Low Power Consumption – Operating Mode...8 0 m W – Power-Down Mode...5 m W /C0068µ-Law Coding /C0068Excellent Power-Supply Rejection Ratio Over Frequency Range of 0 Hz to 50 kHz /C0068No External Components Needed for Sample, Hold, and Autozero Functions /C0068Precision Internal Voltage Reference /C0068Single Chip Contains A/D, D/A, and Associated Filters

description

The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are low-cost single-chip PCM codecs (pulse-code-modulated encoders and decoders) and PCM line filters. These devices incorporate both the A/D and D/A functions, an antialiasing filter (A/D), and a smoothing filter (D/A). They are ideal for use with the TMS320 DSP family members, particularly those featuring a serial port such as the TMS32020, TMS32011, and TMS320C25. Primary applications include:

• Digital encryption systems
• Digital voice-band data storage systems
• Digital signal processing These devices are designed to perform encoding of analog input signals (A/D conversion) and decoding of digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a digital signal processing system. Both devices also provide band-pass filtering of the analog signals prior to encoding, and smoothing after decoding. The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of 0°C to 70°C. The TCM129C18 and TCM129C19 are characterized for operation over the temperature range of –40°C to 85°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright  1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. VBB PWRO+ PWRO– PDN DCLKR PCM IN FSR/TSRE DGTL GND VCC GSX ANLG IN ANLG GND TSX /DCLKX PCM OUT FSX/TSXE CLK DW OR N PACKAGE (TOP VIEW) FEATURES TABLE Number of Pins: Fixed Mode:

2.048 MHz (TCM29C18, TCM129C18),

1.536 MHz (TCM29C19, TCM129C19)

Coding Law: µ-Law Variable Mode: 64 kHz to 2.048 MHz 8-Bit Resolution 12-Bit Dynamic Range

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

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PWRO– GSX ANLG IN Transmit Section Receive Section Control Section PDN Control Logic DCLKR PCM IN Register Input Digital- to-Analog Control Logic Reference Sample and Hold and DAC Analog- to-Digital Control Logic Gain Set Filter Reference FSX/TSXE Autozero Output Register TSX / DCLKX PCM OUT Approximation SuccessiveComparator Sample and Hold and DAC Filter Σ CLK FSR/TSREANLG GND DGTL GND VBBVCC 138116

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION ANLG IN 14 I Inverting analog input to uncommitted transmit operational amplifier. ANLG GND 13 Analog ground return for all voice circuits. ANLG GND is internally connected to DGTL GND. CLK 9 I Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate mode. CLK is used for both the transmit and receive sections. DCLKR 5 I Fixed-data-rate mode — variable-data-rate mode select. When DCLKR is connected to VBB , the device operates in the fixed-data-rate mode. When DCLKR is not connected to VBB , the device operates in the variable-data-rate mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz. DGTL GND 8 Digital ground for all internal logic circuits. DGTL GND is internally connected to ANLG GND. FSR/TSRE 7 I Frame-synchronization clock input/time-slot enable for the receive channel. In the variable-data-rate mode, this signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR is TTL low for 30 ms. FSX/TSXE 10 I Frame-synchronization clock input/time-slot enable for transmit channel. FSX/TSXE operates independently of, but in an analogous manner to FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300 ms. GSX 15 O Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit filter. PCM IN 6 I Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock, which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing. PCM OUT 11 O Transmit PCM output. PCM data is clocked out of pcm out on eight consecutive positive transition of the transmit data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing. PDN 4 I Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TTL low-level input and active with a TTL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be connected to a TTL high level. PWRO+ 2 O Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly in either a differential or single-ended configuration. PWRO– 3 O Inverting output of power amplifier. PWRO– is functionally identical to PWRO+. TSX /DCLKX 12 I/O Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz. VBB 1 Negative supply voltage. Input is –5 V ± 5%. VCC 16 Positive supply voltage. Input is 5 V ± 5%.

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values for maximum ratings are with respect to VBB . recommended operating conditions (see Note 2) MIN NOM MAX UNIT VCC Supply voltage (see Note 3) 4.75 5 5.25 V VBB Supply voltage –4.75 –5 –5.25 V DGTL GND voltage with respect to ANLG GND 0 V VIH High-level input voltage, all inputs except ANLG IN 2.2 V VIL Low-level input voltage, all inputs except ANLG IN 0.8 V VI(PP) Peak-to-peak analog input voltage (see Note 4) 4.2 V R L Load resistance GSX 10 kΩ R L Load resistance PWRO+ and/or PWRO– 300 Ω C L Load capacitance GSX 50 pFC L Load capacitance PWRO+ and/or PWRO– 100 pF TA O perating free air temperature TCM29C18 or TCM29C19 0 70 °CTA Operating free-air temperature TCM129C18 or TCM129C19 –40 85 NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed. 3. Voltages at analog inputs and outputs and VCC and VBB terminals are with respect to ANLG GND. All other voltages are referenced to DGTL GND unless otherwise noted. 4. Analog inputs signals that exceed 4.2 V peak to peak may contribute to clipping and preclude correct A/D conversion. The digital code representing values higher than 4.2 V is 10000000. For values more negative than 4.2 V, the code is 0000000. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current, fDCLK = 2.048 MHz, outputs not loaded PARAMETER TEST CONDITIONS TCM29Cxx TCM129Cxx UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT Operating 10 14 ICC Supply current from VCC Standby FSX or FSR at VIL after 300 ms 1.2 1.5 mACC y CC Power down PDN at VIL after 10 µs 1 1.2 Operating –10 –14 IBB Supply current from VBB Standby FSX or FSR at VIL after 300 ms –1.2 –1.5 mA Power down PDN at VIL after 10 µs –1 –1.2

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ground terminals PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC resistance between ANLG GND and DGTL GND 34 Ω digital interface PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High level output voltage at PCM OUT IOH = –9.6 mA 2.4 VVOH High-level output voltage at PCM OUT IOH = –0.1 mA 3.5 V VOL Low-level output voltage at TSX IOL = 3.2 mA 0.5 V IIH High-level input current, any digital input VI = 2.2 V to VCC 12 µA IIL Low-level input current, any digital input VI = 0 to 0.8 V 12 µA C i Input capacitance 5 10 pF C o Output capacitance 5 pF † All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25°C. transmit side (A/D) characteristics PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Input offset voltage at ANLG IN VI = –2.17 V to 2.17 V ± 25 mV Input offset current at ANLG IN VI = –2.17 V to 2.17 V 1 pA Input bias current VI = –2.17 V to 2.17 V ± 100 nA Open-loop voltage amplification at GSX 5000 Unity-gain bandwidth at GSX 1 MHz Input resistance at ANLG IN 10 M Ω Gain-tracking error with sinusoidal input–3 ≥ dBm0 input level ≥ –40 dBm0, Ref level = –10 dBm0 ± 0.5 dBg (see Notes 5, 6, and 7) –40 > dBm0 input level ≥ –50 dBm0, Ref level = –10 dBm0 ± 25 dB Transmit gain tolerance VI = 1.06 V, f = 1.02 kHz 0.95 1.19 Vrms Noise Ref max output level: 200 Hz to 3 kHz –70 dB Supply-voltage rejection ratio, VCC to VBB f = 0 Hz to 30-kHz (measured at PCM OUT) idle channel, Supply signal = 200 mV peak to peak –20 dB Crosstalk attenuation, transmit to receive (single ended) ANLG IN = 0 dBm, PCM IN = lowest decode level, f = 1-kHz, unity gain, Measured at PWRO+ 62 dB Si l t di t ti ti i id l 0 dBm0 ≥ ANLG IN ≥ –30 dBm0 33 Signal-to-distortion ratio, sinusoidal input (see Note 8) –30 dBm0 > ANLG IN ≥ –40 dBm0 27 dBin ut (see Note 8) –40 dBm0 > ANLG IN ≥ –45 dBm0 22 Absolute delay time to PCM OUT Fixed-data rate, Input to ANLG IN = 1 kHz at 0 dB fCLKX = 2.048 MHz, 245 µs † All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25°C. NOTES: 5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms. 6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder. 7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO– to 0 dBM. All output levels are (sin x)/x corrected. 8. CCITT G.712 – Method 2

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

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receive side (D/A) characteristics (see Note 9) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Output offset voltage PWRO+ and PWRO– (single ended) Relative to ANLG GND ± 200 mV Output resistance at PWRO+ and PWRO– 1 2 Ω Gain-tracking error with sinusoidal–3 dBm0 ≥ input level ≥ –40 dBm0, Ref level = –10 dBm0 ± 0.5 dBg input (see Notes 5, 6, and 7) –40 dBm0 > input level ≥ –50 dBm0, Ref level = –10 dBm0 ± 25 dB Receive gain tolerance VI = 1.06 V, f = 1.02 kHz 1.34 1.69 Vrms Noise Ref max output level: 200 Hz to 3 kHz –70 dB Supply voltage rejection ratio, f = 0 Hz to 30-kHz, Supply signal 200 mVpeak topeak Idle channel, Narrow band 20 dByg j , VCC to VBB (single-ended) Supply signal = 200 mV peak to peak, Frequency at PWRO+ N arrow band, –20 dB Crosstalk attenuation, receive to transmit (single ended) PCM IN = 0 dB, Frequency = 1 kHz at PCM OUT 60 dB Si l t di t ti ti i id l 0 dBm0 ≥ ANLG IN ≥ –30 dBm0 33 Signal-to-distortion ratio, sinusoidal input (see Note 8) –30 dBm0 > ANLG IN ≥ –40 dBm0 27 dBin ut (see Note 8) –40 dBm0 > ANLG IN ≥ –45 dBm0 22 Absolute delay time to PWRO+ Fixed data rate, fCLKX = 2.048 MHz 190 µs † All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25°C. NOTES: 5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms. 6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder. 7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO– to 0 dBM. All output levels are (sin x)/x corrected. 8. CCITT G.712 – Method 2 9. The receive side (D/A) characteristics are referenced to a 600-Ω termination. timing requirements clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 3 and 4) MIN NOM MAX UNIT tc(CLK) Clock period for CLK (2.048-MHz systems) 488 ns tr, tf Rise and fall times for CLK 5 30 ns tw(CLK) Pulse duration for CLK 220 ns tw(DCLK) Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz) 220 ns Clock duty cycle, [tw(CLK)/tc(CLK)] for CLK 45% 50% 55% transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 3) MIN MAX UNIT td(FSX) Frame-sync delay time 100 tc(CLK) –100 ns receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, fixed-data-rate mode (see Figure 4) MIN MAX UNIT td(FSR) Frame-sync delay time 100 tc(CLK)–100 ns

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 5) MIN MAX UNIT td(TSDX) Delay time, time-slot from DCLKX (see Note 10) 140 td(DCLKX)–140 ns td(FSX) Delay time, frame sync 100 tc(CLK)–100 ns tc(DCLKX) Pulse duration, DCLKX 488 15620 ns NOTE 10: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation. receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, variable-data-rate mode (see Figure 6) MIN MAX UNIT td(TSDR) Delay time, time slot from DCLKR (see Note 11) 140 tw(DCLKR) –140 ns td(FSR) Delay time, frame sync TC(CLK) 100 tc(CLK)–100 ns tsu(PCM IN) Setup time before bit 7 falling edge 10 ns th(PCM IN) Hold time after bit 8 falling edge 60 ns tw(DCLKR) Pulse duration, DCLKR 488 15620 ns tSER Time-slot end receive time 0 ns NOTE 11: tFSLR minimum requirement overrides the tc(TSDR) maximum requirement for 64-kHz operation. 64 k-bit operation over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode MIN MAX UNIT tFSLX Transmit frame sync, minimum down timeFSX = TTL high for remainder of frame 488 ns tFSLR Receive frame sync, minimum down time FSR = TTL high for remainder of frame 1952 ns tw(DCLK) Pulse duration, data clock 10 µs switching characteristics propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see timing diagrams) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 Delay time from rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable time on time-slot entry) C L = 0 to 100 pF 0 145 ns tpd2 Delay time from rising edge of transmit clock bit n to bit n data valid at PCM OUT (data valid time) C L = 0 to 100 pF 0 145 ns tpd3 Delay time from falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time on time-slot exit) C L = 0 60 215 ns tpd4 Delay time from rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable time) C L = 0 to 100 pF 0 145 ns tpd5 Delay time from falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable time) C L = 0 60 190 ns propagation delay times over recommended ranges of operating conditions, variable-data-rate mode PARAMETER TEST CONDITIONS MIN MAX UNIT tpd6 Delay time from DCLKX 0 100 ns tpd7 Delay time from time-slot enable to PCM OUT C L = 0 to 100 pF 0 50 ns tpd8 Delay time from time-slot disable to PCM OUT 0 80 ns tpd9 Delay time from FSX td(TSDX) = 140 ns 0 140 ns

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300 Hz –2 dB

NOTE A: This is a typical transfer function of the receiver filter component. Figure 1. Transmit Filter Transfer Characteristics

NOTE A: This is a typical transfer function of the receive filter component. Figure 2. Receive Filter Transfer Characteristics

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B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output. Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output. Figure 3. Transmit Timing (Fixed-Data Rate) B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output. Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output. Figure 4. Receive Timing (Fixed-Data Rate)

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

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system reliability and design considerations TCM29C18, TCM29C19, TCM129C18, and TCM129C19 system reliability and design considerations are described in the following paragraphs. latch-up Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device if supply current to the device is not limited. Even though these devices are heavily protected against latch-up, it is still possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on. To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the power supply and GND (see Figure 7). If it is possible that a TCM29C18-, TCM29C19-, TCM129C18-, or TCM129C19-equipped card that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector traces are longer than the power and signal traces so that the card ground is always the first to make contact. device power-up sequence Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. Ensure that no signals are applied to the device before the power-up sequence is complete. 2. Connect GND. 3. Apply V BB (most negative voltage). 4. Apply VCC (most positive voltage). 5. Force a power down condition in the device. 6. Connect clocks. 7. Release the power down condition. 8. Apply FS synchronization pulses. 9. Apply the signal inputs. When powering down the device, this procedure should be followed in the reverse order.

Figure 7. Latch-Up Protection Diode Connection 20 µs after an interruption of CLKX. These interruptions could possibly occur with some kind of fault condition. To minimize power consumption, a power-down mode and three standby modes are provided. Table 1. Power-Down and Standby Procedures

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

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fixed-data-rate timing (see Figures 3 and 4) Fixed-data-rate timing is selected by connecting DCLKR to VBB and uses master clock CLK, frame- synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the sampling frequency. Data is transmitted on PCM OUT on the first eight positive transitions of CLK following the rising edge of FSX. Data is received on PCM IN on the first eight falling edges of CLK following FSX. A digital-to-analog (D/A) conversion is performed on the received digital word and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred to the receive filter. The TCM29C18 and TCM129C18 operate at 2.048 MHz only. The TCM29C19 and TCM129C19 operate at 1.536 MHz only. variable-data-rate timing Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather than to V BB . It uses master clock CLK, bit clocks DCLKX and DCLKR, and frame-synchronization clocks FSX and FSR. Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from 64 kHz to 2.048 MHz. The bit clocks must be asynchronous; however, the master clock is restricted to 2.048 MHz. When FSX/TSXE is high, PCM data is transmitted from PCM OUT onto the highway on the next eight consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM word is received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR. The transmitted PCM word is repeated in all remaining time slots in the 125-µs frame as long as DCLKX is pulsed and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than once per frame if desired, is available only with variable-data-rate timing. asynchronous operation In either timing mode, the master clock, data clock, and time slot-strobe must be synchronized at the beginning of each frame. Specifically, in the variable-rate mode, the falling edge of CLKX must occur within td(FSX) ns after the rise of FSX, and the falling edge of DCLKX must occur within tTSDX ns after the rise of FSX. CLK and DCLKX are synchronized once per frame but may be of different frequencies. The receive channel operates in a similar manner and is completely independent of the transmit timing (see Figure 6).

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION transmit operation transmit filter The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than 10 kΩ in parallel with less than 50 pF. The input signal on ANLG IN can be either ac or dc coupled. A low-pass antialiasing filter section is included on the device. This section provides 35-dB attenuation at the sampling frequency. No external components are required to provide the necessary antialiasing function for the switched-capacitor section of the transmit filter. The pass band section provides flatness and stopband attenuation that fulfills the AT&T D3/D4 channel bank transmission specification and CCITT recommendation G.712. The device specifications meet or exceed digital class 5 central office switching-systems requirements. A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation at 200 Hz. This feature allows the use of low-cost transformer hybrids without external components. encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sample- and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor array. Digital date representing the sample is transmitted on the first eight data clock bits of the next frame. The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses the sign bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the encoder. All dc offset is removed from the encoder input waveform. The analog input is encoded into an 8-bit digital representation by using the µ-law encoding scheme (CCITT G.711) that equates to 12 bits of resolution for low amplitude signals. Similarly, the decoding section converts 8-bit PCM data into an analog signal with 12 bits of dynamic range. The filter characteristics (band pass) for the encoder and decoder are determined by a single clock input (CLK). The filter roll off (–3 dB) is derived by: f co =k • fCLK /256 for the TCM29C18 and TCM129C18 fco =k • fCLK /192 for the TCM29C19 and TCM129C19 where k has a value of 0.44 for the high-frequency roll-off point and a value of 0.019 for the low-frequency roll-off point. The sampling rate of the ADC is determined by the transmit frame-sync clock (FSX); the sampling rate of the DAC is determined by the receive frame-sync clock (FSR). Once a conversion is initiated by FSX or FSR, data is clocked in or out on the next eight consecutive clock pulses in the fixed-rate-mode. Likewise, data may also be transferred on the next eight consecutive clock pulses of the data clocks (DCLKX and DCLKR) in the variable-data-rate mode. In the variable-data-rate mode, DCLKX and DCLKR are independent but must be in the range from f CLK /32 to fCLK .

TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996

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The serial PCM word is received at PCM IN on the first eight data clock bits of the frame. Digital-to-analog conversion is performed and the corresponding analog sample is held on an internal sample-and-hold capacitor. This sample is transferred to the receive filter. receive filter The receive section of the filter provides pass band flatness and stop band rejection that fulfills both the AT&T D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin x)/x response of such decoders. receive output power amplifiers A balanced-output amplifier is provided to allow maximum flexibility in output configuration. Either of the two outputs can be used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively, the differential output directly drives a bridged load. The output stage is capable of driving loads as low as 300Ω single ended to a level of 12 dBm or 600 Ω differentially to a level of 15 dBm. Transmission levels are specified relative to the receive channel output under digital milliwatt conditions (i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711). output gain The devices are internally connected to set PWRO+ and PWRO– to 0 dBm.

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