TCD1711DG TOSHIBA | Alldatasheet
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TOSHIBA CCD Linear Image Sensor CCD (Charge Coupled Device) TCD1711DG
Rev.1.1 2019-03-27 1 © 2019 Toshiba Electronic Devices & Storage Corporation TOSHIBA CCD Linear Image Sensor CCD (Charge Coupled Device) TCD1711DG The TCD1711DG is a high sensitive and low dark current 7450 elements CCD linear image sensor. The device contains a row of 7450 elements photodiodes which provide 24 lines/mm across a A3 size paper. The device is operated by 5.0 V pulse and 10 V power supply.
Features
Number of Image Sensing Elements: 7450 elements Image Sensing Element Size: 4.7 m by 4.7 m on 4.7 m center Photo Sensing Region: High sensitive PN photodiode Clock: 2-phase (5 V) Power Supply Voltage: 10 V (typ.) Internal Circuit: Clamp circuit Package: 22 pin CERDIP ABSOLUTE MAXIMUM RATINGS (Note 1) Characteristics Symbol Rating Unit Clock pulse voltage V 0.3 to +8.0 V Shift pulse voltage VSH Reset pulse voltage VRS Clamp pulse voltage VCP Power supply voltage VOD 0.3 to +15.0 Operating temperature Topr 0 to 60 °C Storage temperature Tstg 25 to +85 °C Note 1: All voltages are with respect to SS terminals (ground). None of the ABSOLUTE MAXIMUM RATINGS must be exceeded, even instantaneously. If any one of the ABSOLUTE MAXIMUM RATINGS is exceeded, the electrical characteristics, reliability and life time of the device cannot be guaranteed. If the ABSOLUTE MAXIMUM RATINGS are exceeded, the device can be permanently damaged or degraded. Create a system design in such a manner that any of the ABSOLUTE MAXIMUM RATINGS will not be exceeded under any circumstances. WDIP22-G-400-2.54E Pin Connections (top view) OS2 22 SS CP 1E2 2E2 OS1 1 OD RS 2B 2O2 SS 2E1 1E1 SS 2O1 1O1 NC SH 7450 2B 1O2 NC NC
Rev.1.1 2019-03-27 2 © 2019 Toshiba Electronic Devices & Storage Corporation Circuit Diagram Pin Names Pin No. Symbol Name Pin No. Symbol Name
1 OS1 Output signal 1 22 OS2 Output signal 2
2 OD Power supply 21 SS Ground
3 RS Reset gate 20 CP Clamp gate
4 2B Last stage transfer clock (phase 2) 19 2B Last stage transfer clock (phase 2) 5 1O2 Transfer clock 2 (phase 1) 18 1E2 Transfer clock 2 (phase 1) 6 2O2 Transfer clock 2 (phase 2) 17 2E2 Transfer clock 2 (phase 2)
7 NC Non connection 16 NC Non connection
8 SS Ground 15 SS Ground
9 2O1 Transfer clock 1 (phase 2) 14 2E1 Transfer clock 1 (phase 2) 10 1O1 Transfer clock 1 (phase 1) 13 1E1 Transfer clock 1 (phase 1)
11 NC Non connection 12 SH Shift gate
2B 1E2 2E2 CP
22 OS2
CCD analog shift register 2 1E1 2E1 SS Shift gate 1 Signal output buffer CCD analog shift register 1 8 4 5 6 3
1 OS1
RS 2B 2O2 1O2 OD 21 SS SS 1O1 2O1 12 SH
Rev.1.1 2019-03-27 3 © 2019 Toshiba Electronic Devices & Storage Corporation Optical/Electrical Characteristics Ta 25°C, VOD 10 V, V VSH VRS VCP 5 V (pulse), f 1.0 MHz, tINT (integration time) 10 ms, light source daylight fluorescent lamp Characteristics Symbol Min Typ. Max Unit Note Sensitivity R 12 15 18 V/lxs Photo response non uniformity PRNU 4 10 % (Note 2 ) PRNU (3) 6 12 mV (Note 8) Saturation output voltage VSAT 1.5 1.8 V (Note 3) Saturation exposure SE 0.08 0.12 lxs (Note 4) Dark signal voltage VDRK 1 3 mV (Note 5) Dark signal non uniformity DSNU 4 10 mV (Note 5) DC power dissipation PD 250 375 mW Total transfer efficiency TTE 92 98 % Output impedance ZO 0.2 1.0 k Dynamic range DR 1800 (Note 6) DC output signal voltage VOS1 3.0 4.5 6.0 V (Note 7) VOS2 3.0 4.5 6.0 DC differential error voltage │VOS1 VOS2│ 300 mV Random noise ND 1.0 mV (Note 9) Note 2: PRNU is defined on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature, where measured approximately 750 mV of signal output. PRNU X 100 (%) X Where X is average of total signal output and X is the maximum deviation from X under uniform illumination. (OS1) In the case of 3725 elements (OS2), the condition is the same as above too. Note 3: VSAT is defined as the minimum saturation output voltage of all effective pixels. Note 4: Definition of SE: SE VSAT R Note 5: VDRK is defined as average dark signal voltage of all effective pixels. DSNU is defined by the difference between average value (VDRK) and the maximum value of the dark voltage. Note 6: Definition of DR: DR VSAT VDRK VDRK is proportional to tINT (integration time). So shorter integration time makes wider dynamic range. OS VDRK DSNU
Rev.1.1 2019-03-27 4 © 2019 Toshiba Electronic Devices & Storage Corporation Note 7: DC output signal voltage is defined as follows. Note 8: PRNU (3) is defined as the maximum voltage with next pixel, where measured approximately 50 mV of signal output. Note 9: Random noise is defined as the standard deviation (sigma) of the output level difference between two adjacent effective pixels under no illumination (i.e. dark condition) calculated by the following procedure. 1) Two adjacent pixels (pixel n and n1) in one reading are fixed as measurement points. 2) Each of the output levels at video output periods averaged over 200 ns period to get V(n) and V(n1). 3) V(n1) is subtracted from V(n) to get V. V V(n) V(n1) 4) The standard deviation of V is calculated after procedure 2) and 3) are repeated 30 times (30 readings). 30 ΔVi 1ΔV 2V|Vi|30 5) Procedure 2), 3) and 4) are repeated 10 times to get sigma value. 6) 10 sigma values are averaged. j10 value calculated using the above procedure is observed 2 times larger than that measured relative to the ground level. So we specify the random noise as follows. ND SS VOS OS Video output 200 ns Pixel n Pixel n1 Output waveform (Effective pixels under dark condition) Video output 200 ns
Rev.1.1 2019-03-27 5 © 2019 Toshiba Electronic Devices & Storage Corporation Recommended Operating Conditions (Ta 25°C) For best performance, the device should be used within the Recommended Operating Conditions. Characteristics Symbol Min Typ. Max Unit Clock pulse voltage “H” level V1E, V1O V2E, V2O 4.5 5.0 5.5 V “L” level 0 0 0.5 Last stage clock pulse voltage “H” level V2B 4.5 5.0 5.5 V “L” level 0 0 0.5 Shift pulse voltage “H” level VSH 4.5 5.0 5.5 V “L” level 0 0 0.5 Reset pulse voltage “H” level VRS 4.5 5.0 5.5 V “L” level 0 0 0.5 Clamp pulse voltage “H” level VCP 4.5 5.0 5.5 V “L” level 0 0 0.5 Power supply voltage VOD 9.5 10.0 11.0 V Clock Characteristics (Ta 25°C) For best performance, the device should be used within the Recommended Operating Conditions. Characteristics Symbol Min Typ. Max Unit Clock pulse frequency f 1 30 MHz Reset pulse frequency fRS 1 30 MHz Clamp pulse frequency fCP 1 30 MHz Clock capacitance (Note 10) CE 70 pF CO 70 Last stage clock capacitance CB 10 pF Shift gate capacitance CSH 20 pF Reset gate capacitance CRS 10 pF Clamp gate capacitance CCP 10 pF Note 10: VOD 10 V, Input capacitance per a pin.
Rev.1.1 2019-03-27 6 © 2019 Toshiba Electronic Devices & Storage Corporation Timing Chart Effective outputs (3725 elements) SH 1E, 1O 2E, 2O, 2B tINT (integration time) RS CP OS1 OS2 *1: Keep the RS pin “L” level. *2: Keep the CP pin “L” level. D24 *2 D26 D28 D30 D32 D34 D36 D38 D40 D120 D122 D124 D126 S7447 S7449 D128 D130 D132 D134 D136 D138 D140 D142 D25 D27 D29 D31 D33 D35 D37 D39 D41 D121 D123 D125 D127 S7448 S7450 D129 D131 D133 D135 D137 D139 D141 D143 (3 elements) Light shielded outputs (48 elements) Dummy outputs (13 elements) (3 elements) Dummy outputs (4 elements) Dummy outputs (8 elements) Dummy outputs (64 elements) 1 line readout period (3797 elements) Test output (1 element)
Rev.1.1 2019-03-27 7 © 2019 Toshiba Electronic Devices & Storage Corporation Timing Requirements Note 11: Keep the RS and CP pins “L” level. 1O SS 1.5 V (min) 1.5 V (min) 1, 2 cross point 1E SS 1.5 V (min) 1.5 V (min) 2O 2E t2 t3 t4 SH 1E, 1O SH, 1 timing 4.5 V 0.5 V 4.5 V 4.5 V 4.5 V 0.5 V 4.5 V 0.5 V 2, RS, CP, OS timing t6 t7 t8 t9 t10 t17 t16 t15 t13 t12 t14 2B RS CP t11 OS1 OS2 4.5 V 0.5 V 0.5 V 0.5 V t19 t17 t18 t16 (Note 11) SH, RS, CP timing SH RS CP 4.5 V 0.5 V
Rev.1.1 2019-03-27 8 © 2019 Toshiba Electronic Devices & Storage Corporation Characteristics Symbol Min Typ. (Note 12) Max Unit Pulse timing of SH and 1E, 1O t1, t5 200 500 ns SH pulse rise time, fall time t2, t4 0 50 ns SH pulse width t3 1000 1500 ns 2B pulse rise time, fall time t6, t7 0 100 ns RS pulse rise time, fall time t8, t10 0 20 ns RS pulse width t9 8 100 ns Video data delay time t11 8 ns CP pulse rise time, fall time t12, t14 0 20 ns CP pulse width t13 8 100 ns Pulse timing of 2B and CP t15 0 50 ns Pulse timing of RS and CP t16 0 100 ns t17 8 100 ns Pulse timing of SH and CP t18 200 ns Pulse timing of SH and RS t19 200 ns Note 12: Measured with fRS 1 MHz.
Rev.1.1 2019-03-27 9 © 2019 Toshiba Electronic Devices & Storage Corporation Typical Spectral Response Spectral Response Wavelength [nm] Relative response
Rev.1.1 2019-03-27 10 © 2019 Toshiba Electronic Devices & Storage Corporation Cautions 1. Electrostatic Breakdown Store in shorting clip or in conductive foam to avoid electrostatic breakdown. CCD Image Sensor is protected against static electricity, but inferior puncture mode device due to static electricity is sometimes detected. In handing the device, it is necessary to execute the following static electricity preventive measures, in order to prevent the trouble rate increase of the manufacturing system due to static electricity. a. Prevent the generation of static electricity due to friction by making the work with bare hands or by putting on cotton gloves and non-charging working clothes. b. Discharge the static electricity by providing earth plate or earth wire on the floor, door or stand of the work room. c. Ground the tools such as soldering iron, radio cutting pliers of or pincer. d. Ionized air is recommended for discharge when handling CCD image sensors. It is not necessarily required to execute all precaution items for static electricity. It is all right to mitigate the precautions by confirming that the trouble rate within the prescribed range. 2. Window Glass The dust and stain on the glass window of the package degrade optical performance of CCD sensor. Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and allow the glass to dry, by blowing with filtered dry N2. Care should be taken to avoid mechanical or thermal shock because the glass window is easily to damage. 3. Incident Light CCD sensor is sensitive to infrared light. Note that infrared light component degrades resolution and PRNU of CCD sensor. 4. Mounting on a PCB This package is sensitive to mechanical stress. TOSHIBA recommends using IC inserters for mounting, instead of using lead forming equipment. Since this package is not strong against mechanical stress, you should not reform the lead frame. We recommend to use an IC-inserter when you assemble to PCB. 5. Soldering Soldering by the solder flow method cannot be guaranteed because this method may have deleterious effects on prevention of window glass soiling and heat resistance. Using a soldering iron, complete soldering within three seconds for lead temperatures of up to 350°C.
Rev.1.1 2019-03-27 11 © 2019 Toshiba Electronic Devices & Storage Corporation Package Dimensions WDIP22-G-400-2.54E 0 to 15° (Note 1) (Note 3) (Note 2) Note 1: Distance between the edge of the package and the first pixel (S1) Note 2: Distance between the top of chip and bottom of the package Note 3: Glass thickness (n = 1.5)
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