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© Semiconductor Components Industries, LLC, 2015 November, 2015 − Rev. 2

1 Publication Order Number:

TCC−202/D TCC-202 Two-Output PTIC Control IC Introduction TCC−202 is a two−output high−voltage digital to analog control IC specifically designed to control and bias ON Semiconductor’s Passive Tunable Integrated Circuits (PTICs). These tunable capacitor control circuits are intended for use in mobile phones and dedicated RF tuning applications. The implementation of ON Semiconductor’s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance. The tunable capacitors are controlled through a bias voltage ranging from 1 V to 24 V . The TCC−202 high−voltage PTIC control IC has been specifically designed to cover this need, providing two independent high−voltage outputs that control up to two different tunable PTICs in parallel. The device is fully controlled through a MIPI interface. Key Features

  • Controls ON Semiconductor’s PTIC Tunable Capacitors
  • Compliant with Timing Needs of Cellular and Other Wireless System Requirements
  • Integrated Boost Converter with 2 Programmable DAC Outputs (up to 24 V)
  • Low Power Consumption
  • MIPI−RFFE Interface
  • Compliant with MIPI 26 MHz Read−back
  • Available in WLCSP (RDL ball arrays)
  • This is a Pb−Free Device Typical Applications
  • Multi−band, Multi−standard, Advanced and Simple Mobile Phones
  • Tunable Antenna Matching Networks
  • Compatible with Closed−loop and Open−loop Antenna Tuner

Applications

www.onsemi.com See detailed ordering and shipping information on page 21 of this data sheet.

ORDERING INFORMATION

A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071= Pb−Free Package XXXX ALYW /C0071

Table 1. PAD DESCRIPTIONS

  1. To be grounded when not in use.

Table 2. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

Table 3. RECOMENDED OPERATING CONDITIONS

0 V steady state

2 V steady state

16 V steady state

Table 5. BOOST CONVERTER CHARACTERISTICS Table 6. ANALOG OUTPUTS (OUT A, OUT B)

Control IC Functional Block Diagram).

24 V , with 128 steps of 188 mV (2x (24 / 255 V) =

approximated to 188 mV x DAC value. startup default level for the boosted voltage is VHV = 24 V . OUT voltage of any of the two outputs.

  1. Shutdown Mode: All circuit blocks are off, the

the registers are not maintained in shutdown mode.

  1. Startup Mode: Startup is only a transitory mode.
  2. Active Mode: All blocks of the TCC−202 are

automatically entered from the startup mode. power mode under control software command.

  1. Low Power Mode: In low power mode the serial

registers are maintained in the low power mode. Figure 3. Modes of Operation

only minimal leakage current. enable the POR to trigger again. Table 7. VIO POWER−ON RESET AND STARTUP registers are not maintained in shutdown mode. Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified) chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.

Table 10. MIPI RFFE INTERFACE SPECIFICATION implemented as provision, are not described in this document. Table 11. MIPI RFFE ADDRESS MAP

  1. The details for configuration of Turbo mode should be ascertained from the Programming Guide, available from ON Semiconductor.
  2. The two least significant bits from Product ID register are programmed in OTP during manufacture. The other six bits of Produ ct ID are
  3. Manufacture ID is hardcoded in ASIC, and mapped in a READ−only register, not programmed in OTP.
  4. TCC−202 supports WRITE access to Product ID, only in respect to comply with MIPI RFFE specification 6.8.3, Programmable USID”, of

MIPI Alliance Specification for RF Front−End Control Interface (RFFE) Version 1.00.00 26 July 2011.

Table 12. REGISTER DETAILS The following are the details of the available RFFE registers:

  1. When any of the bits [3:2] are written with ‘0’, the corresponding DAC is disabled, but the Turbo−Charge process which is already started, will
  2. If all bits [3:2] are ‘0’, then incoming DAC messages will be ignored, until at least one of [3:1] is set ‘1’.

TCC−202 www.onsemi.com Register RFFE: RFFE_REG_0x13 Address RFFE A[4:0]: 0x13 Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits Reserved Reserved TCM_B TCM_A TCM [1:0] Turbo Multiplication Factor 00 (default) 4 01 3 10 2 11 1 Step [us] DAC state 0 1 2 3 4 5 6 7 8 9 10 11

9 TCDLY Turbo OFF 18 27 36 45 54 63 72 81 90 99

7 TCDLY Turbo OFF 14 21 28 35 42 49 56 63 70 77

5 (default) TCDLY Turbo OFF 10 15 20 25 30 35 40 45 50 55

3 TCDLY Turbo OFF 6 9 12 15 18 21 24 27 30 33

The value of Turbo time is deducted based on the hardware comparison of new DAC value in respect to old DAC value, as follows: If DAC new > DAC old, then TUP = TCDLY If DAC new < DAC old, and DAC new_divby2 < 21, then TDOWN = TCDLY + TCM * (21 – DAC_new_divby2) If DAC new < DAC old, and DAC new_divby2 > 21, then TDOWN = TCDLY If DAC new < DAC old, and DAC new_divby2 = 21, then TDOWN = TCDLY Register RFFE: RFFE_REG_0x9 Address RFFE A[4:0]: 0x09 Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits Reserved DAC_WAKEUP_CTRL Turbo Latency Select Reserved Reserved Bit [3]: DAC Wake−up Control applicable to Wake−up from LP 0 : (default) Don’t apply Turbo when Wake−up from LP STD or LP FTA 1: Always apply Turbo UP when Wake−up from LP STD or LP FTA. Turbo UP is calculated based on DAC value prior to enter LP STD or LP FTA mode. NOTE 1: Turbo is NOT applied after Wake−up to the DACs which are programmed with 0x00 in the DAC value register NOTE 2: Turbo is NOT applied after Wake−up from FTA mode if a trigger (Turbo, Normal, Glide) was generated while TC2x2 was in LP FTA mode NOTE 3: When Bit[3] = ‘1’, then Turbo is applied after Wake−up regardless if:

  • DAC values are updated or not
  • last DAC value update is equal with old DAC value NOTE 4: When RFFE_REG_0x31 / Wake−up DAC Ctrl is ‘0’ (default) Turbo after Wake−Up is applied after first vhv_too_lowfalling edge is detected. When RFFE_REG_0x31 / Wake−up DAC Ctrl is ‘1’ Turbo after Wake−up is applied after rc_clk starts. Bit [2]: Turbo UP latency Select when Wake−up from LP. This field has no effect when DAC_WAKEUP_CTRL[1:0] = ‘00’ 0: (default) Turbo UP latency is 50 /C0109s 1: Turbo UP latency is 100 /C0109s

TCC−202 www.onsemi.com Register RFFE: RFFE_REG_0x10 Address RFFE A[4:0]: 0x10 Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits Reserved Fixed Boost voltage value Reset U−0 U−0 U−0 U−1 W-1 W−0 W-1 W-1 Bit [3:0]: Boost voltage value Register RFFE: RFFE_STATUS_0x1A Address RFFE A[4:0]: 0x1A Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits SWR CFPE CLE AFPE DFPE RURE WURE BGE RFFE_STATUS register can be read any time after power−up without the need to enable the Read Operation as described below. SWR Soft−Reset MIPI−RFFE registers Write ‘1’ to this bit to reset all the MIPI−RFFE registers, except RFFE_REG_0x1C, RFFE_USID, and RFFE_GROUP_SID This bit will always Read−back ‘0’. The soft reset occurs in the last clock cycle of the MIPI−RFFE frame which Writes ‘1’ to this bit. Right immediately after this frame, all the MIPI−RFFE registers have the reset value and are ready to be reprogrammed as desired. The OTP duplicated registers are reset to the values written in OTP. SWR can be written only by USID messages. GSID and Broadcast frames will be ignored when writing to this register field. RFFE_STATUS Bits [6:0] are set ‘1’ by hardware to flag when a certain condition is detected, as described below. RFFE_STATUS Bits [6:0] cannot be written, but it is cleared to ‘0’ under following conditions:

  • Hardware Self−reset is applied after RFFE_STATUS is READ
  • When SWR is written ‘1’ with USID frames
  • When power mode transitions through STARTUP mode ‘01’
  • After Power−up Reset CFPE 1: Command frame with parity error received. On the occurrence of this error, the slave will ignore the entire Command Sequence CLE 1: Incompatible command length, due to unexpected SSC received before command length to be completed. On the occurrence of this error, the slave will accept Write data up to the last correct and complete frame. When MIPI−RFFE multi−byte Read command is detected, the slave will always replay with an extended Read command of length of one byte. AFPE 1: Address frame with parity error received. On the occurrence of this error, the slave will ignore the entire Command Sequence DFPE 1: Data frame with parity error received. On the occurrence of this error, the slave will ignore only the erroneous data byte (s) RURE 1: Read of non−existent register was detected. On the occurrence of this error, the slave will not respond to the Read command frame. When the Read Operation is not enabled ,any read from an address other than 0x1A, will set RURE and the slave will not respond to the Read command frame. When the Read Operation is enabled , any read from an unoccupied RFFE register address will set RURE. WURE 1: Write to non−existent register was detected. On the occurrence of this error, the slave discards data being written, and on the next received frame, proceeds as normal BGE 1: Read using the Broadcast ID was detected On the occurrence of this error, the slave will ignore the entire Command Sequence

TCC−202 www.onsemi.com Register RFFE: RFFE_GROUP_SID_0x1B Address RFFE A[4:0]: 0x1B Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits Reserved Reserved Reserved Reserved GSID[3] GSID[2] GSID[1] GSID[0] Reset 0 0 0 0 W−0 W−0 W−0 W−0 GSID = Group Slave Identifier Register NOTE: The GSID[3:0] field can be written directly by messages using USID. NOTE: GSID value is NOT retained during SHUTDOWN power mode. NOTE: GSID value is not affected by SWR bit from RFFE_STATUS register NOTE: Frames using USID = GSID, can write only to RFFE_REG_0x1C[7:6] and [2:0]. NOTE: RFFE READ frames containing GSID will be ignored Register RFFE: RFFE_REG_0x1C Address RFFE A[4:0]: 0x1C Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits Power Mode (Note 12) Trigger Mask 2 (Notes 8, 9, 10, 11) Trigger Mask 1 (Notes 8, 9, 10, 11) Trigger Mask 0 (Notes 8, 9, 10, 11) Trigger 2 Trigger 1 Trigger 0 8. Trigger Mask bits [5:3] can be changed, either set or cleared, only with an individual message using USID 9. During broadcast MIPI−RFFE accesses using GSID = ‘0000’, Trigger bits [2:0] are masked by the pre−existent setting of Trigger Mask Bits [5:3] 10.During Individual MIPI−RFFE accesses using USID, Trigger bits [2:0] are masked by the incoming Trigger Mask bits [5:3] within the same write message to RFFE_REG_0x1C register. During Individual MIPI−RFFE accesses using USID, pre−existent setting of Trigger Mask Bits [5:3] is ignored. 11. When RFFE_REG_0x1C/ Trigger_Mask_2 = ‘1’ and Trigger_Mask_1 = ‘1’ and Trigger_Mask_0 = ‘1’, then DAC messages will be sent to DACs immediately after RFFE_REG_0x04 is received, without waiting for any trigger 12.Power mode field bits [7:6] and Triggers bits [2:0] can be changed by either MIPI−RFFE broadcast messages when USID field within the Register Write Command is 0x0 , or individual messages when US ID fields within the Register Write Command is equal with RFFE_REG_0x1F[3:0] NOTE: All the 8 bits of RFFE_REG_0x1C register bits are NOTaffected by SWR bit from RFFE_STATUS register Bit [7:6]: Power Mode 00: ACTIVE mode, defined by following hardware behavior:

  • Boost Control active, VHV set by Digital Interface
  • V out A and B enabled and controlled by Digital Interface 01: STARTUP mode, defined by following hardware behavior: o
  • Boost Control active, VHV set by Digital Interface
  • V out A and B disabled 10: LOW POWER mode is defined by following hardware behavior:
  • Digital interface is active, while all other circuits are in lowpower mode 11: Reserved (State of hardware does not change) Bit 5: Mask trigger 2 0:Trigger 2 not masked. Data goes to destination register after bit 2 is written value 1 (default) 1:Trigger 2 is masked. Data goes directly to the destination register Bit 4: Mask trigger 1 0:Trigger 1 not masked. Data goes to destination register after bit 1 is written value 1(default) 1:Trigger 1 is masked. Data goes directly to the destination register. Bit 3: Mask trigger 0 0:Trigger 0 not masked. Data goes to destination register after bit 0 is written value 1(default) 1:Trigger 0 is masked. Data goes directly to the destination register. Bit 2: Trigger 2 Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 5. Bit 1: Trigger 1 Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 4. Bit 0: Trigger 0 Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 3.

TCC−202 www.onsemi.com Register RFFE: RFFE_PRODUCT_ID_0x1D Address RFFE A[4:0]: 0x1D Reset Source: N/A 7 6 5 4 3 2 1 0 Bits PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 (1) Reset 0 0 1 0 0 0 0 OTP[4] Bits [7:1] are hardcoded in ASIC Bits [0] can be programmed in OTP during manufacturing Register RFFE: RFFE_MANUFACTURER_ID_0x1E Address RFFE A[4:0]: 0x1E Reset Source: N/A 7 6 5 4 3 2 1 0 Bits MPN7 MPN6 MPN5 MPN4 MPN3 MPN2 MPN1 MPN0 Reset 0 0 1 0 1 1 1 0 Register RFFE: RFFE_USID_0x1F Address RFFE A[4:0]: 0x1F Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode) 7 6 5 4 3 2 1 0 Bits Reserved (2) MPN9 (2) MPN8 (2) USID3 (1) USID2 (1) USID1 (1) USID0 (1) Reset 0 0 0 1 W−0 W−1 W−1 W−1 USID = Unique Slave Identifier Register 1. USID field can be changed by:

  • MIPI−RFFE broadcast messages when USID field within the Register Write Command is 0b0000
  • MIPI−RFFE individual messages when USID field within the Register Write Command equal with content of RFFE_REG_0x1F[3:0] 2. In the sequence of writing USID field, the upper [7:4] must match the value 0b0001 hardcoded in the RFFE register 0x1F NOTE: USID value is NOT retained during SHUTDOWN power mode. NOTE: USID value is not affected by SWR bit from RFFE_STATUS register.

Table 15. OTHER RFFE COMMAND SEQUENCES byte and a value of 0b1111 would write sixteen bytes. starting from the address indicated in the Address Frame. Figure 14. Extended Register Write Command Sequence

Table 16. RFFE COMMAND FRAME for Extended Register Write Command Sequence for DACs Loading Procedure Read command sequence is not supported. Table 17. DAC CONFIGURATION (ENABLE MASK) at [0x00] Defaults shown as (x) nominally 2 MHz and spread between 0.8 MHz and 3.2 MHz when enabled (default). Table 18. DAC MODE SETUP: DAC ENABLE Table 19. BOOST DAC MODE SETUP (VHV) at [0x10] (Notes 13, 14) 14.VHV is recommended to be set at VDac Max + 2V for non−turbo operation and + 4V when turbo is used.

Table 20. POWER MODE BIT SETTING IN REGISTER [0X1C] Table 21. EXTENDED REGISTER WRITE TO UPDATE DAC A, B Figure 15. Register Read Command Sequence Table 22. REGISTER READ COMMAND

0 CFPE CLE AFPE DFPE RURE WURE BGE BP

Figure 16. TCC−202 with External Components Table 23. RECOMMENDED EXTERNAL BOM NSR0340P2T5G devices may also be used. Table 24. ORDERING INFORMATION Specifications Brochure, BRD8011/D.

TCC−202 www.onsemi.com PACKAGE DIMENSIONS WLCSP12, 1.28x1.684 CASE 567KZ ISSUE A SEATING PLANE 0.08 C

0.10 C A1

A 0.25 12X DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.40 RECOMMENDED A1 PACKAGE OUTLINE PITCH 0.40 PITCH

0.05 C2X

ÈÈ ÈÈ E D A B PIN A1 REFERENCE

0.05 C2X TOP VIEW

e A0.05 BC 0.03 C 12X b C B A BOTTOM VIEW 123 e/2 e NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. DIM A MIN MAX −−− MILLIMETERS D 1.28 BSC E b 0.23 0.29 e 0.40 BSC 0.65 0.17 0.23

1.684 BSC

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