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© Semiconductor Components Industries, LLC, 2015 September, 2015 − Rev. 5

1 Publication Order Number:

TCC−106/D TCC-106 Six-Output PTIC Control IC Introduction ON Semiconductor’s PTIC Controller IC is a six−output high−voltage digital to analog control IC specifically designed to control and bias ON Semiconductor’s Passive Tunable Integrated Circuits (PTICs). These tunable capacitive circuits are intended for use in mobile phones and dedicated RF tuning applications. The implementation of ON Semiconductor’s tunable circu its in mobile phones enables significant improvement in terms of antenna radiated performance. The tunable capacitors are controlled through a bias voltage ranging from 2 V to 20 V . The TCC−106 high−voltage PTIC control IC has been specifically designed to cover this need, providing six independent high−voltage outputs that control up to six different tunable PTICs in parallel. The device is fully controlled through a multi−protocol digital interface. Key Features

  • Controls ON Semiconductor’s PTIC Tunable Capacitors
  • Compliant with Timing Needs of Cellular and Other Wireless System Requirements
  • Integrated Boost Converter with 6 Programmable Outputs (up to 24 V)
  • Low Power Consumption
  • Auto−detection of SPI (30− or 32−bit) or MIPI RFFE Interfaces (1.2 V or 1.8 V)
  • Available in WLCSP (RDL ball arrays) and for Stand−alone or Module Integration
  • This is a Pb−Free Device Typical Applications
  • Multi−band, Multi−standard, Advanced and Simple Mobile Phones
  • Tunable Antenna Matching Networks
  • Compatible with Closed−loop and Open−loop Antenna Tuner

Applications

www.onsemi.com See detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet.

ORDERING INFORMATION

TC6 = Product Code x = MIPI ID A = Assembly Location L = Wafer Lot Code Y = Year Code W = Week Code O = Pin 1 Marker

Figure 1. Control IC Functional Block Diagram

Table 1. PAD DESCRIPTIONS

1 L_BOOST AOH Boost Inductor 25 B4

3 GNDA P Analog Ground 0 C3

4 TRIG DIO Trigger Signal Input (Note 2) VIO C4

5 CLK DI MIPI RFFE / SPI Clock VIO D4

6 CS DI Chip Select for SPI VIO D3

7 DATA DIO Digital IO (SPI and MIPI RFFE) VIO E4

8 VIO P Digital IO Supply 3 E3

9 IDB0 DI MIPI RFFE ID Bit 0 (Note 3) VIO C2

10 GNDIO P Digital IO Ground VIO D2

11 OUTA AOH High Voltage Output A VHV E2

12 OUTB AOH High Voltage Output B VHV E1

13 OUTC AOH High Voltage Output C VHV D1

14 OUTD AOH High Voltage Output D VHV C1

15 OUTE AOH High Voltage Output E VHV B1

16 OUTF AOH High Voltage Output F VHV A1

17 ATEST AO Analog Test Out (Note 4) VREG B2

19 GND_BOOST P Ground for Booster 0 A3

20 VHV AOH / AIH Boost High Voltage can be Forced Externally 25 A4

  1. To be grounded when not in use.
  2. This pin has to be connected to either GNDIO or VIO level, even if only SPI protocol is used. Never let it float.
  3. To be grounded in normal operation.

Table 2. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

Table 3. RECOMENDED OPERATING CONDITIONS

0 V steady state

2 V steady state

16 V steady state

Table 5. BOOST CONVERTER CHARACTERISTICS Table 6. ANALOG OUTPUTS (OUT A, OUT B, OUT C)

D, DAC E and DAC F) through the digital interface. Control IC Functional Block Diagram).

24 V , with 128 steps of 188 mV (2 V x 24 V / 255 V =

approximated to 188 mV x (DAC value). startup default level for the boosted voltage is VHV = 24 V . OUT voltage of any of the six outputs. GND through an effective impedance of less than 800 ohms.

  1. Shutdown Mode: All circuit blocks are off, the

the registers are not maintained in shutdown mode.

  1. Startup Mode: Startup is only a transitory mode.

and the DAC outputs are placed in a high Z state. the device automatically proceeds to the active mode.

  1. Active Mode: All blocks of the TCC−106 are

automatically entered from the startup mode. power mode under control software command.

  1. Low Power Mode: In low power mode the serial

registers are maintained in the low power mode. Figure 2. Modes of Operation

only minimal leakage current. enable the POR to trigger again. Table 7. VIO POWER−ON RESET AND STARTUP registers are not maintained in shutdown mode. Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified) chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.

Table 10. 3−WIRE SERIAL INTERFACE SPECIFICATION

Figure 8. 3−wire Serial Interface Signal Timing 30−bit or 32−bit frame length is automatically detected. exactly 30 bits or 32 bits. SPI registers are write only. Table 11. 32 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS) Table 12. 30 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS) Table 13. 3−WIRE SERIAL INTERFACE ADDRESS MAP

Table 14. MIPI RFFE INTERFACE SPECIFICATION

implemented as provision, are not described in this document. Table 15. MIPI RFFE ADDRESS MAP Table 16. DAC CONFIGURATION (ENABLE MASK) at [0x00] Defaults shown as (x) no restrictions exist as to which three.

Table 17. DAC MODE SETUP: DAC ENABLE Table 18. DAC MODE SETUP: DAC ENABLE Table 19. BOOST DAC MODE SETUP (VHV) at [0x10] (Note 5)

  1. Bit 4 is fixed at logic 1 for reverse software compatibility

will be applied to the outputs. external TRIG pin to be used as a synchronization signal. programmable via [0x11] bit 1.

  • The requested DAC voltage levels for DAC A, B, C are applied to the outputs all together at the same time, after DAC C value is written. This event will not affect the outputs of DAC D, E, F.
  • The requested DAC voltage levels for DAC D, E, F are applied to the outputs all together at the same time, after DAC F value is written. This event will not affect the outputs of DAC A, B, C.
  • Optionally a configuration register can select the last DAC to be written in order to trigger internally the update of all six DACs at the same time. For example the configuration register can select that a write to DAC B value will trigger internally the update of all six DACs outputs.

Table 20. TRIGGER CONFIGURATION at [0x11] Table 21. EXTERNAL TRIGGER CONFIGURATION BIT SETTING AT [0x11] gisters loaded with the new voltage settings which are then applied to the outputs. Table 22. POWER MODE AND TRIGGER REGISTER [0x1C] destination registers. Default for bit 0, 1 and 2 is logic low. destination register. Default for bit 3, 4 and 5 is logic low.

Table 23. POWER MODE BIT SETTING IN REGISTER [0x1C]

  • Register 0 Write (used to access the Register 0 DAC Configuration − Enable Mask). Register 0 can be also be accessed using Register Write or/and Extended Register Write.
  • Register Write (used to access only one register at the time)
  • Extended Register Write (used to access a group of contiguous registers with one command) Register 0 Write Command Sequence The Command Sequence starts with a Sequence Start Condition (SSC) which is followed by the Register 0 Write Command Frame. This Frame contains the Slave address, a logic one, and the seven bit word that will be written to Register 0. The Command Sequence is depicted below.

Figure 12. Register 0 Write Command Sequence Table 24. MIPI RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE

The write register command sequence may be used to access each register (addresses 0−31). Figure 13. Register Write Command Sequence Table 25. MIPI RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SENTENCE Table 26. MIPI RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SENTENCE

byte and a value of 0b1111 would write 16 bytes. starting from the address indicated in the address frame. Figure 14. Extended Register Write Command Sequence

Table 27. EXTENDED REGISTER WRITE TO UPDATE DAC A, B, C (Note 6) Table 28. EXTENDED REGISTER WRITE TO UPDATE DAC D, E, F (Note 6)

  1. The six DACs can be updated either all together in the same time by using one Extended Register Write command of 8 bytes, or separately

Figure 15. Register Read Command Sequence Table 29. REGISTER READ COMMAND

0 CFPE CLE AFPE DFPE RURE WURE BGE BP

Figure 16. TCC−106 with External Components Table 30. RECOMMENDED EXTERNAL BOM

  1. Recommended for noise reduction only – not essential

Figure 17. Ball Array Package − Top View

  • = Pin 1 Marker a=0 b=1 MIPI RFFE ID Bit 1 2250 /C0109m ±10 /C0109m 2600 /C0109m ±10 /C0109m TC6x 7LYW A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 E1 E2 E3 E4 580 /C0109m380 /C0109m ±25 /C0109m 200 /C0109m ±20 /C0109m 400 /C0109m NOTE: Die dimensions include an assumed 60 /C0109m wide sawing kerf, this kerf width is subject to change without notice.

Figure 18. WLCSP Carrier Tape Drawings Table 31. ORDERING INFORMATION Specifications Brochure, BRD8011/D.

TCC−106 www.onsemi.com PACKAGE DIMENSIONS WLCSP20, 2.58x2.23 CASE 567HL ISSUE O SEATING PLANE 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A MIN MAX −−− MILLIMETERS D 2.58 BSC E b 0.23 0.29 e 0.40 BSC 0.65 È È E D A B PIN A1 REFERENCE e A0.05 BC 0.03 C 0.08 C 20X b C B A

0.10 C A1

A C 0.18 0.22

2.23 BSC

0.25 20X DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.40 0.40

0.05 C2X TOP VIEW

e A3 0.38 REF RECOMMENDED PACKAGE OUTLINE 123 PITCH D E PITCH e/2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a numb er of patents, trademarks, reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 TCC−106/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative