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Technical content
Features
- Controls ON Semiconductor’s PTIC Tunable Capacitors and RF Tuners
- Compliant with Timing Needs of Cellular and Other Wireless System Requirements
- Integrated Boost Converter with 3 Programmable Outputs (Up To 24 V)
- Low Power Consumption
- Auto-detection of SPI (30- or 32-bit) or MIPI RFFE Interfaces (1.2 V or 1.8 V)
- Available in WLCSP (Ball and Peripheral Arrays) and for Stand-alone or Module Integration Typical Applications
- Multi-band, Multi-standard, Advanced and Simple Mobile Phones
- Tunable Antenna Matching Networks
- Compatible with Closed Loop and Open-loop Antenna Tuner
Applications
http://onsemi.com Peripheral Bump CASE TBD See detailed ordering and shipping information in the package dimensions section on page 29 of this data sheet.
ORDERING INFORMATION
TCC = Product Code X = MIPI ID A = Assembly Location L = Wafer Lot Code Y = Year Code W = Week Code O = Pin 1 Marker Peripheral Bump RDL TCCX ALYW TCCx ALYW TCC = Product Code x = MIPI ID A = Assembly Location L = Wafer Lot Code Y = Year Code W = Week Code O = Pin 1 Marker
4 BIT
7 BIT
Figure 1. HVDAC Functional Block Diagram
Table 1. PIN FUNCTION DESCRIPTIONS
1 L_BOOST Analog HV Output Boost Inductor
2 AVDD Power Analog Supply
3 GND_REF Power Analog Ground
4 TRIG Digital I/O Trigger Signal Input
5 CS Digital Input SPI_CS (Ground for MIPI RFFE)
6 CLK Digital Input RFFE SCLK/SPI CLK
7 DATA Digital I/O RFFE SDATA/SPI_DATA
8 VIO Power IO Reference Supply
9 GND_DIG Power Digital Ground
10 OUTA Analog HV Output High Voltage Output A
11 OUTB Analog HV Output High Voltage Output B
12 OUTC Analog HV Output High Voltage Output C
13 VREG Analog Output VREG Capacitor
14 ATEST Analog Output Test Pin (Ground in Application)
15 GND_BOOST Power Boost Ground
16 VHV Analog HV I/O Boost High Voltage Output
Figure 2. Peripheral Row Footprint − Top View
Table 2. PIN FUNCTION DESCRIPTIONS Figure 3. Ball Array Footprint − Top View
Table 3. ABSOLUTE MAXIMUM RATINGS Table 4. RECOMMENDED OPERATING CONDITIONS Table 5. DC CHARACTERISTICS
Table 5. DC CHARACTERISTICS (continued) Table 6. BOOST CONVERTER CHARACTERISTICS
Table 7. ANALOG OUTPUTS (OUT A, OUT B, OUT C)
DACs used in a 7-bit format. startup default level for the boosted voltage is VHV = 20 V . OUT voltage of any of the three outputs. GND through an effective impedance of less than 800 /C0087.
- Shutdown Mode: All circuit blocks are off, the
the registers are not maintained in shutdown mode.
- Startup Mode: Startup is only a transitory mode.
mode or the low power mode to the startup mode. proceeds to the Active mode.
- Active Mode: All blocks of the TCC−103 are
under control software command.
- Low Power Mode: In low power mode the serial
registers are maintained in the low power mode. only minimal leakage current. Table 8. VIO POR also resets the serial interface circuitry. Table 8. VIO POWER-ON RESET AND STARTUP
Table 9. VIO THRESHOLDS chip is reset and placed into the Shutdown state. a command via the serial interface. Table 10. TIMING Figure 4. Output Setting Diagram
Figure 5. Startup Timing Diagram
latched on the falling edge of CS. Table 11. 3-WIRE SERIAL INTERFACE SPECIFICATION
Figure 9. 3-wire Serial Interface Signal Timing 30-bit or 32-bit frame length is automatically detected. exactly 30 bits or 32 bits. SPI registers are write only. Table 12. 32 BITS FRAME: ADDRESS DECODING (1 OR 2 OR 3 OUTPUTS) Table 13. 30 BITS FRAME: ADDRESS DECODING (1 OR 2 OR 3 OUTPUTS) Table 14. 3-WIRE SERIAL INTERFACE ADDRESS MAP
set to 24 V when using Turbo-Charge mode. Table 15. DATA DECODING FOR DATA REGISTER [00000] Table 16. DATA DECODING FOR DATA REGISTER [00001] Table 17. FIRST AND LAST 26 VALUES OF TURBO TIME ENCODED TABLE INTO
corresponding delay from Table 18. Table 18. TUNING TCDLY STEPS [/C0109S]
5 Turbo OFF 5 10 15 20 25 30 35 40 45 50 55
4 Turbo OFF 4 8 12 16 20 24 28 32 36 40 44
3 Turbo OFF 3 6 9 12 15 18 21 24 27 30 33
2 Turbo OFF 2 4 6 8 10 12 14 16 18 20 22
Table 19. TURBO-CHARGE DELAY PARAMETERS REGISTER FOR A, B & C [00100] Table 20. TURBO-CHARGE MULTIPLICATION Table 21. TURBO-CHARGE DELAY STEP SETTINGS available through register shown in Table 21. Table 22. DATA DECODING FOR DATA REGISTER [10000] sent to data registers 0x00000 and 0x00001. Table 23. DATA DECODING FOR DATA REGISTER
Table 24. BOOST DAC MODE SETUP Table 25. POWER MODE SETUP Register [10000], bit D13 (TE, Trigger Enable). for TP is low-to-high transition of the TRIG signal. and are not synchronized with the TRIG signal. Table 26. DAC MODE SETUP: DAC ENABLE *If all bits [3:1] are ‘0’, then incoming DAC messages will be ignored until at least one of [3:1] is set ‘1’.
RFFE interface the CS pin is grounded. Table 27. MIPI RFFE INTERFACE SPECIFICATION
The HVDAC contains twenty-four 8 bit registers. Table 28. MIPI RFFE ADDRESS MAP *The two least significant bits are programmed in OTP during manufacture.
Table 29. DAC CONFIGURATION (ENABLE MASK) AT [0x00] Table 30. BOOST DAC MODE SETUP (VHV) AT [0x10] (Note 1)
- Bit 4 is fixed at logic 1 for reverse SW compatibility.
will be applied to the outputs. external TRIG pin to be used as a synchronization signal. programmable via [0x11] bit 1.
Table 31. TRIGGER CONFIGURATION AT [0x11] Table 32. EXTERNAL TRIGGER CONFIGURATION BIT SETTINGS AT [0x11] with the new voltage settings which are then applied to the outputs. − − − 0 − External TRIG Pin Signal Is Active Falling. Table 33. POWER MODE AND TRIGGER REGISTER [0x1C] destination registers. Default for bit 0, 1 & 2 is logic low. destination register. Default for bit 3, 4 & 5 is logic low. Table 34. POWER MODE BIT SETTINGS IN REGISTER [0x1C] Table 35. PRODUCT_ID REGISTER AT [0x1D] *Programmed in OTP during manufacture (4 combinations of Product ID possible). Table 36. MANUFACTURER_ID REGISTER AT [0x1E] Table 37. SPARE(1:0), MANUFACTURER_ID(9:8), USID(3:0) REGISTER AT [0x1F] *Changes to the USID are not retained during SHUTDOWN power mode.
Table 38. TURBO-CHARGE DAC A, B & C REGISTER [0x01] Table 39. DAC A REGISTER [0x02] Table 40. DAC B REGISTER [0x03] Table 41. DAC C REGISTER [0x04] Table 42. TURBO-CHARGE DELAY STEPS [0x12] NOTE: TC_STP_DAC_X is defined in the Table 21. Table 43. TURBO-CHARGE DELAY MULTIPLICATION [0x13] NOTE: TCM_X is defined in the Table 20 .
byte and a value of 0b1111 would write sixteen bytes. starting from the address indicated in the Address Frame. Figure 12. Extended Register Write Command Sequence Table 46. EXTENDED REGISTER WRITE
Figure 13. Recommended MIPI RFFE Interface Application Schematic
Figure 14. Recommended 3-wire Serial Interface Application Schematic Table 47. RECOMMENDED EXTERNAL BOM
Figure 17. WLCSP Carrier Tape Drawings
Table 48. ORDERING INFORMATION Specifications Brochure, BRD8011/D. of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.