TCAN1042GDRBRQ1

TCAN1042-Q1_17 TI1 | Alldatasheet

Document overview

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Technical content

Copyright © 2016, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 TCAN1042-Q1AutomotiveFaultProtectedCANTransceiverwithCANFD

1 Features

1• AEC Q100: Qualified for Automotive Applications – Device Temperature Grade 1: -40°C to 125°C Ambient Operating Temperature – Device HBM Classification Level: ±16 kV – Device CDM Classification Level ±1500 V

• Meets the ISO 11898-2:2016 and ISO 11898-5:2007 Physical Layer Standards
• 'Turbo' CAN: – All Devices Support Classic CAN and 2 Mbps CAN FD (Flexible Data Rate) and "G" Options Support 5 Mbps – Short and Symmetrical Propagation Delay Times and Fast Loop Times for Enhanced Timing Margin – Higher Data Rates in Loaded CAN Networks
• I/O Voltage Range Supports 3.3 V and 5 V MCUs
• Ideal Passive Behavior When Unpowered – Bus and Logic Terminals are High Impedance (no load) – Power Up/Down With Glitch Free Operation On Bus and RXD Output
• Protection Features – IEC ESD Protection up to ±15 kV – Bus Fault Protection: ±58 V (non-H variants) and ±70 V (H variants) – Undervoltage Protection on VCC and VIO (V variants only) Supply Terminals – Driver Dominant Time Out (TXD DTO) - Data rates down to 10 kbps – Thermal Shutdown Protection (TSD)
• Receiver Common Mode Input Voltage: ±30 V
• Typical Loop Delay: 110 ns
• Junction Temperatures from –55°C to 150°C
• Available in SOIC(8) Package and Leadless VSON(8) Package (3.0 mm x 3.0 mm) with Improved Automated Optical Inspection (AOI) Capability

2 Applications

• Automotive and Transportation
• All devices support highly loaded CAN networks
• Heavy Machinery ISOBUS Applications – ISO 11783
• SAE J2284 High-Speed CAN for Automotive

Applications

• GMW3122 Dual-Wire CAN Physical Layer
• Meets requirements of SAE J2962, GIFT/ICT, ISO16845

3 Description

This CAN transceiver family meets the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. All devices are designed for use in CAN FD networks up to 2 Mbps (megabits per second). Devices with part numbers that include the "G" suffix are designed for data rates up to 5 Mbps, and versions with the "V" have a secondary power supply input for I/O level shifting the input pin thresholds and RXD output level. This family has a low power standby mode with remote wake request feature. Additionally, all devices include many protection features to enhance device and network robustness. Device Information ORDER NUMBER PACKAGE BODY SIZE TCAN1042x-Q1 SOIC (8) 4.90 mm × 3.91 mm VSON (8) 3.00 mm x 3.00 mm Functional Block Diagram A. Terminal 5 function is device dependent; NC on devices without the "V" suffix, and VIO for I/O level shifting for devices with the "V" suffix. B. RXD logic output is driven to VCC on devices without the "V" suffix, and VIO for devices with the "V" suffix.

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Table of Contents

13.2 Receiving Notification of Documentation Updates 30

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2016) to Revision B Page

• Changed Feature "Meets the Released ISO 11898-2:2007 and ISO 11898-2:2003 Physical Layer Standards" To:
• Changed Feature From: "All devices support 2 Mbps CAN FD.." To: "All Devices Support Classic CAN and 2 Mbps
• Changed Feature From: "EMC: SAE J2962, GIFT/ICT, ISO 16845" To: "Meets requirements of SAE J2962,
• Deleted "VI = 0.4 sin (4E6 π t) + 2.5 V" from the Test Condition of CI in the RECEIVER ELECTRICAL
• Deleted "VI = 0.4 sin (4E6 π t)" from the Test Condition of CID in the RECEIVER ELECTRICAL CHARACTERISTICS
• Added "-30 V ≤ VCM ≤ +30" to the Test Condition of RID and RIN in the RECEIVER ELECTRICAL

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated Revision History (continued) Changes from Original (March 2016) to Revision A Page

• Changed Feature From: Meets the Requirements of ISO11898-2 (2016) To: Meets the December 17th, 2015 Draft

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

5 Device Comparison Table

NUMBER BUS FAULT PROTECTION 5-Mbps FLEXIBLE DATA RATE 3-V LEVEL SHIFTER INTEGRATED PIN 8 MODE SELECTION TCAN1042-Q1 (Base) ±58 V Low Power Standby Mode with Remote Wake TCAN1042G-Q1 ±58 V X TCAN1042GV-Q1 ±58 V X X TCAN1042V-Q1 ±58 V X TCAN1042H-Q1 ±70 V TCAN1042HG-Q1 ±70 V X TCAN1042HGV-Q1 ±70 V X X TCAN1042HV-Q1 ±70 V X

6 Pin Configurations and Functions

D Package for Base, (H), (G) and (HG) Devices

8 PIN (SOIC)

8 PIN (VSON)

D Package for (V), (HV), (GV), and (HGV) Devices NAME Base, (H), (G), (HG) (V), (GV), (HV), (HGV) TXD 1 1 DIGITAL INPUT CAN transmit data input (LOW for dominant and HIGH for recessive bus states) GND 2 2 GND Ground connection VCC 3 3 POWER Transceiver 5-V supply voltage RXD 4 4 DIGITAL OUTPUT CAN receive data output (LOW for dominant and HIGH for recessive bus states) NC 5 — — No Connect VIO — 5 POWER Transceiver I/O level shifting supply voltage (Devices with "V" suffix only) CANL 6 6 BUS I/O Low level CAN bus input/output line CANH 7 7 BUS I/O High level CAN bus lnput/output line STB 8 8 DIGITAL INPUT Standby Mode control input (active high)

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

7 Specifications

7.1 Absolute Maximum Ratings(1) (2)

VCC 5-V bus supply voltage range –0.3 7 V VIO I/O Level Shifting Voltage Range Devices with the "V" suffix –0.3 7 V VBUS CAN Bus I/O voltage range (CANH, CANL) Devices without the "H" suffix –58 58 V V(Diff) Max differential voltage between CANH and CANL Devices without the “H”suffix –58 58 V VBUS CAN Bus I/O voltage range (CANH, CANL) Devices with the "H" suffix –70 70 V V(Diff) Max differential voltage between CANH and CANL Devices with the “H”suffix –70 70 V V(Logic_Input) Logic input terminal voltage range (TXD, STB) –0.3 7 and VI ≤ VIO + 0.3 V V(Logic_Output) Logic output terminal voltage range (RXD) –0.3 7 and VI ≤ VIO + 0.3 V IO(RXD) RXD (Receiver) output current –8 8 mA TJ Virtual junction temperature range (see Thermal Information) –55 150 °C TSTG Storage temperature range (see Thermal Information) –65 150 °C (1) Tested in accordance to JEDEC Standard 22, Test Method A114. (2) Test method based upon JEDEC Standard 22 Test Method A114, CAN bus is stressed with respect to GND. (3) Tested in accordance to JEDEC Standard 22, Test Method C101. (4) Tested in accordance to JEDEC Standard 22, Test Method A115. (5) ISO7637 is a system level transient test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions. Different system level configurations may lead to different results.

7.2 ESD Ratings

TEST CONDITIONS VALUE UNIT D (SOIC) Package Human Body Model (HBM) ESD stress voltage All terminals(1) ±6000 V CAN bus terminals (CANH, CANL) to GND(2) ±16000 Charged Device Model (CDM) ESD stress voltage All terminals(3) ±1500 V Machine Model (MM) All terminals(4) ±200 System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND SAE J2962-2 per ISO 10605: Powered Air Discharge ±15000 V SAE J2962-2 per ISO 10605: Powered Contact Discharge ±8000 System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-2: Unpowered Contact Discharge ±15000 V IEC 61000-4-2: Powered on Contact Discharge ±8000 System Level Electrical fast transient (EFT) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-4: Criteria A ±4000 V ISO7637-2 Transients according to GIFT - ICT CAN EMC test specification(5) CAN bus terminals (CANH, CANL) to GND Pulse 1 –100 V Pulse 2 +75 Pulse 3a –150 Pulse 3b +100 ISO7637-3 Transients CAN bus terminals (CANH, CANL) to GND Direct Coupling Capacitor "Slow Transient Pulse" with 100 nF coupling capacitor - Powered ±85 DRB (VSON) Package Human Body Model (HBM) ESD stress voltage All terminals(1) ±6000 V CAN bus terminals (CANH, CANL) to GND(2) ±16000 Charged Device Model (CDM) ESD stress voltage All terminals(3) ±1500 V Machine Model (MM) All terminals(4) ±200

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated ESD Ratings (continued) TEST CONDITIONS VALUE UNIT System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND SAE J2962-2 per ISO 10605: Powered Air Discharge ±15000 V SAE J2962-2 per ISO 10605: Powered Contact Discharge ±8000 System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-2: Unpowered Contact Discharge ±14000 V IEC 61000-4-2: Powered on Contact Discharge ±8000 System Level Electrical fast transient (EFT) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-4: Criteria A ±4000 V ISO7637-2 Transients according to GIFT - ICT CAN EMC test specification(5) CAN bus terminals (CANH, CANL) to GND Pulse 1 –100 V Pulse 2 +75 Pulse 3a –150 Pulse 3b +100 ISO7637-3 Transients CAN bus terminals (CANH, CANL) to GND Direct Coupling Capacitor "Slow Transient Pulse" with 100 nF coupling capacitor - Powered ±85

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

7.3 Recommended Operating Conditions

VCC 5-V Bus Supply Voltage Range 4.5 5.5 V VIO I/O Level-Shifting Voltage Range 3 5.5 IOH(RXD) RXD terminal HIGH level output current –2 mA IOL(RXD) RXD terminal LOW level output current 2 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.4 Thermal Information

THERMAL METRIC(1) TEST CONDITIONS TCAN1042-Q1 UNITD (SOIC) DRB (VSON)

8 Pins 8 Pins

RθJA Junction-to-air thermal resistance High-K thermal resistance(2) 105.8 40.2 °C/W RθJB Junction-to-board thermal resistance(3) 46.8 49.7 °C/W RθJC(TOP) Junction-to-case (top) thermal resistance(4) 48.3 15.7 °C/W ΨJT Junction-to-top characterization parameter(5) 8.7 0.6 °C/W ΨJB Junction-to-board characterization parameter(6) 46.2 15.9 °C/W TTSD Thermal shutdown temperature 170 170 °C TTSD_HYS Thermal shutdown hysteresis 5 5 °C

7.5 Power Rating

PARAMETER TEST CONDITIONS POWER DISSIPATION UNIT PD Average power dissipation VCC = 5 V, VIO = 5 V (if applicable), TJ = 27°C, RL = 60 Ω, S at 0 V, Input to TXD at 250 kHz, CL_RXD = 15 pF. Typical CAN operating conditions at 500 kbps with 25% transmission (dominant) rate. 52 mW VCC = 5.5 V, VIO = 5.5 V (if applicable), TJ = 150°C, RL = 50 Ω, S at 0 V, Input to TXD at 500 kHz, CL_RXD = 15 pF. Typical high load CAN operating conditions at 1 Mbps with 50% transmission (dominant) rate and loaded network. 124 mW

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω.

7.6 Electrical Characteristics

Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT SUPPLY CHARACTERISTICS ICC 5-V supply current Normal mode (dominant) See Figure 5, TXD = 0 V, RL = 60 Ω, CL = open, RCM = open, STB = 0 V, Typical Bus Load 40 70 mA See Figure 5, TXD = 0 V, RL = 50 Ω, CL = open, RCM = open, STB = 0 V, High Bus Load 45 80 Normal mode (dominant – with bus fault) See Figure 5, TXD = 0 V, STB = 0 V, CANH = -12 V, RL = open, CL = open, RCM = open 180 Normal mode (recessive) See Figure 5, TXD = VCC or VIO, RL = 50 Ω, CL = open, RCM = open, STB = 0 V 1.5 2.5 Standby mode Devices with the "V" suffix (I/O level- shifting), VCC not needed in Standby mode, See Figure 5, TXD = VIO, RL = 50 Ω, CL = open, RCM = open, STB = VIO 0.5 5 µADevices without the "V" suffix (5-V only), See Figure 5, TXD = VCC, RL = 50 Ω, CL = open, RCM = open, STB = VCC IIO I/O supply current Normal mode RXD floating, TXD = STB = 0 or 5.5 V 90 300 Standby mode RXD floating, TXD = STB = VIO, VCC = 0 or 5.5 V 12 17 UVVCC Rising undervoltage detection on VCC for protected mode All devices 4.2 4.4 V Falling undervoltage detection on VCC for protected mode 3.8 4.0 4.25 VHYS(UVVCC) Hysteresis voltage on UVVCC 200 mV UVVIO Undervoltage detection on VIO for protected mode Devices with the "V" suffix (I/O level-shifting) 1.3 2.75 V VHYS(UVVIO) Hysteresis voltage on UVVIO for protected mode 80 mV STB TERMINAL (MODE SELECT INPUT) VIH High-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.7 x VIO V Devices without the "V" suffix (5-V only) 2 VIL Low-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.3 x VIO Devices without the "V" suffix (5-V only) 0.8 IIH High-level input leakage current STB = VCC = VIO = 5.5 V -2 2 µAIIL Low-level input leakage current STB = 0V, VCC = VIO = 5.5 V –20 0 -2 Ilkg(OFF) Unpowered leakage current STB = 5.5 V, VCC = VIO = 0 V -1 0 1 TXD TERMINAL (CAN TRANSMIT DATA INPUT) VIH High-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.7 x VIO V Devices without the "V" suffix (5-V only) 2 VIL Low-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.3 x VIO Devices without the "V" suffix (5-V only) 0.8 IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1 µAIIL Low-level input leakage current TXD = 0 V, VCC = VIO = 5.5 V –100 -25 –7 Ilkg(OFF) Unpowered leakage current TXD = 5.5 V, VCC = VIO = 0 V –1 0 1 CI Input capacitance VIN = 0.4 x sin(2 x π x 2 x 106 x t) + 2.5 V 5 pF

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT RXD TERMINAL (CAN RECEIVE DATA OUTPUT) VOH High-level output voltage Devices with the "V" suffix (I/O level- shifting), See Figure 6, IO = –2 mA. 0.8 × VIO V Devices without the "V" suffix (5V only), See Figure 6, IO = –2 mA. 4 4.6 VOL Low-level output voltage Devices with the "V" suffix (I/O level- shifting), See Figure 6, IO = +2 mA. 0.2 x VIO Devices without the "V" suffix (5-V only), See Figure 6, IO = +2 mA. 0.2 0.4 Ilkg(OFF) Unpowered leakage current RXD = 5.5 V, VCC = 0 V, VIO = 0 V –1 0 1 µA DRIVER ELECTRICAL CHARACTERISTICS VO(DOM) Bus output voltage (dominant) CANH See Figure 5 and Figure 14, TXD = 0 V, STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 2.75 4.5 V CANL 0.5 2.25 VO(REC) Bus output voltage (recessive) CANH and CANL See Figure 5 and Figure 14, TXD = VCC or VIO, VIO = VCC, STB = 0 V , RL = open (no load), RCM = open 2 0.5 × VCC 3 VO(STB) Bus output voltage (Standby mode) CANH See Figure 5 and Figure 14, STB = VIO, RL = open (no load), RCM = open -0.1 0 0.1 CANL -0.1 0 0.1 CANH - CANL -0.2 0 0.2 VOD(DOM) Differential output voltage (dominant) CANH - CANL See Figure 5 and Figure 14, TXD = 0 V, STB = 0 V, 45 Ω ≤ RL < 50 Ω, CL = open, RCM = open 1.4 3 See Figure 5 and Figure 14, TXD = 0 V, STB = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 1.5 3 See Figure 5 and Figure 14, TXD = 0 V, STB = 0 V, RL = 2240 Ω, CL = open, RCM = open 1.5 5 VOD(REC) Differential output voltage (recessive) CANH - CANL See Figure 5 and Figure 14, TXD = VCC, STB = 0 V, RL = 60 Ω, CL = open, RCM = open –120 12 mV See Figure 5 and Figure 14, TXD = VCC, STB = 0 V, RL = open (no load), CL = open, RCM = open –50 50 VSYM Output symmetry (dominant or recessive) ( VO(CANH) + VO(CANL)) / VCC See Figure 5 and Figure 17, STB at 0 V, Rterm = 60 Ω, Csplit = 4.7 nF, CL = open, RCM = open, TXD = 250 kHz, 1 MHz 0.9 1.1 V/V VSYM_DC DC Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) See Figure 5 and Figure 14, STB = 0 V, RL = 60 Ω, CL = open, RCM = open –0.4 0.4 V IOS(SS_DOM) Short-circuit steady-state output current, dominant, Normal mode See Figure 14 and Figure 11, STB at 0 V, VCANH = -5 V to 40 V, CANL = open, TXD = 0 V –100 mA See Figure 14 and Figure 11, STB at 0 V, VCANL = -5 V to 40 V, CANH = open, TXD = 0 V 100 IOS(SS_REC) Short-circuit steady-state output current, recessive, Normal mode See Figure 14 and Figure 11, STB at 0 V, –27 V ≤ VBUS ≤ 32 V, Where VBUS = CANH = CANL, TXD = VCC –5 5 mA

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT RECEIVER ELECTRICAL CHARACTERISTICS VCM Common mode range, Normal mode See Figure 6 and Table 1, STB = 0 V -30 +30 V VIT+ Positive-going input threshold voltage, Normal mode See Figure 6, Table 6 and Table 1, STB = 0 V, -20 V ≤ VCM ≤ +20 V 900 mV VIT– Negative-going input threshold voltage, Normal mode 500 VIT+ Positive-going input threshold voltage, Normal mode See Figure 6, Table 6 and Table 1, STB = 0 V, -30 V ≤ VCM ≤ +30 V 1000 VIT– Negative-going input threshold voltage, Normal mode 400 VHYS Hysteresis voltage (VIT+ - VIT–), Normal mode See Figure 6, Table 6 and Table 1, STB = 0 V 120 VCM Common mode range, Standby mode Devices with the "V" suffix (I/O level- shifting), See Figure 6, Table 6 and Table 1, STB = VIO, 4.5 V ≤ VIO ≤ 5.5 V -12 12 VDevices with the "V" suffix (I/O level- shifting), See Figure 6, Table 6 and Table 1, STB = VIO, 3.0 V ≤ VIO ≤ 4.5 V -2 +7 Devices without the "V" suffix (5V only), See Figure 6, Table 6 and Table 1, STB = VCC -12 12 VIT(STANDBY) Input threshold voltage, Standby mode STB = VCC or VIO 400 1150 mV ILKG(IOFF) Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC = VIO = 0 V 4.8 µA CI Input capacitance to ground (CANH or CANL) TXD = VCC, VIO = VCC 24 30 pF CID Differential input capacitance (CANH to CANL) TXD = VCC, VIO = VCC 12 15 RID Differential input resistance TXD = VCC = VIO = 5 V, STB = 0 V, -30 V ≤ VCM ≤ +30 V 30 80 kΩ RIN Input resistance (CANH or CANL) 15 40 RIN(M) Input resistance matching: [1 – RIN(CANH) / RIN(CANL)] × 100% VCANH = VCANL = 5 V –2% +2%

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω.

7.7 Switching Characteristics

Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DEVICE SWITCHING CHARACTERISTICS tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 8, STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 100 160 ns tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 110 175 tMODE Mode change time, from Normal to Standby or from Standby to Normal See Figure 7 9 45 µs tWK_FILTER Filter time for valid wake up pattern 0.5 1.85 µs DRIVER SWITCHING CHARACTERISTICS tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) See Figure 5, STB = 0 V, RL = 60 Ω, CL = 100 pF, RCM = open ns tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 55 tsk(p) Pulse skew (|tpHR - tpLD|) 20 tR Differential output signal rise time 45 tF Differential output signal fall time 45 tTXD_DTO Dominant timeout See Figure 10, STB = 0 V, RL = 60 Ω, CL = open 1.2 3.8 ms RECEIVER SWITCHING CHARACTERISTICS tpRH Propagation delay time, bus recessive input to high output (Dominant to Recessive) See Figure 6, STB = 0 V, CL(RXD) = 15 pF 65 ns tpDL Propagation delay time, bus dominant input to low output (Recessive to Dominant) 50 ns tR RXD Output signal rise time 10 ns tF RXD Output signal fall time 10 ns FD Timing Parameters tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all devices See Figure 9 , STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, ΔtREC = tBIT(RXD) - tBIT(BUS) 435 530 ns Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G device variants only 155 210 tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns, all devices 400 550 Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device variants only 120 220 ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices -65 40 Receiver timing symmetry with tBIT(TXD) = 200 ns, G device variants only -45 15

7.8 Typical Characteristics

Figure 1. VOD(D) over Temperature Figure 2. VOD(D) over VCC Figure 3. ICC Recessive over Temperature Figure 4. Total Loop Delay over Temperature

8 Parameter Measurement Information

Figure 5. Driver Test Circuit and Measurement Figure 6. Receiver Test Circuit and Measurement Table 1. Receiver Differential Input Voltage Threshold Test (See Figure 6)

Copyright © 2016, Texas Instruments Incorporated TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

These CAN transceivers meet the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. They are designed for data rates in excess of 1 Mbps for CAN FD and enhanced timing margin / higher data rates in long and highly-loaded networks. These devices provide many protection features to enhance device and CAN robustness.

9.2 Functional Block Diagram

communication after the time tTXD_DTO .

9.3 Feature Description

9.3.1 TXD Dominant Timeout (DTO)

held dominant longer than the timeout period tTXD_DTO. The DTO circuit timer starts on a falling edge on TXD. Figure 12. Example Timing Diagram for TXD DTO Minimum Data Rate = 11 / tTXD_DTO.

9.3.2 Thermal Shutdown (TSD)

(TTSD_HYS) below the thermal shutdown temperature (TTSD) of the device.

(1) See the VIT section of the Electrical Characteristics. (2) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

9.3.3 Undervoltage Lockout

bus during an undervoltage event on either the VCC or VIO supply terminals. Table 2. Undervoltage Lockout 5 V Only Devices (Devices without the "V" Suffix)(1) (1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive. Table 3. Undervoltage Lockout I/O Level Shifting Devices (Devices with the "V" Suffix) the device typically resumes normal operation within 50 µs.

9.3.4 Unpowered Device

loading down other circuits that may remain powered.

9.3.5 Floating Terminals

terminal is also pulled up to force the device into low power Standby mode if the terminal floats.

9.3.6 CAN Bus Short Circuit Current Limiting

• Control fields with set bits
• Bit stuffing
• Interframe space

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

• TXD dominant time out (fault case limiting) These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents. The average short circuit current may be calculated with the following formula: IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC] (1) Where:
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current NOTE Consider the short circuit current and possible fault cases of the network when sizing the power ratings of the termination resistance and other network components.

9.3.7 Digital Inputs and Outputs

9.3.7.1 5-V VCC Only Devices (Devices without the "V" Suffix): The 5-V VCC only devices are supplied by a single 5-V rail. The digital inputs have TTL input thresholds and are therefore 5 V and 3.3 V compatible. The RXD outputs on these devices are driven to the VCC rail for logic high output. Additionally, the TXD and STB pins are internally pulled up to VCC. The internal bias of the mode pins may only place the device into a known state if the terminals float, they may not be adequate for system-level biasing during transients or noisy enviroments. NOTE TXD pull up strength and CAN bit timing require special consideration when these devices are used with CAN controllers with an open-drain TXD output. An adequate external pull up resistor must be used to ensure that the CAN controller output of the micrcontroller maintains adequate bit timing to the TXD input. 9.3.7.2 5 V VCC with VIO I/O Level Shifting (Devices with the "V" Suffix): These devices use a 5 V VCC power supply for the CAN driver and high speed receiver blocks. These transceivers have a second power supply for I/O level-shifting (VIO). This supply is used to set the CMOS input thresholds of the TXD and pins and the RXD high level output voltage. Additionally, the internal pull ups on TXD and STB are pulled up to VIO.

(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

9.4 Device Functional Modes

Table 4. Operating Modes

9.4.1 CAN Bus States

receiver, corresponding to a logic high on the TXD and RXD terminals. Figure 13. Bus States (Physical Bit Representation) Figure 14. Bias Unit (Recessive Common Mode Bias) and Receiver

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

9.4.2 Normal Mode

Select the Normal mode of device operation by setting STB terminal low. The CAN driver and receiver are fully operational and CAN communication is bi-directional. The driver translates a digital input on TXD to a differential output on CANH and CANL. The receiver translates the differential signal from CANH and CANL to a digital output on RXD.

9.4.3 Standby Mode

Activate low power Standby mode by setting STB terminal high. In this mode the bus transmitter will not send data nor will the normal mode receiver accept data as the bus lines are biased to ground minimizing the system supply current. Only the low power receiver will be actively monitoring the bus for activity. RXD indicates a valid wake up event after a wake-up pattern (WUP) has been detected on the Bus. The low power receiver is powered using only the VIO pin. This allows VCC to be removed reducing power consumption further. The bus lines are biased to ground in Standby mode to minimize the required system supply current. The low power receiver is supplied by VIO and is capable of detecting CAN bus activity even if VIO is the only supply voltage available to the transceiver.

9.4.3.1 Remote Wake Request via Wake Up Pattern (WUP) in Standby Mode

active and the node should return to normal operation. falling edge and low corresponding to a "filtered" dominant on the RXD output terminal.

1. Bus signals that last less than tWK_FILTER(MIN) will never be detected as part of a valid WUP
2. Bus signals that last more than tWK_FILTER(MIN) but less than tWK_FILTER(MAX) may be detected as part of a valid
3. Bus signals that last more than tWK_FILTER(MAX) will always be detected as part of a valid WUP

that remains on the bus for longer than tWK_FILTER. Figure 15. Wake Up Pattern (WUP)

9.4.4 Driver and Receiver Function Tables

Figure 14 for bus state and common mode bias information. terminal will be pulled high and the transmitter will remain in recessive (non-driven) state. Table 5. Driver Function Table (1) H = high level, L = low level, ? = indeterminate. (2) See Receiver Electrical Characteristics section for input thresholds. Table 6. Receiver Function Table

validate and test their design implementation to confirm system functionality.

10.1 Application Information

microprocessor applications. The bus termination is shown for illustrative purposes.

10.2 Typical Applications

Figure 16. Typical CAN Bus Application

10.2.1 Design Requirements

10.2.1.1 Bus Loading, Length and Number of Nodes

The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. 11898-2. They have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000. km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

responsibility of good network design and balancing these tradeoffs.

10.2.2 Detailed Design Procedures

10.2.2.1 CAN Termination

two terminations always exist on the network. filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used. fluctuations in the bus common-mode voltages at the start and end of message transmissions. Figure 17. CAN Bus Termination Concepts needed for a 3.3-V micrcontroller.

10.2.3 Application Curves

Figure 20. ICC Dominant Current over VCC Supply Voltage

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

11 Power Supply Requirements

These devices are designed to operate from a VCC input supply voltage range between 4.5 V and 5.5 V. Some devices have an output level shifting supply input, VIO, designed for a range between 3.0 V and 5.5 V. Both supply inputs must be well regulated. A bulk capacitance, typically 4.7 μF, should be placed near the CAN transceiver's main VCC supply output, and in addition a bypass capacitor, typically 0.1 μF, should be placed as close to the device's VCC and VIO supply terminals. This helps to reduce supply voltaeg ripple present on the outputs of the switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB power planes and traces.

12 Layout

Robust and reliable bus node design often requires the use of external transient protection device in order to protect against EFT and surge transients that may occur in industrial enviroments. Because ESD and transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be applied during PCB design. The family comes with high on-chip IEC ESD protection, but if higher levels of system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors should be placed as close to the on-board connectors as possible to prevent noisy transient events from propagating further into the PCB and system.

TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

12.1 Layout Guidelines

• Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device, D1, has been used for added protection. The production solution can be either bi-directional TVS diode or varistor with ratings matching the application requirements. This example also shows optional bus filter capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the CANH and CANL lines between the transceiver U1 and connector J1.
• Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
• Use supply (VCC) and ground planes to provide low inductance. NOTE High-frequency currents follows the path of least impedance and not the path of least resistance.
• Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver, examples are C1, C2 on the VCC supply and C6 and C7 on the VIO supply.
• Bus termination: this layout example shows split termination. This is where the termination is split into two resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C3. Split termination provides common mode filtering for the bus. When bus termination is placed on the board instead of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the bus thus also removing the termination. See the application section for information on power ratings needed for the termination resistor(s).
• To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not required.
• Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used, this is mandatory to ensure the bit timing into the device is met.
• Terminal 5: For "V" variants of the family, bypass capacitors should be placed as close to the pin as possible (example C6 and C7). For device options without VIO I/O level shifting, this pin is not internally connected and can be left floating or tied to any existing net, for example a split pin connection.
• Terminal 8: is shown assuming the mode terminal, STB, will be used. If the device will only be used in normal mode, R4 is not needed and R5 could be used for the pull down resistor to GND.

12.2 Layout Example

13 Device and Documentation Support

13.1 Related Links

resources, tools and software, and quick access to order now. Table 7. Related Links

13.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

13.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.4 Trademarks

E2E is a trademark of Texas Instruments.

13.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C TYP-.244.228 -6.195.80[ ] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] TYP-.010.005 -0.250.13[ ] - 8 -.010.004 -0.250.11[ ] .010 [0.25] -.050.016 -1.270.41[ ] .041 [1.04] A NOTE 3 -.197.189 -5.004.81[ ] B NOTE 4 -.157.150 -3.983.81[ ] SOIC SOIC - 1.75 mm max heightD0008B 4221445/B 04/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] (.217) [5.5] 8X (.061 ) [1.55] 8X (.024) [0.6] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] SOIC SOIC - 1.75 mm max heightD0008B 4221445/B 04/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED OPENING SOLDER MASK DETAILS SOLDER MASK METAL SOLDER MASK DEFINED SCALE:6X LAND PATTERN EXAMPLE SYMM 4 5 SEE DETAILS IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE SYMM 4 5 SEE DETAILS SYMM TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (.217) [5.5] SOIC SOIC - 1.75 mm max heightD0008B 4221445/B 04/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE BASED ON .005 INCH [0.127 MM] THICK STENCIL SOLDER PASTE EXAMPLE SCALE:6X SYMM SYMM 4 5 IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM SYMM 4 5 TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

www.ti.com PACKAGE OUTLINE C 8X 0.35 0.25 2.4 0.05 1.95 1.6 0.05 6X 0.65

1 MAX

8X 0.5 0.3 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP

0.1 MIN

(0.05) VSON - 1 mm max heightDRB0008F PLASTIC SMALL OUTLINE - NO LEAD 4222121/C 10/2016 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 SCALE 30.000 SECTION A-A SECTION A-A TYPICAL TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.3) (2.4) (2.8) 6X (0.65) (1.6) ( 0.2) VIA TYP (0.55) (0.95) 8X (0.6) (R0.05) TYP VSON - 1 mm max heightDRB0008F PLASTIC SMALL OUTLINE - NO LEAD 4222121/C 10/2016 SYMM SCALE:20X LAND PATTERN EXAMPLE NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 www.ti.com SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.3) 8X (0.6) (1.47) (1.07) (2.8) (0.635) 6X (0.65) VSON - 1 mm max heightDRB0008F PLASTIC SMALL OUTLINE - NO LEAD 4222121/C 10/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 82% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 4 5 METAL TYP SYMM TCAN1042-Q1,TCAN1042V-Q1,TCAN1042H-Q1 TCAN1042HV-Q1,TCAN1042G-Q1,TCAN1042GV-Q1 TCAN1042HG-Q1,TCAN1042HGV-Q1 SLLSES9B – FEBRUARY 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1 TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

www.ti.com 18-Jun-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TCAN1042DQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042DRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042DRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042DRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042GDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042GDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042GDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042GDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042GVDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042GVDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042GVDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042GVDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HGDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042

www.ti.com 18-Jun-2017 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TCAN1042HGDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HGDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HGDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042 TCAN1042HGVDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HGVDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HGVDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HGVDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HVDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HVDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HVDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042HVDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042VDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V TCAN1042VDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042VDRBTQ1 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 125 1042V TCAN1042VDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1042V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 18-Jun-2017 Addendum-Page 3 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TCAN1042H-Q1, TCAN1042HG-Q1, TCAN1042HGV-Q1, TCAN1042HV-Q1 :

• Catalog: TCAN1042H , TCAN1042HG , TCAN1042HGV , TCAN1042HV NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

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