TCAL9538

TCAL9538 8 -Bit I2 C-Bus, SMBus I/O Expander With Interrupt Output, Reset, and Agile I/O Configuration Registers datasheet (Rev. B)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCPS280,B]
• PDF pages: 50

Technical content

TCAL9538 8-Bit I2C-Bus, SMBus I/O Expander With Interrupt Output, Reset, and Agile I/O Configuration Registers

1 Features

• Operating power-supply voltage range of 1.08V to 3.6V
• Low standby current consumption of 1µA typical at 1.8V
• 1MHz fast mode plus I2C bus
• Hardware address pin allows four devices on the same I2C, SMBus bus
• Active-low reset input (RESET)
• Open-drain active-low interrupt output (INT)
• Input or output configuration register
• Polarity inversion register
• Configurable I/O drive strength register
• Pull-up and pull-down resistor configuration register
• Internal power-on reset
• Noise filter on SCL or SDA inputs
• Latched outputs with high-current drive maximum capability for directly driving LEDs
• Latch-up performance exceeds 100mA per JESD 78, class II
• ESD protection exceeds JESD 22 – 4000V Human-body model (A114-A) – 1000V Charged-device model (C101)

2 Applications

• Servers
• Routers (telecom switching equipment)
• Personal computers
• Personal electronics
• Industrial automation
• Gaming consoles
• Products with GPIO-limited processors

3 Description

The TCAL9538 device provides general purpose parallel input/output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol and is designed for 1.08V to 3.6V VCC operation. The device supports 100kHz (Standard-mode), 400kHz (Fast-mode), and 1MHz (fast-mode-plus) I2C clock frequencies. I/O expanders such as the TCAL9538 provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and so on. The TCAL9538 has Agile I/O ports which include additional features designed to enhance the I/O performance in terms of speed, power consumption and EMI. The additional features are: programmable output drive strength, programmable pull-up and pull- down resistors, latchable inputs, maskable interrupt, interrupt status register, and programmable open- drain or push-pull outputs.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TCAL9538 TSSOP (16) 5mm × 6.4mm UQFN (16) 2.6mm × 1.8mm X2QFN (16) 1.6mm x 1.6mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TCAL9538 I2C or SMBus Controller (processor) SDA SCL INT VCC GND RESET Peripheral Devices RESET, ENABLE, or control inputs INT or status outputs LEDs Keypad Simplified Schematic TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. PW (TSSOP) Package, 16-Pin (Top View) RESET 1 SCL INT P3 GND P4 P5 A1 A0 VCC SDA 5 6 7 8 16 15 14 13 Figure 4-2. RSV (UQFN) Package, 16-Pin (Top View) Not to scale 1 2 3 4 A B C D P3 GND P4 P5 P6P7P1 A1 SDA INT SCLVCCA0RESET Figure 4-3. DTU (X2QFN) Package, 16-Pin (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME TSSOP (PW) QFN (RSV) X2QFN (DTU) A0 1 15 A2 I Address input. Connect directly to VCC or ground A1 2 16 B2 I Address input. Connect directly to VCC or ground GND 8 6 D2 – Ground INT 13 11 B4 O Interrupt output. Connect to VCC through a pull-up resistor P0 4 2 B1 I/O P-port input/output (push-pull design structure). At power on, P0 is configured as an input P1 5 3 C2 I/O P-port input/output (push-pull design structure). At power on, P1 is configured as an input P2 6 4 C1 I/O P-port input/output (push-pull design structure). At power on, P2 is configured as an input P3 7 5 D1 I/O P-port input/output (push-pull design structure). At power on, P3 is configured as an input P4 9 7 D3 I/O P-port input/output (push-pull design structure). At power on, P4 is configured as an input P5 10 8 D4 I/O P-port input/output (push-pull design structure). At power on, P5 is configured as an input P6 11 9 C4 I/O P-port input/output (push-pull design structure). At power on, P6 is configured as an input P7 12 10 C3 I/O P-port input/output (push-pull design structure). At power on, P7 is configured as an input RESET 3 1 A1 I Active-low reset input. Connect to VCC through a pull-up resistor, if no active connection is used SCL 14 12 A4 I Serial clock bus. Connect to VCC through a pull-up resistor SDA 15 13 B3 I/O Serial data bus. Connect to VCC through a pull-up resistor VCC 16 14 A3 – Supply voltage (1) I = Input, O = Output, I/O = Input or Output. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCAL9538

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 4 V VI Input voltage(2) –0.5 4 V VO Output voltage(2) –0.5 4 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input-output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current(3) VO = 0 to VCC 50 mA IOH Continuous output high current(3) VO = 0 to VCC –50 mA ICC Continuous current through GND –200 mA ICC Continuous current through VCC 160 mA TJ Junction temperature 130 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) Connecting an IO pin directly to GND is not allowed if this pin is set as output, because this will generate >150mA current which could damage the device. We recommend a >10kΩ pull down resistor connected to IO pin if user wants to connect the IO pin to GND.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±4000 V Charged device model (CDM), per ANSI/ESDA/ JEDEC specification JS-002, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 1.08 3.6 V VIH High-level input voltage All Pins 0.7 * VCC 3.6 V VIL Low-level input voltage All Pins -0.5 0.3 * VCC V IOH High-level output current P0-P7 –10 mA IOL Low-level output current (VOL ≤ 0.3V) P0-P7 25 mA TA Ambient temperature –40 125 °C TJ Junction temperature 125 °C TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) Package UNITPW (TSSOP) RSV (UQFN) DTU (X2QFN) PINS PINS PINS RθJA Junction-to-ambient thermal resistance 115.7 123.1 143.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 46.1 65.0 55.6 °C/W RθJB Junction-to-board thermal resistance 62.0 54.6 81.9 °C/W ΨJT Junction-to-top characterization parameter 6.0 2.9 1.3 °C/W ΨJB Junction-to-board characterization parameter 61.4 52.9 81.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCAL9538

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIK Input diode clamp voltage II = –18 mA 1.08 V to 3.6 V –1.2 V VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 0.85 1.0 V VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.6 0.75 V VOH P-port high-level output voltage(1) IOH = –8 mA; CC-XX = 11b 1.08 V 0.8 V 1.65 V 1.4 2.3 V 2.1 3 V 2.8 IOH = –2.5 mA & CC-XX = 00b; IOH = –5 mA & CC-XX = 01b; IOH = –7.5 mA & CC-XX = 10b; IOH = –10 mA & CC-XX = 11b; 1.08 V 0.75 1.65 V 1.4 2.3 V 2.1 3 V 2.8 VOL Low-level output voltage P ports IOL = 8 mA; CC-XX = 11b 1.08 V 0.2 V 1.65 V 0.15 2.3 V 0.1 3.0 V 0.1 P ports IOL = 2.5 mA and CC-XX = 00b; IOL = 5 mA and CC-XX = 01b; IOL = 7.5 mA and CC-XX = 10b; IOL = 10 mA and CC-XX = 11b; 1.08 V 0.25 V 1.65 V 0.15 2.3 V 0.1 3.0 V 0.1 IOL Low-level output current SDA VOL = 0.4 V 1.08 V to 3.6 V mA INT VOL = 0.4 V 4 II Input leakage current P ports VI = VCC or GND 1.08 V to 3.6 V ±1 µAVI = 3.6 V 0 V ±1 II Input leakage current SCL, SDA, RESET VI = VCC or GND 1.08 V to 3.6 V ±1 II Input leakage current VI = VCC or GND 1.08 V to 3.6 V ±1 µA TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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5.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT ICC Quiescent current Operating mode (400 kHz) SDA, RESET =VCC, P ports, ADDR = VCC or GND, I/O = inputs, fSCL = 400 kHz, –40°C < TA ≤ 85°C

3.6 V 11 15

µA

2.7 V 8 11

1.95 V 5 8

1.32 V 2 6

SDA, RESET =VCC, P ports, ADDR = VCC or GND, I/O = inputs, fSCL = 400 kHz, 85°C < TA ≤ 125°C

3.6 V 7 24

µA

2.7 V 5 18

1.95 V 4 14

1.32 V 2 11

(1 MHz) SDA, RESET = VCC, P ports, ADDR = VCC or GND, I/O = inputs, fSCL = 1 MHz, –40°C < TA ≤ 85°C

3.6 V 34

µA

2.7 V 24

1.95 V 18

1.32 V 12

SDA, RESET = VCC, P ports, ADDR = VCC or GND, I/O = inputs, fSCL = 1 MHz, 85°C < TA ≤ 125°C

3.6 V 42

µA

2.7 V 30

1.95 V 22

1.32 V 16

SCL, SDA, RESET = VCC, P port, ADDR = VCC or GND, I/O = inputs, IO = 0, fSCL = 0 kHz,

3.6 V 1 3

µA 2.7 V 0.8 2.0 1.95 V 0.6 1.6 1.32 V 0.6 1.4 SCL, SDA, RESET = VCC. P port, ADDR = VCC or GND, I/O = inputs, IO = 0, fSCL = 0 kHz, 85 °C < TA ≤ 125 °C

3.6 V 14

µA

2.7 V 10

1.95 V 8

1.32 V 6

Rpu(int) internal pull-up resistance P port 70 100 140 kΩ Rpd(int) internal pull-down resistance CI Input pin capacitance SCL VI = VCC or GND 1.08 V to 3.6 V 2.5 5 pF CIO Input-output pin capacitance SDA VIO = VCC or GND 1.08 V to 3.6 V 6 8 pF P port VIO = VCC or GND 1.08 V to 3.6 V 6 8.5 (1) Each I/O must be externally limited to a maximum of 25 mA, CC-XX refers to output drive strength register setting.

5.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT RESET tw Reset pulse duration 80 ns tREC Reset recovery time 0 ns tRESET Time to reset 400 ns P-Ports tPH Minimum pulse width on P-Port that causes an interrupt 30 ns www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCAL9538

5.7 I2C Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT I2C Bus - Standard Mode fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 ns tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capacitive load 400 pF I2C Bus - Fast Mode fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns ticf I2C input fall time 20 × (VCC / 5.5 V) 300 ns tocf I2C output fall time 10-pF to 400-pF bus 20 × (VCC / 5.5 V) 300 ns tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 µs tvd(data) Valid data time SCL low to SDA output valid 0.9 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 µs Cb I2C bus capacitive load 400 pF I2C Bus - Fast Mode Plus fscl I2C clock frequency 0 1000 kHz tsch I2C clock high time 0.26 µs tscl I2C clock low time 0.5 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 50 ns tsdh I2C serial-data hold time 0 ns TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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5.7 I2C Bus Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT ticr I2C input rise time 120 ns ticf I2C input fall time 20 × (VCC / 5.5 V) 120 ns tocf I2C output fall time 10-pF to 550-pF bus 20 × (VCC / 5.5 V) 120 ns tbuf I2C bus free time between stop and start 0.5 µs tsts I2C start or repeated start condition setup 0.26 µs tsth I2C start or repeated start condition hold 0.26 µs tsps I2C stop condition setup 0.26 µs tvd(data) Valid data time SCL low to SDA output valid 0.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.45 µs Cb I2C bus capacitive load 550 pF

5.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT tiv Interrupt valid time P port INT 1 µs tir Interrupt reset delay time SCL INT 1 µs tpv Output data valid time SCL P port 400 ns tps Input data setup time P port SCL 0 ns tph Input data hold time P port SCL 300 ns www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCAL9538

5.9 Typical Characteristics

TA = 25°C (unless otherwise noted) Temperature (C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 3.6 V VCCP = 3.3 V VCCP = 2.5 V VCCP = 1.8 V VCCP = 1.2 V VCCP = 1.08 V Figure 5-1. Supply Current vs Temperature - FM mode Temperature (C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 3.6V VCCP = 3.3V VCCP = 2.5V VCCP = 1.8V VCCP = 1.2V VCCP = 1.08V Figure 5-2. Supply Current vs Temperature - FM+ mode Temperature (C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 3.6 V VCCP = 3.3 V VCCP = 2.5 V VCCP = 1.8 V VCCP = 1.2 V VCCP = 1.08 V Figure 5-3. Standby Supply Current vs Temperature VCCP - Supply Voltage (V) ICC - Supply Current (µA) 125C 85C 25C -40C Figure 5-4. Supply Current vs Supply Voltage - FM mode VCCP - Supply Voltage (V) ICC - Supply Current (µA) 125C 85C 25C -40C Figure 5-5. Supply Current vs Supply Voltage - FM+ mode VOL - Output Low Voltage (V) IOL - Sink Current (mA) 125C 85C 25C -40C Figure 5-6. I/O Sink Current vs Output Low Voltage, VCC = 1.08V TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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5.9 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) VOL - Output Low Voltage (V) IOL - Sink Current (mA) 125C 85C 25C -40C Figure 5-7. I/O Sink Current vs Output Low Voltage, VCC = 1.2V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 120 140 160 180 200 125C 85C 25C -40C Figure 5-8. I/O Sink Current vs Output Low Voltage, VCC = 1.8V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 125 150 175 200 225 250 275 300 125C 85C 25C -40C Figure 5-9. I/O Sink Current vs Output Low Voltage, VCC = 2.5V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 125 150 175 200 225 250 275 300 325 125C 85C 25C -40C Figure 5-10. I/O Sink Current vs Output Low Voltage, VCC = 3.3V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 125 150 175 200 225 250 275 300 325 125C 85C 25C -40C Figure 5-11. I/O Sink Current vs Output Low Voltage, VCC = 3.6V Temperature (C) VOL - Output Low Voltage (mV) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 1.2V, I OL = 10 mA VCCP = 3.3V, I OL = 10 mA VCCP = 1.2V, IOL = 1 mA VCCP = 3.3V, I OL = 1 mA Figure 5-12. I/O Low Voltage vs Temperature www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCAL9538

TA = 25°C (unless otherwise noted) VCC - VOH (V) Source Current (mA) 125C 85C 25C -40C Figure 5-13. I/O Source Current vs Output High Voltage , VCC = 1.08V VCC - VOH (V) Source Current (mA) 125C 85C 25C -40C Figure 5-14. I/O Source Current vs Output High Voltage, VCC = 1.2V VCC - VOH (V) Source Current (mA) 100 110 120 130 125C 85C 25C -40C Figure 5-15. I/O Source Current vs Output High Voltage, VCC = 1.8V VCC - VOH (V) Source Current (mA) 100 125 150 175 125C 85C 25C -40C Figure 5-16. I/O Source Current vs Output High Voltage, VCC = 2.5V VCC - VOH (V) Source Current (mA) 100 120 140 160 180 200 220 125C 85C 25C -40C Figure 5-17. I/O Source Current vs Output High Voltage, VCC = 3.3V VCC - VOH (V) Source Current (mA) 120 150 180 210 240 125C 85C 25C -40C Figure 5-18. I/O Source Current vs Output High Voltage, VCC = 3.6V TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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TA = 25°C (unless otherwise noted) Temperature (C) VCC - VOH (V) -40 -25 -10 5 20 35 50 65 80 95 110 125 0.02 0.04 0.06 0.08 0.1 0.12 0.14 VCC = 1.2V, I SOURCE = -10 mA VCC = 3.3V, I SOURCE = -10 mA VCC = 1.2V, ISOURCE = -1 mA VCC = 3.3V, I SOURCE = -1 mA Figure 5-19. I/O High Voltage vs Temperature www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCAL9538

6 Parameter Measurement Information

RL = 1 k/c87 VCC CL = 50 pF (see Note A) tbuf ticr tsth tsds tsdh ticf ticr tscl tsch tststvd(ack) tvd(data) 0.3 /c215VCC Stop Condition tsps Repeat Start ConditionStart or Repeat Start Condition SCL SDA Start Condition (S) Address Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) Three Bytes for Complete Device Programming SDA LOAD CONFIGURATION VOLTAGE WAVEFORMS ticf Stop Condition (P) tsp DUT SDA 0.7 /c215VCC 0.3 /c215VCC 0.7 /c215VCC R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Address Bit 1 Address Bit 6 BYTE DESCRIPTION

1 I 2C address

2, 3 P-port data A. CL includes probe and jig capacitance. tocf is measured with CL of 10pF or 400pF. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. All parameters and waveforms are not applicable to all devices. Figure 6-1. I2C Interface Load Circuit and Voltage Waveforms TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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A A A A S 1 1 1 0 A1 0 A0 1 Data 1 1 PData 2 Start Condition 8 Bits (One Data Byte) From Port Data From PortSlave Address R/W 87654321 tir tir tsps tiv Address Data 1 Data 2 INT Data Into Port B B A A Pn INT R/W A tir 0.7 × VCC 0.3 × VCC 0.7 × VCC 0.3 × VCC 0.7 × VCC 0.3 × VCC 0.7 × VCC 0.3 × VCC INT SCL View B−BView A−A tiv RL = 4.7 kΩ VCC CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION DUT INT ACK From Slave ACK From Slave A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. All parameters and waveforms are not applicable to all devices. Figure 6-2. Interrupt Load Circuit and Voltage Waveforms www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCAL9538

0.7 × VCC 0.3 × VCC SCL P3 tpv (see Note B) Slave ACK Unstable Data Last Stable Bit SDA Pn Pn WRITE MODE (R/W = 0) P0 A 0.7 × VCC 0.3 × VCC SCL P3 0.7 × VCC 0.3 × VCC tps tph READ MODE (R/W = 1) DUT CL = 50 pF (see Note A) P-PORT LOAD CONFIGURATION Pn 2 × VCC 500 Ω 500 Ω A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 6-3. P-Port Load Circuit and Timing Waveforms TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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0.3 V CC

(see Note D) RL = 1 kΩ VCC CL = 50 pF (see Note A) SDA LOAD CONFIGURATION DUT SDA P-PORT LOAD CONFIGURATION VCC/2 tRESET DUT CL = 50 pF (see Note A) Pn 2 × VCC 500 Ω 500 Ω A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 6-4. Reset Load Circuits and Voltage Waveforms www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCAL9538

7 Detailed Description

7.1 Overview

The TCAL9538 is a general purpose I/O expander for the two-line bidirectional bus (I2C) is designed for 1.08V to 3.6V operation. It provides general-purpose remote I/O expansion for processors through I2C communication, an interface consisting of serial clock (SCL), and serial data (SDA) signals. The TCAL9538 digital core consists of 8-bit data registers, which allow the user to configure the I/O port characteristics. At power-up or after a software reset call, the I/Os are configured as inputs. However, the system controller can configure the I/Os as either inputs or outputs by writing to the Configuration registers. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. The system controller can read all registers. Additionally, the TCAL9538 has Agile I/O functionality, which is specifically targeted to enhance the I/O ports. The Agile I/O features and registers include programmable output drive strength, programmable pull-up and pull-down resistors, latchable inputs, maskable interrupts, interrupt status register, and programmable open-drain or push-pull outputs. These configuration registers improve the I/O by increasing flexibility and allowing the user to optimize their design for power consumption, speed, and EMI. Other features of the device include an interrupt that is generated on the INT pin whenever an input port changes state. The device can be reset to its default state by issuing a software reset command or by cycling power to the device and causing a power-on reset. The hardware selectable address pins allow multiple TCAL9538 devices to be connected to the same I2C bus. The TCAL9538 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed. The INT pin can be connected to the interrupt input of a processor. By sending an interrupt signal on this line, the device can inform the processor if there is incoming data on the remote I/O ports without having to communicate through the I2C bus. Thus, the device can remain a simple target device. The system controller can re-initialize I 2C/SMBus state machine in the event of a timeout or other improper operation by asserting a low on the RESET input pin. Two hardware pins (A0 and A1) can be used to program and vary the fixed I 2C address, and allow up to four devices to share the same I2C bus or SMBus.

7.2 Functional Block Diagrams

8 Bits I/O

Figure 7-1. Logic Diagram (Positive Logic) TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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A. On power up or reset, all registers return to default values. Figure 7-2. Simplified Schematic of P0 to P7

7.3 Feature Description

7.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off (see Section 7.2), which creates a high- impedance input. The input voltage may be raised above the supply voltage to a maximum of 3.6V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either supply or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.

7.3.2 Adjustable Output Drive Strength

The output drive strength registers allow the user to control the drive level of the GPIO. Each GPIO can be configured independently to one of the four possible current levels. By programming these bits the user is changing the number of transistor pairs or 'fingers' that drive the I/O pad. Figure 7-3 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the output drive strength register. When the output drive strength register bits are programmed to 01b, then only two of the fingers are active, reducing the current drive capability by 50%. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCAL9538

PMOS_EN0 PMOS_EN1 PMOS_EN2 PMOS_EN3 NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 Output Port Register Current Control Register PMOS_EN[3:0] NMOS_EN[3:0] Figure 7-3. Simplified Output Stage A function of the output drive selection causes a peak current to occur when the output switches. Reducing the current drive capability may reduce the system noise that occurs. This peak current runs through the supply and GND package inductance and creates a noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues without the need of additional external components.

7.3.3 Interrupt Output (INT)

Any rising or falling edge of the port inputs in the input mode generates an interrupt, provided the interrupt feature is unmasked. After time t iv, the INT signal is valid. Resetting the interrupt circuit is achieved when data on the port is changed back to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. The INT output has an open-drain structure and requires an external pull-up resistor to V CC if the interrupt feature is required; otherwise, it may be left floating.

7.3.4 Reset Input (RESET)

The RESET input can be asserted to initialize the system while keeping the V CC supply at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of t W. The TCAL9538 registers and I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P port can be changed externally or through the controller. This input requires a pull-up resistor to V CC, if no active connection is used. When RESET is toggled the input port register is updated to reflect the state of the GPIO pins. TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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7.3.5 Software Reset Call

The software reset call is a command sent from the controller on the I 2C bus that instructs all devices that support the command to be reset to the power-up default state. To function as expected, the I 2C bus must be functional, and no devices can be hanging the bus. The software reset call is defined as the following steps: 1. The I2C bus controller sends a start condition. 2. The address used is the reserved general call I2C bus address '0000 0000' with the R/W bit set to 0. The byte sent is 0x00. 3. Any devices supporting the general call functionality will ACK. If the R/W bit is set to 1 (read), then the device will NACK. 4. When the general call address is acknowledged, the controller sends only 1 byte of data equal to 0x06. If the data byte is any other value, then the device does not acknowledge or reset. If more than 1 byte is sent, then no more bytes is acknowledged, and the device ignores the I2C message considering as invalid. 5. After the 1 byte of data (0x06) is sent, the controller sends a STOP condition to end the Software Reset sequence. The device ignores a repeated START condition and no reset is performed. When the previous steps are completed successfully, the device performs a reset. This clears all register values back to power-on defaults.

7.4 Device Functional Modes

7.4.1 Power-On Reset

When power (from 0V) is applied to V CC, an internal power-on reset holds the TCAL9538 in a reset condition until the supply has reached VPOR. At that time, the reset condition is released, and the TCAL9538 registers and I2C/SMBus state machine initializes to their default states. After that, V CC must be lowered to below V PORF and back up to the operating voltage for a power-reset cycle.

7.5 Programming

7.5.1 I2C Interface

The bidirectional I 2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfer can only be initiated when the bus is not busy. A controller initiates I 2C communication with this device by sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 7-4). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address input of the target device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 7-5). The controller sends a Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high (see Figure 7-4). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7-6). When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met for proper operation. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCAL9538

A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the target. The controller receiver does this by holding the SDA line high. In this event, the transmitter must release the data line to enable the controller to generate a Stop condition. SDA SCL S P Start□Condition Stop□Condition Figure 7-4. Definition of Start and Stop Conditions SDA SCL Data□Line Change Figure 7-5. Bit Transfer S 1 2 8 9 NACK ACK Data Output by Transmitter Data Output by Receiver SCL From Controller Start Condition Clock Pulse for Acknowledgment Figure 7-6. Acknowledgment on the I2C Bus Table 7-1. Interface Definition BYTE BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Device I2C address H H H L L A1 A0 R/ W I/O data bus P7 P6 P5 P4 P3 P2 P1 P0 TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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7.6 Register Maps

7.6.1 Device Address

Figure 7-7 shows the address of the TCAL9538. 1 1 1 0 A1 A0 Slave Address R/W Fixed Programmable Figure 7-7. TCAL9538 Address Table 7-2. Address Reference Inputs I2C BUS TARGET ADDRESS A1 A0 L L 112 (decimal), 70 (hexadecimal) L H 113 (decimal), 71 (hexadecimal) H L 114 (decimal), 72 (hexadecimal) H H 115 (decimal), 73 (hexadecimal) The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCAL9538

7.6.2 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which is stored in the control register in the TCAL9538. The lower two bits of this data byte reflect the internal registers (input, output, polarity inversion, or configuration) that are affected. Bit 6 in conjunction with the lower four bits of the Command byte are used to point to the extended features of the device (Agile IO). The command byte is sent only during a write transmission. Once a new command has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Upon power-up, hardware reset, or software reset, the control register defaults to 00h. B2 B1 B0B5 B4 B3B7 B6 Figure 7-8. Control Register Bits Table 7-3. Command Byte CONTROL REGISTER BITS COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULTB7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 00 Input Port Read byte xxxx xxxx 0 0 0 0 0 0 0 1 01 Output Port Read/write byte 1111 1111 0 0 0 0 0 0 1 0 02 Polarity Inversion Read/write byte 0000 0000 0 0 0 0 0 0 1 1 03 Configuration Read/write byte 1111 1111 0 1 0 0 0 0 0 0 40 Output Drive Strength 0 Read/write byte 1111 1111 0 1 0 0 0 0 0 1 41 Output Drive Strength 1 Read/write byte 1111 1111 0 1 0 0 0 0 1 0 42 Input latch register Read/write byte 0000 0000 0 1 0 0 0 0 1 1 43 Pull-up/pull-down enable register Read/write byte 0000 0000 0 1 0 0 0 1 0 0 44 pull-up/pull-down selection register Read/write byte 1111 1111 0 1 0 0 0 1 0 1 45 Interrupt mask register Read/write byte 1111 1111 0 1 0 0 0 1 1 0 46 Interrupt status register Read byte 0000 0000 0 1 0 0 1 1 1 1 4F Output port configuration register Read/write byte 0000 0000

7.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The input port register is read only. Writes to this register have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I 2C device that the Input Port register will be accessed next. Table 7-4. Register 0 (Input Port Register) BIT I-7 I-6 I-5 I-4 I-3 I-2 I-1 I-0 DEFAULT X X X X X X X X The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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Table 7-5. Register 1 (Output Port Register) BIT O-7 O-6 O-5 O-4 O-3 O-2 O-1 O-0 DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written to '1'), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written to a '0'), the corresponding port pin's original polarity is retained. Table 7-6. Register 2 (Polarity Inversion Register) BIT P-7 P-6 P-5 P-4 P-3 P-2 P-1 P-0 DEFAULT 0 0 0 0 0 0 0 0 The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 7-7. Register 3 (Configuration Register) BIT C-7 C-6 C-5 C-4 C-3 C-2 C-1 C-0 DEFAULT 1 1 1 1 1 1 1 1 The output drive strength registers control the output drive level of the P port GPIO buffers. Each GPIO can be configured independently to the desired output current level by two register control bits. For example, Port P7 is controlled by register 41 (bits 7 and 6), port P6 is controlled by register 41 (bits 5 and 4), and so on. The output drive level of the GPIO is programmed 00b = 0.25x drive strength, 01b = 0.5x drive strength, 10b = 0.75x drive strength, or 11b = 1x for full drive strength capability. Table 7-8. Registers 40, and 41 (Output Drive Strength Registers) BIT CC-3 CC-3 CC-2 CC-2 CC-1 CC-1 CC-0 CC-0 DEFAULT 1 1 1 1 1 1 1 1 BIT CC-7 CC-7 CC-6 CC-6 CC-5 CC-5 CC-4 CC-4 DEFAULT 1 1 1 1 1 1 1 1 The Input latch register enables and disables the input latch feature of the P port GPIO pins. This register is effective only when the pin is configured as an input port. When an input latch register bit is 0, the corresponding input pin state is not latched. A state change in the corresponding input pin generates an interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. When an input latch register bit is set to 1, the corresponding input pin state is latched. A change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0 and 1). A read of the input port register clears the interrupt. However, if the input pin returns to its initial logic state before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. For example, if the P4 input was at a logic 0 state and then transitions to a logic 1 state followed by going back to the logic 0 state, the input port register will capture this change and an interrupt will be generated (if unmasked). When the read is performed on the input port 0 register, the interrupt is cleared, assuming there were no additional inputs that have changed, and bit 4 of the input port register will read '1'. The next read of the input port register bit 4 should now read '0'. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state. A read of the input register reflects only the change of state of the latched input and also clears the interrupt. If the input latch register changes from a latched to a non-latched configuration, the interrupt will be cleared if the input logic value returns to its original state. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCAL9538

If the input pin is changed from a latched to a non-latched input, a read from the input port register reflects the current port logic level. If the input pin is changed from a non-latched to a latched input, the read from the input register reflects the latched logic level. Table 7-9. Register 42 (Input Latch Register) BIT L-7 L-6 L-5 L-4 L-3 L-2 L-1 L-0 DEFAULT 0 0 0 0 0 0 0 0 The pull-up/pull-down enable register allows the user to enable or disable pull-up/pull-down resistors on the GPIO pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the GPIO pins. The resistors are disabled when the GPIOs are configured as outputs Use the pull-up/pull-down selection register to select either a pull-up or pull-down resistor. Table 7-10. Register 43 (Pull-Up/Pull-Down Enable Register) BIT PE-7 PE-6 PE-5 PE-4 PE-3 PE-2 PE-1 PE-0 DEFAULT 0 0 0 0 0 0 0 0 The pull-up/pull-down selection register allows the user to configure each GPIO to have a pull-up or pull-down resistor by programming the respective register bit. Setting a bit to a logic 1 selects a 100k Ω pull-up resistor for that GPIO pin. Setting a bit to logic 0 selects a 100k Ω pull-down resistor for that GPIO pin. If the pull-up/ pull-down feature is disabled through register 43, writing to this register has no effect on the GPIO pin. Table 7-11. Register 44 (Pull-Up/Pull-Down Selection Register) BIT PUD-7 PUD-6 PUD-5 PUD-4 PUD-3 PUD-2 PUD-1 PUD-0 DEFAULT 1 1 1 1 1 1 1 1 The Interrupt mask register is defaulted to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding bit in the interrupt mask register is to 1, the interrupt is masked and the interrupt pin is not asserted. If the corresponding bit in the interrupt mask register is set to 0, the interrupt pin is asserted. When an input changes state and the resulting interrupt is masked, setting the interrupt mask register bit to 0 will cause the interrupt pin to be asserted. If the interrupt mask bit of an input that is already currently the source of an interrupt is set to 1, the interrupt pin is de-asserted. Table 7-12. Register 45 (Interrupt Mask Register) BIT M-7 M-6 M-5 M-4 M-3 M-2 M-1 M-0 DEFAULT 1 1 1 1 1 1 1 1 The Interrupt status register is a read only register used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return to logic 0. Table 7-13. Register 46 (Interrupt Status Register) BIT S-7 S-6 S-5 S-4 S-3 S-2 S-1 S-0 DEFAULT 0 0 0 0 0 0 0 0 The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 7-2). A logic 1 configures the I/O as open-drain ( Q1 is disabled, Q2 is active) and the recommended command sequence is to program this register (4F) before the Configuration register (03) sets the port pins as outputs. TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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Table 7-14. Register 4F (Output Port Configuration Register) BIT Reserved ODEN-0 DEFAULT 0 0 0 0 0 0 0 0

7.6.4 Bus Transactions

Data is exchanged between the controller and TCAL9538 through write and read commands.

7.6.4.1 Writes

Data is transmitted to the TCAL9538 by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 7-7 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. 1 2SCL 3 4 5 6 7 8 SDA A A A Data 0 R/W tpv 00 0 0 0 0 0 1 0.7 0.0 Data 11.7 1.0 AS 1 1 1 0 0 0 P Target Address Command Byte Data to Port 0 Data to Port 1 Start Condition Acknowledge From Target Write to Port Data Out from Port 1 Data Out from Port 0 Data Valid Acknowledge From Target Acknowledge From Target tpv Stop Condition A1 A2 Figure 7-9. Write to Output Port Registers <br/> 1 2SCL 3 4 5 6 7 8 SDA A A A Data 0 Data to Register R/W 00 0 0 0 0 1 1 MSB LSB Data1MSB LSB AS 1 1 1 0 0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 P Acknowledge From Target Acknowledge From Target Start Condition Command ByteTarget Address Acknowledge From Target Data to Register Stop Condition A1 A0 Figure 7-10. Write to Configuration Registers

7.6.4.2 Reads

The bus controller must first send the TCAL9538 address with the LSB set to a logic 0 (see Figure 7-7 for device address). The command byte is sent after the address and determines which register is accessed. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus controller must not acknowledge the data. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCAL9538

A PNA S 1 MSB LSB MSB L SB Target Address Acknowledge From Target Command Byte Data From Upper or Lower Byte of Register Last Byte Data Acknowledge From Target Acknowledge From TargetTarget Address Data From Lower or Upper Byte of Register First Byte Data No Acknowledge From Controller Acknowledge From Controller At this moment, controller transmitter becomes controller receiver, and target receiver becomes target transmitter. 1 0 01 1 R/W Stop Condition A0 A1 A0 Figure 7-11. Read From Register <br/> SCL SDA INT Start Condition R/W Read From Port Data Into Port Stop Condition ACK From Controller NACK From Controller ACK From Target Data From PortTarget Address Data From Port 1 9 R765432 01 1S 01 A1 1 A Data 1 Data 4A NA P Data 2 Data 3 Data 4 Data 5 INT is cleared by Read from Port Stop not needed to clear INT tph tps tirtiv A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from P port (see Figure 7-11). Figure 7-12. Read Input Port Register TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

TCAL9538 is used in applications where this device is connected as a target to an I 2C controller (processor); the I2C bus may contain any number of other target devices. The TCAL9538 is in a remote location from the controller, placed close to the GPIOs to which the controller needs to monitor or control.

8.2 Typical Application

shows an application in which the TCAL9538 can be used. SDA SCL INT GND INT GND VCC VCC VCC 10 k (1) Ω 10 k (1) Ω 10 kΩ 10 kΩ 2 kΩ 100 kΩ (x 3) Master Controller TCAL9538 INT RESET Subsystem 2 (e.g., counter) Subsystem 3 (e.g., alarm system) ALARM Controlled Device (e.g., CBT device)ENABLE A B VCC RESET RESET Subsystem 1 (e.g., temperature sensor)SDA SCL 1 1 A. Device address configured as 1110000 for this example. B. P0, P2 and P3 are configured as outputs. C. P1, P4, and P5 are configured as inputs. D. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor is not needed. Outputs (in the P port) do not need pullup resistors. Figure 8-1. Typical Application Schematic www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCAL9538

8.2.1 Design Requirements

Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Supply Voltage (VCC) 1.8V Output current rating, P-port sinking (IOL) 25mA Output current rating, P-port sourcing (IOH) 10mA I2C bus clock (SCL) speed 1MHz

8.2.2 Detailed Design Procedure

The pull-up resistors, R P, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all targets on the I 2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL: R p m i n = V CC − V OL max I O L (1) The maximum pull-up resistance is a function of the maximum rise time, t r (120ns for fast-mode-plus operation, fSCL = 1MHz) and bus capacitance, Cb: R p m ax = t r 0.8473 × C b (2) The maximum bus capacitance for an I 2C bus must not exceed 400pF for standard-mode or fast-mode operation, or 550pF for fast-mode-plus. The bus capacitance can be approximated by adding the capacitance of the TCAL9538, C i for SCL, or C io for SDA. Plus the capacitance of wires, connections, traces, and the capacitance of additional targets on the bus.

8.2.2.1 Minimizing ICC When I/Os Control LEDs

As shown in Figure 8-2, normally I/Os are connected to VCC through a resistor when the I/Os are used to control LEDs. For a P-port configured as an input, current consumption increases as V I becomes lower than V CC. The LEDs are diodes with threshold voltage V T, and are off when a P-port is configured as an input, but the voltages at the P-port will be equal to VCC minus VT. For battery-powered applications, it is essential that the voltage of P-ports controlling the LEDs is greater than or equal to V CC when the P-ports are configured as input to minimize current consumption. Figure 8-2 shows a high-value resistor in parallel with the LED. Figure 8-3 shows V CC less than the LED supply voltage by at least V T. Both of these methods maintain the I/O V I at or above V CC and prevent additional supply current consumption when the P-port is configured as an input and the LED is off. LEDLEDxVCC 100 kΩVCC Figure 8-2. High-Value Resistor in Parallel with LED TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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1.8 V 3.3 V LEDx VCC Figure 8-3. Device Supplied by a Lower Voltage

8.2.3 Application Curves

Standard-mode: fSCL = 100kHz tr = 1 µs Fast-mode: fSCL = 400kHz tr = 300ns Fast-mode plus: fSCL = 1MHz tr = 120ns Figure 8-4. Maximum Pullup Resistance (Rp(max)) vs Bus Capacitance (Cb) www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCAL9538

8.3 Power Supply Recommendations

8.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCAL9538 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. Figure 8-5 and Figure 8-6 shows the two types of power-on reset. VCC Ramp-Up Re-Ramp-Up Time□to□Re-Ramp Time Ramp-Down VCC_RT VCC_RTVCC_FT VCC_TRR_GND Figure 8-5. V is Lowered Below 0.2V or 0V and Then Ramped Up VCC Ramp-Up Time□to□Re-Ramp Time Ramp-Down VIN drops□below□POR□levels VCC_RTVCC_FT VCC_TRR_VPOR50 Figure 8-6. V is Lowered Below the POR Threshold, then Ramped Back Up Table 8-2 lists the performance of the power-on reset feature for both types of power-on reset. Table 8-2. Recommended Supply Sequencing and Ramp Rates PARAMETER(1) (2) MIN TYP MAX UNIT tFT Fall rate See Figure 8-5 0.1 2000 ms tRT Rise rate See Figure 8-5 0.1 2000 ms tTRR_GND Time to re-ramp (when VCC drops to GND) See Figure 8-5 1 μs tTRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50mV) See Figure 8-6 1 μs VCC_GH Level that V can glitch down to, but not cause a functional disruption when V = 1μs See Figure 8-7 1.0 V tGW Glitch width that will not cause a functional disruption when V = 0.5 × VCCx See Figure 8-7 10 μs VPORF Voltage trip point of POR on falling VCC 0.6 V VPORR Voltage trip point of POR on rising VCC 1.0 V (1) TA = 25°C (unless otherwise noted). (2) Not tested. Specified by design. Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (V CC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. For more information on how to measure these specifications, see Figure 8-7 and Table 8-2. TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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8.4 Layout

8.4.1 Layout Guidelines

For device reliability, follow common printed circuit board (PCB) layout practices. Additional concerns related to high-speed data transfer, such as matched impedance and differential pairs, are not a concern for I 2C signal speeds. It is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces in all PCB layouts. Bypass and decoupling capacitors are commonly used to control the voltage on the supply pins. Using a larger capacitor provides additional power in the event of a short power supply glitch, and using a smaller capacitor filters out high-frequency ripple. These capacitors should be placed as close to the TCAL9538 as possible. Figure 8-9 shows these best practices. For the layout example provided in Figure 8-9 , it is possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power and ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to power or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 8-9 .

8.4.2 Layout Example

8 GND 9P4

Figure 8-9. TCAL9538 Layout TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 www.ti.com

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9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2023) to Revision B (May 2025) Page

• Updated Feature from "Hardware address pin allows two devices" to "Hardware address pin allows Changes from Revision * (November 2022) to Revision A (November 2023) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TCAL9538 SCPS280B – NOVEMBER 2022 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TCAL9538

www.ti.com 15-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCAL9538DTUR Active Production X2QFN (DTU) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 NJ TCAL9538DTUR.A Active Production X2QFN (DTU) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 NJ TCAL9538PWR Active Production TSSOP (PW) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL9538 TCAL9538PWR.A Active Production TSSOP (PW) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL9538 TCAL9538RSVR Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 9538 TCAL9538RSVR.A Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 9538 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 15-Jul-2026 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCAL9538DTUR X2QFN DTU 16 3000 189.0 185.0 36.0 TCAL9538PWR TSSOP PW 16 3000 353.0 353.0 32.0 TCAL9538RSVR UQFN RSV 16 3000 189.0 185.0 36.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. UQFN - 0.55 mm max heightRSV 16 ULTRA THIN QUAD FLATPACK - NO LEAD1.8 x 2.6, 0.4 mm pitch 4231225/A

www.ti.com PACKAGE OUTLINE C 1.85 1.75 2.65 2.55 0.55 0.45 0.05 0.00 2X 1.2 12X 0.4 2X 1.2 15X 0.45 0.35 16X 0.25 0.15 0.55 0.45 (0.13) TYP UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 0.05 C

0.07 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 ° X 0.1) SYMM SYMM 5 8 1316 SCALE 5.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.4) (R0.05) TYP

0.05 MAX

0.05 MIN

15X (0.6) 16X (0.2) (1.6) (2.4) (0.7) UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X SEE SOLDER MASK DETAIL 5 8 1316 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 15X (0.6) 16X (0.2) 12X (0.4) (1.6) (2.4) (R0.05) TYP (0.7) UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 25X SYMM SYMM 5 8 1316

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 0.4 0.3 1.2

0.4 TYP

1.2 (0.115) TYP (0.115) TYP 16X 0.22 0.12 (0.1) (0.25) B 1.65 1.55 A 1.65 1.55 4228238/B 03/2022 X2QFN - 0.4 mm max heightDTU0016A PLASTIC QUAD FLATPACK - NO LEAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is for Embedded Application only. PicoStar is a trademark of Texas Instruments. PIN A1 INDEX AREA SEATING PLANE 0.05 C 0.05 C SCALE 8.000 PIN 1 ID SYMM SYMM 1 2 3 4 A B C D

www.ti.com EXAMPLE BOARD LAYOUT (0.4) TYP (0.4) TYP (1.2) TYP (1.2) TYP 16X ( 0.17) (R0.05) TYP 0.0325 MAX 0.0325 MIN 4228238/B 03/2022 X2QFN - 0.4 mm max heightDTU0016A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:50X 1 2 3 4 A B C D NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK OPENING SOLDER MASK DEFINED EXPOSED METAL METAL UNDER SOLDER MASK

www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP (1.2) TYP (1.2) TYP 16X ( 0.17) (R0.05) TYP 4228238/B 03/2022 X2QFN - 0.4 mm max heightDTU0016A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.0625 mm THICK STENCIL SCALE:50X 1 2 3 4 A B C D

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