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TCAL6416RADTOR

Texas Instruments

TCAL6416R 16-Bit Translating I2C-Bus, SMBus I/O Expander with Interrupt Output, Reset Input, and Sticky Registers for Agile I/O Configuration REVISED SEPTEMBER 2025

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TCAL6416R 16-Bit Translating I2C-Bus, SMBus I/O Expander with Interrupt Output, Reset Input, and Sticky Registers for Agile I/O Configuration

1 Features

Operating power-supply voltage range of 1.08V to 3.6V
Allows bidirectional voltage-level translation and GPIO expansion between 1.2V, 1.8V, 2.5V, and 3.3V I2C bus and p-ports
Low standby current consumption of 1µA typical at 1.8V
1MHz fast mode plus I2C bus
Hardware address pin allows two devices on the same I2C, SMBus bus
Active-low reset input (RESET) – Sticky registers retain values when device is reset with RESET – I2C functional state machine is reset
Open-drain active-low interrupt output (INT)
Input or output configuration register
Polarity inversion register
Configurable I/O drive strength register
10kΩ pull-up and pull-down resistor configuration register
Internal power-on reset
Software reset call support
Noise filter on SCL or SDA inputs
Latched outputs with high-current drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100mA per JESD 78, class II
ESD protection exceeds JESD 22 – 4000V Human-body model (A114-A) – 1000V Charged-device model (C101)

2 Applications

Servers
Routers (telecom switching equipment)
Personal computers
Personal electronics
Industrial automation
Gaming consoles
Products with GPIO-limited processors

3 Description

The TCAL6416R provides general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol. The device operates with a power supply voltage ranging from 1.08V to 3.6V on the I2C bus side (VCCI), and a power supply voltage ranging from 1.08V to 3.6V on the P- port side (VCCP). The device supports 100kHz (standard-mode), 400kHz (fast-mode), and 1MHz (fast-mode-plus) I2C clock frequencies. I/O expanders, such as the TCAL6416R, provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and so on. The TCAL6416R has Agile I/O ports which include additional features designed to enhance the I/O performance in terms of speed, power consumption and EMI. The additional features are: programmable output drive strength, programmable pull-up and pull- down resistors, latchable inputs, maskable interrupt, interrupt status register, and programmable open- drain or push-pull outputs. The RESET pin only resets the I 2C state machine when stuck to regain access to the I 2C. I/O pins and sticky registers retain the last configured state while the I2C is being re-initialized.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TCAL6416R DTO (X2QFN, 24) 2mm × 2mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TCAL6416R I2C or SMBus Controller (processor) SDA SCL INT P10 P11 P12 P13 VCCI ADDR GND VCCP P14 P15 P16 P17 P00 P01 P02 P03 P04 P05 P06 P07 RESET Peripheral Devices RESET, ENABLE, or control inputs INT or status outputs LEDs Keypad Simplified Schematic TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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4 Pin Configuration and Functions

A B C D E Not to scale RESET VCCI VCCP SCL ADDR P00 INT SDA P17 P02 P03 P01 P16 P15 P04 P07 P10 P14 P13 P05 P06 GND P11 P12 Figure 4-1. DTO Package, 24-Pin X2QFN (Top View) www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCAL6416R

Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. INT B3 O Interrupt output. Connect to VCCI or VCCP through a pull-up resistor VCCI A2 — Supply voltage of I2C bus. Connect directly to the supply voltage of the external I2C controller RESET A1 I Active-low reset input. Connect to VCCI through a pull-up resistor, if no active connection is used P00 B1 I/O P-port input/output (push-pull design structure). At power on, P00 is configured as an input P01 C3 I/O P-port input/output (push-pull design structure). At power on, P01 is configured as an input P02 C1 I/O P-port input/output (push-pull design structure). At power on, P02 is configured as an input P03 C2 I/O P-port input/output (push-pull design structure). At power on, P03 is configured as an input P04 D1 I/O P-port input/output (push-pull design structure). At power on, P04 is configured as an input P05 E1 I/O P-port input/output (push-pull design structure). At power on, P05 is configured as an input P06 E2 I/O P-port input/output (push-pull design structure). At power on, P06 is configured as an input P07 D2 I/O P-port input/output (push-pull design structure). At power on, P07 is configured as an input GND E3 — Ground P10 D3 I/O P-port input/output (push-pull design structure). At power on, P10 is configured as an input P11 E4 I/O P-port input/output (push-pull design structure). At power on, P11 is configured as an input P12 E5 I/O P-port input/output (push-pull design structure). At power on, P12 is configured as an input P13 D5 I/O P-port input/output (push-pull design structure). At power on, P13 is configured as an input P14 D4 I/O P-port input/output (push-pull design structure). At power on, P14 is configured as an input P15 C5 I/O P-port input/output (push-pull design structure). At power on, P15 is configured as an input P16 C4 I/O P-port input/output (push-pull design structure). At power on, P16 is configured as an input P17 B5 I/O P-port input/output (push-pull design structure). At power on, P17 is configured as an input ADDR A5 I Address input. Connect directly to VCCP or ground SCL A4 I Serial clock bus. Connect to VCCI through a pull-up resistor SDA B4 I/O Serial data bus. Connect to VCCI through a pull-up resistor VCCP A3 — Supply voltage of TCAL6416R for P-ports (1) I = input, O = output TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCI, VCCP Supply voltage –0.5 4 V VI Input voltage(2) –0.5 4 V VO Output voltage(2) –0.5 4 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input-output clamp current P port VO < 0 or VO > VCCP ±20 mA SDA VO < 0 or VO > VCCI ±20 IOL Continuous output low current(3) P port VO = 0 to VCCP 50 mA SDA VO = 0 to VCCI 25 IOH Continuous output high current(3) P port VO = 0 to VCCP –50 mA ICC Continuous current through GND –200 mA ICC Continuous current through VCCP 160 mA Continuous current through VCCI 10 TJ Junction temperature 130 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) Connecting an IO pin directly to GND is not allowed if this pin is set as output, because this will generate >150mA current which could damage the device. We recommend a >10kΩ pull down resistor connected to IO pin if user wants to connect the IO pin to GND.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±4000 V Charged device model (CDM), per ANSI/ESDA/ JEDEC specification JS-002, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCAL6416R

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCI, VCCP Supply voltage 1.08 3.6 V VIH High-level input voltage SCL, SDA, RESET 0.7 * VCCI 3.6 V P00-P17, ADDR 0.7 * VCCP 3.6 VIL Low-level input voltage SCL, SDA, RESET -0.5 0.3 * VCCI V P00-P17, ADDR -0.5 0.3 * VCCP V IOH High-level output current (VCCP - VOH ≤ 0.3V) P00-P17 –10 mA IOH (Total of all ports) High-level output current (VCCP - VOH ≤ 0.3V) P00-P17 –160 mA IOL Low-level output current (VOL ≤ 0.3V) P00-P17 25 mA IOL (Total of all ports) Low-level output current (VOL ≤ 0.3V) P00-P17 160 mA TA Ambient temperature –40 125 °C TPCB Board temperature (measured 1mm away from the device) –40 120 °C TJ Junction temperature 125 °C

5.4 Thermal Information

THERMAL METRIC (1) Package UNITDTO (X2QFN) PINS RθJA Junction-to-ambient thermal resistance 150.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.1 °C/W RθJB Junction-to-board thermal resistance 89.4 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 89.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCP MIN TYP MAX UNIT VIK Input diode clamp voltage II = –18mA 1.08V to 3.6V –1.2 V VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 0.85 1.0 V VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.6 0.75 V VOH P-port high-level output voltage IOH = –8mA; CC-XX = 11b 1.08V 0.8 V 1.65V 1.4 2.3V 2.1 3V 2.8 IOH = –2.5mA & CC-XX = 00b; IOH = –5mA & CC-XX = 01b; IOH = –7.5mA & CC-XX = 10b; IOH = –10mA & CC-XX = 11b; 1.08V 0.75 1.65V 1.4 2.3V 2.1 3V 2.8 VOL Low-level output voltage P ports IOL = 8mA; CC-XX = 11b 1.08V 0.2 V 1.65V 0.15 2.3V 0.1 3.0V 0.1 P ports IOL = 2.5mA and CC-XX = 00b; IOL = 5mA and CC-XX = 01b; IOL = 7.5mA and CC-XX = 10b; IOL = 10mA and CC-XX = 11b; 1.08V 0.25 V 1.65V 0.15 2.3V 0.1 3.0V 0.1 IOL Low-level output current SDA VOL = 0.4V 1.08V to 3.6V mA INT VOL = 0.4V 4 II Input leakage current P ports VI = VCC or GND 1.08V to 3.6V ±1 µAVI = 3.6V 0V ±1 II Input leakage current SCL, SDA, RESET VI = VCC or GND 1.08V to 3.6V ±1 II Input leakage current ADDR VI = VCC or GND 1.08V to 3.6V ±1 µA www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCAL6416R

5.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCP MIN TYP MAX UNIT ICC (ICCI + ICCP) Quiescent current Operating mode (400kHz) SDA, RESET = VCCI, P port, ADDR = VCCP or GND, I/O = inputs, fSCL = 400kHz, –40°C < TA ≤ 85°C 3.6V 7 15 µA 2.7V 5 11 1.95V 4 8 1.32V 2 6 SDA, RESET = VCCI, P port, ADDR = VCCP or GND, I/O = inputs, fSCL = 400kHz, 85°C < TA ≤ 125°C 3.6V 7 24 µA 2.7V 5 18 1.95V 4 14 1.32V 2 11 Operating mode (1MHz) SDA, RESET = VCCI, P port, ADDR = VCCP or GND, I/O = inputs, fSCL = 1MHz, –40°C < TA ≤ 85°C 3.6V 34 µA 2.7V 24 1.95V 18 1.32V 12 SDA, RESET = VCCI, P port, ADDR = VCCP or GND, I/O = inputs, fSCL = 1MHz, 85°C < TA ≤ 125°C 3.6V 42 µA 2.7V 30 1.95V 22 1.32V 16 Standby mode SCL, SDA, RESET = VCCI, P port, ADDR = VCCP or GND, I/O = inputs, IO = 0, fSCL = 0kHz, –40°C < TA ≤ 85°C 3.6V 1.5 4 µA 2.7V 1.2 3 1.95V 0.6 3 1.32V 0.6 3 SCL, SDA, RESET = VCCI, P port, ADDR = VCCP or GND, I/O = inputs, IO = 0, fSCL = 0kHz, 85°C < TA ≤ 125°C 3.6V 14 µA 2.7V 10 1.95V 8 1.32V 6 Rpu(int) internal pull-up resistance P port 7 10 14 kΩ Rpd(int) internal pull-down resistance kΩ CI Input pin capacitance SCL VI = VCC or GND 1.08V to 3.6V 2.5 5 pF CIO Input-output pin capacitance SDA VIO = VCC or GND 1.08V to 3.6V 6 8 pF P port VIO = VCC or GND 1.08V to 3.6V 6 8.5

5.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT tw Reset pulse duration 80 ns tREC Reset recovery time 0 ns tRESET Time to reset 400 ns P-Ports tPH Minimum pulse width on P-Port that causes an interrupt 30 ns TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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5.7 I2C Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT I2C Bus - Standard Mode fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10pF to 400pF bus 300 ns tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capacitive load 400 pF I2C Bus - Fast Mode fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns ticf I2C input fall time 20 × (VCC / 5.5V) 300 ns tocf I2C output fall time 10pF to 400pF bus 20 × (VCC / 5.5V) 300 ns tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 µs tvd(data) Valid data time SCL low to SDA output valid 0.9 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 µs Cb I2C bus capacitive load 400 pF I2C Bus - Fast Mode Plus fscl I2C clock frequency 0 1000 kHz tsch I2C clock high time 0.26 µs tscl I2C clock low time 0.5 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 50 ns tsdh I2C serial-data hold time 0 ns www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCAL6416R

5.7 I2C Bus Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT ticr I2C input rise time 120 ns ticf I2C input fall time 20 × (VCC / 5.5V) 120 ns tocf I2C output fall time 10pF to 550pF bus 20 × (VCC / 5.5V) 120 ns tbuf I2C bus free time between stop and start 0.5 µs tsts I2C start or repeated start condition setup 0.26 µs tsth I2C start or repeated start condition hold 0.26 µs tsps I2C stop condition setup 0.26 µs tvd(data) Valid data time SCL low to SDA output valid 0.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.45 µs Cb I2C bus capacitive load 550 pF

5.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT tiv Interrupt valid time P port INT 1 µs tir Interrupt reset delay time SCL INT 1 µs tpv Output data valid time SCL P port 400 ns tps Input data setup time P port SCL 0 ns tph Input data hold time P port SCL 300 ns

5.9 Typical Characteristics

TA = 25°C (unless otherwise noted) Temperature (C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 3.6V VCCP = 3.3V VCCP = 2.5V VCCP = 1.8V VCCP = 1.2V Figure 5-1. Supply Current vs Temperature - FM mode Temperature (C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 3.6V VCCP = 3.3V VCCP = 2.5V VCCP = 1.8V VCCP = 1.2V Figure 5-2. Supply Current vs Temperature - FM+ mode TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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5.9 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) Temperature (C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 3.6V VCCP = 3.3V VCCP = 2.5V VCCP = 1.8V VCCP = 1.2V VCCP = 1.08V Figure 5-3. Standby Supply Current vs Temperature VCCP - Supply Voltage (V) ICC - Supply Current (µA) 125C 85C 25C −40C Figure 5-4. Supply Current vs Supply Voltage - FM mode VCCP - Supply Voltage (V) ICC - Supply Current (µA) 125C 85C 25C −40C Figure 5-5. Supply Current vs Supply Voltage - FM+ mode VOL - Output Low Voltage (V) IOL - Sink Current (mA) 125C 85C 25C -40C Figure 5-6. I/O Sink Current vs Output Low Voltage, VCCP = 1.08V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 125C 85C 25C -40C Figure 5-7. I/O Sink Current vs Output Low Voltage, VCCP = 1.2V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 120 140 160 180 200 125C 85C 25C -40C Figure 5-8. I/O Sink Current vs Output Low Voltage, VCCP = 1.8V www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCAL6416R

TA = 25°C (unless otherwise noted) VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 125 150 175 200 225 250 275 125C 85C 25C -40C Figure 5-9. I/O Sink Current vs Output Low Voltage, VCCP = 2.5V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 125 150 175 200 225 250 275 300 325 125C 85C 25C -40C Figure 5-10. I/O Sink Current vs Output Low Voltage, VCCP = 3.3V VOL - Output Low Voltage (V) IOL - Sink Current (mA) 100 125 150 175 200 225 250 275 300 325 125C 85C 25C -40C Figure 5-11. I/O Sink Current vs Output Low Voltage, VCCP = 3.6V Temperature (C) VOL - Output Low Voltage (mV) -40 -25 -10 5 20 35 50 65 80 95 110 125 VCCP = 1.2V, I OL = 10 mA VCCP = 3.3V, I OL = 10 mA VCCP = 1.2V, IOL = 1 mA VCCP = 3.3V, I OL = 1 mA Figure 5-12. I/O Low Voltage vs Temperature VCCP - VOH (V) Source Current (mA) 125C 85C 25C -40C Figure 5-13. I/O Source Current vs Output High Voltage , VCCP = 1.08V VCCP - VOH (V) Source Current (mA) 125C 85C 25C -40C Figure 5-14. I/O Source Current vs Output High Voltage, VCCP = 1.2V TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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TA = 25°C (unless otherwise noted) VCCP - VOH (V) Source Current (mA) 100 110 120 130 125C 85C 25C -40C Figure 5-15. I/O Source Current vs Output High Voltage, VCCP = 1.8V VCCP - VOH (V) Source Current (mA) 100 125 150 175 125C 85C 25C -40C Figure 5-16. I/O Source Current vs Output High Voltage, VCCP = 2.5V VCCP - VOH (V) Source Current (mA) 100 120 140 160 180 200 220 125C 85C 25C -40C Figure 5-17. I/O Source Current vs Output High Voltage, VCCP = 3.3V VCCP - VOH (V) Source Current (mA) 120 150 180 210 240 125C 85C 25C -40C Figure 5-18. I/O Source Current vs Output High Voltage, VCCP = 3.6V Temperature (C) VCCP - VOH (V) -40 -25 -10 5 20 35 50 65 80 95 110 125 0.02 0.04 0.06 0.08 0.1 0.12 0.14 VCCP = 1.2V, I SOURCE = -10 mA VCCP = 3.3V, I SOURCE = -10 mA VCCP = 1.2V, ISOURCE = -1 mA VCCP = 3.3V, I SOURCE = -1 mA Figure 5-19. I/O High Voltage vs Temperature www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCAL6416R

6 Parameter Measurement Information

RL = 1 k/c87 VCCI CL = 50 pF (see Note A) tbuf ticr tsth tsds tsdh ticf ticr tscl tsch tststvd(ack) tvd(data) 0.3 /c215VCC Stop Condition tsps Repeat Start ConditionStart or Repeat Start Condition SCL SDA Start Condition (S) Address Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) Three Bytes for Complete Device Programming SDA LOAD CONFIGURATION VOLTAGE WAVEFORMS ticf Stop Condition (P) tsp DUT SDA 0.7 /c215VCC 0.3 /c215VCC 0.7 /c215VCC R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Address Bit 1 Address Bit 6 BYTE DESCRIPTION

1 I 2C address

2, 3 P-port data A. CL includes probe and jig capacitance. tocf is measured with CL of 10pF or 400pF. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. All parameters and waveforms are not applicable to all devices. Figure 6-1. I2C Interface Load Circuit and Voltage Waveforms TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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A A A A S 0 1 0 0 0 0 AD DR 1 Data 1 1 PData 2 Start Condition 8 Bits (One Data Byte) From Port Data From PortTarget Address R/W 87654321 Address Data 1 Data 2 INT B B A A Pn INT R/W AINT SCL View B−BView A−A ACK From Target ACK From Target INTERRUPT LOAD CONFIGURATION VCCI R = 4.7 kL Ω C = 100 pFL (see Note A) DUT INT

0.7 V× CCI

0.3 V× CCI

0.5 V× CCI

0.5 V× CCP

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. All parameters and waveforms are not applicable to all devices. Figure 6-2. Interrupt Load Circuit and Voltage Waveforms www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCAL6416R

WRITE MODE (R/ = 0)W P0 ASCL P3 READ MODE (R/ = 1)W DUT P-PORT LOAD CONFIGURATION Pn 500 Ω 500 Ω

2 V× CCP

0.7 V× CCP

C = 50 pFL (see Note A) Target ACK tpv (see Note B) Pn Pn tps tph A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 6-3. P-Port Load Circuit and Timing Waveforms TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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R = 1 kL Ω C = 50 pFL (see Note A) DUT SDA DUT P-PORT LOAD CONFIGURATION Pn 500 Ω 500 Ω 2 x VCCP C = 50 pFL (see Note A)

0.3 V´ CCI

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, tr/tf ≤ 30ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 6-4. Reset Load Circuits and Voltage Waveforms www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCAL6416R

7 Detailed Description

7.1 Overview

The TCAL6416R supports voltage translation over a wide supply voltage range. This allows the device to interface with modern processors on the I 2C side, where supply levels are lower to conserve power. In contrast to the dropping power supplies of processors, some PCB components (such as LEDs) still require a higher voltage power supply. The VCCI pin is the power supply for the I 2C bus, and therefore the pull-up resistors connected to the SCL, SDA, and RESET pins should be terminated at V CCI. The INT output has an open-drain structure and requires an external pull-up resistor to V CCP or VCCI depending on the application. The V CCP pin is the power supply for the P-ports. If the external pull-up resistors are used on any P-port, or if the LEDs are driven by any P-port, then the one or more of the resistors or LEDs connected to P00-P07 and P10-P17 should be terminated at V CCP. The device P-ports configured as outputs have the ability to sink up to 25mA for directly driving LEDs, but the current must be limited externally with an additional resistance. The TCAL6416R digital core consists of 8-bit data registers, which allow the user to configure the I/O port characteristics. At power-up or after a software reset call, the I/Os are configured as inputs. However, the system controller can configure the I/Os as either inputs or outputs by writing to the Configuration registers. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. The system controller can read all registers. Additionally, the TCAL6416R has Agile I/O functionality, which is specifically targeted to enhance the I/O ports. The Agile I/O features and registers include programmable output drive strength, programmable pull-up and pull-down resistors, latchable inputs, maskable interrupts, interrupt status register, and programmable open-drain or push-pull outputs. These configuration registers improve the I/O by increasing flexibility and allowing the user to optimize their design for power consumption, speed, and EMI. Other features of the device include an interrupt that is generated on the INT pin whenever an input port changes state. The device can be reset to its default state by issuing a software reset command or by cycling power to the device and causing a power-on reset. The ADDR hardware selectable address pin allows two TCAL6416R devices to be connected to the same I2C bus. The TCAL6416R open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed. The INT pin can be connected to the interrupt input of a processor. By sending an interrupt signal on this line, the device can inform the processor if there is incoming data on the remote I/O ports without having to communicate through the I2C bus. Thus, the device can remain a simple target device. The system controller can re-initialize I 2C/SMBus state machine in the event of a timeout or other improper operation by asserting a low on the RESET input pin without resetting the sticky registers to default values. One hardware pin (ADDR) can be used to program and vary the fixed I 2C address, and allow two devices to share the same I2C bus or SMBus. TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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7.2 Functional Block Diagrams

16 Bits I/O

A. All I/Os are set to inputs at power up. Figure 7-1. Logic Diagram (Positive Logic) Interrupt Mask VCCP Output Port Register Data Configuration Register D Q CK Q Data from Shift Register Write Configuration Pulse Output Port Register D Q CKWrite Pulse Polarity Inversion Register D Q CK Data from Shift Register Write Polarity Pulse Input Port Register D Q CKRead Pulse Input Port Register Data FF Data from Shift Register FF FF FF GND to INT Pull-Up/Pull-Down Control ESD Protection Diode 10 k VCCP Input Port Latch D Q EN Latch Read Pulse Input Latch Register D Q CK FF Data from Shift Register Write Input Latch Pulse P10 to P17 P00 to P07 A. On power up or after a software reset call, all registers return to default values. Figure 7-2. Simplified Schematic of P00 to P17 www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCAL6416R

7.3 Feature Description

7.3.1 Voltage Translation

Table 7-1 lists all of the optional voltage supply level combinations for the I 2C bus (VCCI) and the P-ports (V CCP) supported by the TCAL6416R. Table 7-1. Voltage Translation VCCI (SDA AND SCL OF I2C Controller) (V) VCCP (P-PORTS) (V) 1.2 1.2 1.2 1.8 1.2 2.5 1.2 3.3 1.8 1.2 1.8 1.8 1.8 2.5 1.8 3.3 2.5 1.2 2.5 1.8 2.5 2.5 2.5 3.3 3.3 1.2 3.3 1.8 3.3 2.5 3.3 3.3

7.3.2 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off (see Section 7.2), which creates a high- impedance input. The input voltage may be raised above the supply voltage to a maximum of 3.6V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either supply or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.

7.3.3 Adjustable Output Drive Strength

The output drive strength registers allow the user to control the drive level of the GPIO. Each GPIO can be configured independently to one of the four possible current levels. By programming these bits the user is changing the number of transistor pairs or 'fingers' that drive the I/O pad. Figure 7-3 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the output drive strength register. When the output drive strength register bits are programmed to 01b, then only two of the fingers are active, reducing the current drive capability by 50%. TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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PMOS_EN0 PMOS_EN1 PMOS_EN2 PMOS_EN3 NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 Output Port Register Current Control Register PMOS_EN[3:0] NMOS_EN[3:0] Figure 7-3. Simplified Output Stage A function of the output drive selection causes a peak current to occur when the output switches. Reducing the current drive capability may reduce the system noise that occurs. This peak current runs through the supply and GND package inductance and creates a noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues without the need of additional external components.

7.3.4 Interrupt Output (INT)

Any rising or falling edge of the port inputs in the input mode generates an interrupt, provided the interrupt feature is unmasked. After time t iv, the INT signal is valid. Resetting the interrupt circuit is achieved when data on the port is changed back to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. The INT output has an open-drain structure and requires an external pull-up resistor to V CC if the interrupt feature is required; otherwise, it may be left floating.

7.3.5 Reset Input (RESET)

The RESET input is asserted to initialize the I 2C state machine while keeping the V CCP supply at the operating level. A state machine reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCAL6416R registers are sticky and retain their last configured state while the I 2C state machine initializes, when RESET is toggled. The RESET input low reverts the Address Pointer (Command byte) to the default value. www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCAL6416R

This input requires a pull-up resistor to VCCI, if no active connection is used. See Section 7.3.6 on how to reset the registers without power cycling the TCAL6416R.

7.3.6 Software Reset Call

The software reset call is a command sent from the controller on the I 2C bus that instructs all devices that support the command to be reset to the power-up default state. To function as expected, the I 2C bus must be functional, and no devices can be hanging the bus. The software reset call is defined as the following steps: 1. The I2C bus controller sends a start condition. 2. The address used is the reserved general call I2C bus address '0000 0000' with the R/W bit set to 0. The byte sent is 0x00. 3. Any devices supporting the general call functionality will ACK. If the R/W bit is set to 1 (read), then the device will NACK. 4. When the general call address is acknowledged, the controller sends only 1 byte of data equal to 0x06. If the data byte is any other value, then the device does not acknowledge or reset. If more than 1 byte is sent, then no more bytes is acknowledged, and the device ignores the I2C message considering as invalid. 5. After the 1 byte of data (0x06) is sent, the controller sends a STOP condition to end the Software Reset sequence. The device ignores a repeated START condition and no reset is performed. When the previous steps are completed successfully, the device performs a reset. This clears all register values back to power-on defaults.

7.4 Device Functional Modes

7.4.1 Power-On Reset

When power (from 0V) is applied to V CCP, an internal power-on reset holds the TCAL6416R in a reset condition until the supply has reached V POR. At that time, the reset condition is released, and the TCAL6416R registers and I2C/SMBus state machine initializes to their default states. After that, V CCP must be lowered to below V PORF and back up to the operating voltage for a power-reset cycle.

7.5 Programming

7.5.1 I2C Interface

The bidirectional I 2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfer can only be initiated when the bus is not busy. A controller initiates I 2C communication with this device by sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 7-4). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address input of the target device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 7-5). The controller sends a Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high (see Figure 7-4). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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7.6 Register Maps

7.6.1 Device Address

Figure 7-7 shows the address of the TCAL6416R. Device Address 1 0 0 0 0 AD DR R/W Fixed Programmable Figure 7-7. TCAL6416R Address Table 7-3. Address Reference ADDR I2C BUS TARGET ADDRESS L 32 (decimal), 20 (hexadecimal) H 33 (decimal), 21 (hexadecimal) The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.

7.6.2 Multiple Power-Up Default Conditions

There are two additional devices under the TCAL6416R which have different register start-up values. This is done to assist systems with different power-up requirements and accommodate their initialization software. Table 7-4 lists the names of the devices and changes in their start-up values. TCAL6416RADTOR (referenced as TCAL6416RA on Section 7.6.3 and Section 7.64 ) has updated power-up values for Output Port and Configuration registers. TCAL6416RBDTOR (referenced as TCAL6416RB on Section 7.6.3 and Section 7.64) has updated power-up values for Polarity Inversion, Pull-Up/Pull-Down Enable and Interrupt Mask registers. Table 7-4. Devices and their start-up values Orderable Part Number Changes to Register Start-Up Values Command Byte (Hex) Changes TCAL6416RDTOR Uses default power-up values N/A TCAL6416RADTOR Output Port 0 & 1 Configuration 0 & 1 02 & 03 06 & 07 TCAL6416RBDTOR Polarity Inversion 0 & 1 Pull-Up/Pull-Down Enable 0 & 1 Interrupt Mask 0 & 1 04 & 05 46 & 47 4A & 4B TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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7.6.3 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which is stored in the control register in the TCAL6416R. The lower three bits of this data byte reflect the internal registers (input, output, polarity inversion, or configuration) that are affected. Bit 6 in conjunction with the lower four bits of the Command byte are used to point to the extended features of the device (Agile IO). The command byte is sent only during a write transmission. Once a new command has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Upon power-up, hardware reset, or software reset, the control register defaults to 00h. The RESET input low reverts the Address Pointer (Command byte) to default values. B2 B1 B0B5 B4 B3B7 B6 Figure 7-8. Control Register Bits Table 7-5. Command Byte CONTROL REGISTER BITS COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT POWER-UP TCAL6416R A POWER-UP TCAL6416R BB7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 00 Input Port 0 Read byte xxxx xxxx xxxx xxxx xxxx xxxx 0 0 0 0 0 0 0 1 01 Input Port 1 Read byte xxxx xxxx xxxx xxxx xxxx xxxx 0 0 0 0 0 0 1 0 02 Output Port 0 Read/write byte 1111 1111 0000 0000 1111 1111 0 0 0 0 0 0 1 1 03 Output Port 1 Read/write byte 1111 1111 0000 0000 1111 1111 0 0 0 0 0 1 0 0 04 Polarity Inversion 0 Read/write byte 0000 0000 0000 0000 1111 1111 0 0 0 0 0 1 0 1 05 Polarity Inversion 1 Read/write byte 0000 0000 0000 0000 1111 1111 0 0 0 0 0 1 1 0 06 Configuration 0 Read/write byte 1111 1111 0000 0000 1111 1111 0 0 0 0 0 1 1 1 07 Configuration 1 Read/write byte 1111 1111 0000 0000 1111 1111 0 1 0 0 0 0 0 0 40 Output Drive Strength 0 Read/write byte 1111 1111 1111 1111 1111 1111 0 1 0 0 0 0 0 1 41 Output Drive Strength 0 Read/write byte 1111 1111 1111 1111 1111 1111 0 1 0 0 0 0 1 0 42 Output Drive Strength 1 Read/write byte 1111 1111 1111 1111 1111 1111 0 1 0 0 0 0 1 1 43 Output Drive Strength 1 Read/write byte 1111 1111 1111 1111 1111 1111 0 1 0 0 0 1 0 0 44 Input latch register 0 Read/write byte 0000 0000 0000 0000 0000 0000 0 1 0 0 0 1 0 1 45 Input latch register 1 Read/write byte 0000 0000 0000 0000 0000 0000 0 1 0 0 0 1 1 0 46 Pull-up/pull-down enable register 0 Read/write byte 0000 0000 0000 0000 1111 1111 0 1 0 0 0 1 1 1 47 pull-up/pull-down enable register 1 Read/write byte 0000 0000 0000 0000 1111 1111 0 1 0 0 1 0 0 0 48 pull-up/pull-down selection register 0 Read/write byte 1111 1111 1111 1111 1111 1111 0 1 0 0 1 0 0 1 49 pull-up/pull-down selection register 1 Read/write byte 1111 1111 1111 1111 1111 1111 www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCAL6416R

Table 7-5. Command Byte (continued) CONTROL REGISTER BITS COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT POWER-UP TCAL6416R A POWER-UP TCAL6416R BB7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 0 1 0 4A Interrupt mask register 0 Read/write byte 1111 1111 1111 1111 0000 0000 0 1 0 0 1 0 1 1 4B Interrupt mask register 1 Read/write byte 1111 1111 1111 1111 0000 0000 0 1 0 0 1 1 0 0 4C Interrupt status register 0 Read byte 0000 0000 0000 0000 0000 0000 0 1 0 0 1 1 0 1 4D Interrupt status register 1 Read byte 0000 0000 0000 0000 0000 0000 0 1 0 0 1 1 1 1 4F Output port configuration register Read/write byte 0000 0000 0000 0000 0000 0000

7.6.4 Register Descriptions

The TCAL6416R has sticky registers that retain the last values when RESET is asserted low. The registers only revert back to power up default when the device is power cycled, or a software reset call is issued. The input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether Configuration register defines the pin as an input or output. The input port registers are read only. Writes to these registers have no effect. The externally applied logic level determines the default value (X). Before a read operation, a write transmission is sent with the command byte to indicate to the I 2C device that the Input Port register is accessed next. Table 7-6. Registers 0 and 1 (Input Port Registers) (1) BIT I-07 I-06 I-05 I-04 I-03 I-02 I-01 I-00 DEFAULT X X X X X X X X BIT I-17 I-16 I-15 I-14 I-13 I-12 I-11 I-10 DEFAULT X X X X X X X X The output port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 7-7. Registers 2 and 3 (Output Port Registers) BIT O-07 O-06 O-05 O-04 O-03 O-02 O-01 O-00 DEFAULT 1 1 1 1 1 1 1 1 TCAL6416RA 0 0 0 0 0 0 0 0 BIT O-17 O-16 O-15 O-14 O-13 O-12 O-11 O-10 DEFAULT 1 1 1 1 1 1 1 1 TCAL6416RA 0 0 0 0 0 0 0 0 The polarity inversion registers (register 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with 1), then the corresponding port pin polarity is inverted. If a bit in these registers is cleared (written with a 0), then the corresponding port pin's original polarity is retained. Table 7-8. Registers 4 and 5 (Polarity Inversion Registers) BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 P-00 DEFAULT 0 0 0 0 0 0 0 0 TCAL6416RB 1 1 1 1 1 1 1 1 BIT P-17 P-16 P-15 P-14 P-13 P-12 P-11 P-10 TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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Table 7-8. Registers 4 and 5 (Polarity Inversion Registers) (continued) BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 P-00 DEFAULT 0 0 0 0 0 0 0 0 TCAL6416RB 1 1 1 1 1 1 1 1 The configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is set to 1, then the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these registers is cleared to 0, then the corresponding port pin is enabled as an output. Changing a port from an input to an output configuration will cause any interrupt associated with that port to be cleared. Table 7-9. Registers 6 and 7 (Configuration Registers) BIT C-07 C-06 C-05 C-04 C-03 C-02 C-01 C-00 DEFAULT 1 1 1 1 1 1 1 1 TCAL6416RA 0 0 0 0 0 0 0 0 BIT C-17 C-16 C-15 C-14 C-13 C-12 C-11 C-10 DEFAULT 1 1 1 1 1 1 1 1 TCAL6416RA 0 0 0 0 0 0 0 0 The output drive strength registers control the output drive level of the P port GPIO buffers. Each GPIO can be configured independently to the desired output current level by two register control bits. For example, register 0x41h (bits 7 and 6) controls Port P07, register 0x41h (bits 5 and 4) controls port P06, and so forth. The output drive level of the GPIO is programmed 00b = 0.25x drive strength, 01b = 0.5x drive strength, 10b = 0.75x drive strength, or 11b = 1x for full drive strength capability. For more details, see \\. Table 7-10. Registers 0x40h, 0x41h, 0x42h, and 0x43h (Output Drive Strength Registers) BIT CC-03 CC-03 CC-02 CC-02 CC-01 CC-01 CC-00 CC-00 DEFAULT 1 1 1 1 1 1 1 1 BIT CC-07 CC-07 CC-06 CC-06 CC-05 CC-05 CC-04 CC-04 DEFAULT 1 1 1 1 1 1 1 1 BIT CC-13 CC-13 CC-12 CC-12 CC-11 CC-11 CC-10 CC-10 DEFAULT 1 1 1 1 1 1 1 1 BIT CC-17 CC-17 CC-16 CC-16 CC-15 CC-15 CC-14 CC-14 DEFAULT 1 1 1 1 1 1 1 1 The input latch registers enable and disable the input latch feature of the P port GPIO pins. These registers are effective only when the pin is configured as an input port. When an input latch register bit is 0, the corresponding input pin state is not latched. A state change in the corresponding input pin generates an interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. When an input latch register bit is set to 1, the corresponding input pin state is latched. A change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0 and 1). A read of the input port register clears the interrupt. However, if the input pin returns to its initial logic state before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. For example, if the P04 input was at a logic 0 state and then transitions to a logic 1 state followed by returning to the logic 0 state, then the input port 0 register captures this change and an interrupt is generated (if unmasked). When the read is performed on the input port 0 register, the interrupt is cleared, assuming there were no www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCAL6416R

additional inputs that have changed, and bit 4 of the input port 0 register reads '1'. The next read of the input port register bit 4 should now read '0'. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state. A read of the input register reflects only the change of state of the latched input and also clears the interrupt. If the input latch register changes from a latched to a non-latched configuration, the interrupt is cleared if the input logic value returns to its original state. If the input pin is changed from a latched to a non-latched input, then a read from the input port register reflects the current port logic level. If the input pin is changed from a non-latched to a latched input, then the read from the input register reflects the latched logic level. Table 7-11. Registers 0x44h and 0x45h (Input Latch Registers) BIT L-07 L-06 L-05 L-04 L-03 L-02 L-01 L-00 DEFAULT 0 0 0 0 0 0 0 0 BIT L-17 L-16 L-15 L-14 L-13 L-12 L-11 L-10 DEFAULT 0 0 0 0 0 0 0 0 The pull-up/pull-down enable registers allow the user to enable or disable pull-up/pull-down resistors on the GPIO pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the GPIO pins. The resistors are disabled when the GPIO pins are configured as outputs. Use the pull-up/pull-down selection registers to select either a pull-up or pull-down resistor. Table 7-12. Registers 0x46h and 0x47h (Pull-Up/Pull-Down Enable Registers) BIT PE-07 PE-06 PE-05 PE-04 PE-03 PE-02 PE-01 PE-00 DEFAULT 0 0 0 0 0 0 0 0 TCAL6416RB 1 1 1 1 1 1 1 1 BIT PE-17 PE-16 PE-15 PE-14 PE-13 PE-12 PE-11 PE-10 DEFAULT 0 0 0 0 0 0 0 0 TCAL6416RB 1 1 1 1 1 1 1 1 The pull-up/pull-down selection registers allow the user to configure each GPIO to have a pull-up or pull-down resistor by programming the respective register bit. Setting a bit to a logic 1 selects a 10k Ω pull-up resistor for that GPIO pin. Setting a bit to logic 0 selects a 10k Ω pull-down resistor for that GPIO pin. If the pull-up/pull-down feature is disabled through registers 0x46h and 0x47h, then writing to these registers will have no effect on the GPIO pin. Table 7-13. Registers 0x48h and 0x49h (Pull-Up/Pull-Down Selection Registers) BIT PUD-07 PUD-06 PUD-05 PUD-04 PUD-03 PUD-02 PUD-01 PUD-00 DEFAULT 1 1 1 1 1 1 1 1 BIT PUD-17 PUD-16 PUD-15 PUD-14 PUD-13 PUD-12 PUD-11 PUD-10 DEFAULT 1 1 1 1 1 1 1 1 The interrupt mask registers are defaulted to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding bit in the interrupt mask register is set to 1, the interrupt is masked and the interrupt pin is not asserted. If the corresponding bit in the interrupt mask register is set to 0, the interrupt pin is asserted. TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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When an input changes state and the resulting interrupt is masked, setting the interrupt mask register bit to 0 causes the interrupt pin to be asserted. If the interrupt mask bit of an input that is already currently the source of an interrupt is set to 1, the interrupt pin is de-asserted. Table 7-14. Registers 0x4Ah and 0x4Bh (Interrupt Mask Registers) BIT M-07 M-06 M-05 M-04 M-03 M-02 M-01 M-00 DEFAULT 1 1 1 1 1 1 1 1 TCAL6416RB 0 0 0 0 0 0 0 0 BIT M-17 M-16 M-15 M-14 M-13 M-12 M-11 M-10 DEFAULT 1 1 1 1 1 1 1 1 TCAL6416RB 0 0 0 0 0 0 0 0 The interrupt status registers are read only registers used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return to logic 0. Table 7-15. Registers 0x4Ch and 0x4Dh (Interrupt Status Registers) BIT S-07 S-06 S-05 S-04 S-03 S-02 S-01 S-00 DEFAULT 0 0 0 0 0 0 0 0 BIT S-17 S-16 S-15 S-14 S-13 S-12 S-11 S-10 DEFAULT 0 0 0 0 0 0 0 0 The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures the I/O as push-pull (Q1 and Q2 are active. A logic 1 configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended command sequence is to program this register (0x4Fh) before the Configuration register (06 and 07) sets the port pins as outputs. ODEN0 configures Port 0X and ODEN1 configures Port 1X. Table 7-16. Register 0x4Fh (Output Port Configuration Register) BIT Reserved ODEN-1 ODEN-0 DEFAULT 0 0 0 0 0 0 0 0

7.6.5 Bus Transactions

Data is exchanged between the controller and TCAL6416R through write and read commands.

7.6.5.1 Writes

Data is transmitted to the TCAL6416R by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 7-7 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. Twenty-two registers within the TCAL6416R are configured to operate as eleven register pairs. The eleven pairs are input port, output port, polarity inversion, configuration, output drive strength (two 16-bit registers), input latch, pull-up/pull-down enable, pull-up/pulldown selection, interrupt mask, and interrupt status registers. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 7-9 and Figure 7-10). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register pair may be updated independently of the other registers. www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCAL6416R

00 0 0 0 0 0 1 0.7 0.0 Data 11.7 1.0 AS 0 1 0 0 0 0 AD DR 0 P Target Address Command Byte Data to Port 0 Data to Port 1 Start Condition Acknowledge From Target Write to Port Data Out from Port 1 Data Out from Port 0 Data Valid Acknowledge From Target Acknowledge From Target tpv Stop Condition Figure 7-9. Write to Output Port Registers <br/> 1 2SCL 3 4 5 6 7 8 SDA A A A Data 0 Data to Register R/W 00 0 0 0 0 1 1 MSB LSB Data1MSB LSB AS 0 1 0 0 0 0 AD DR 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 P Acknowledge From Target Acknowledge From Target Start Condition Command ByteTarget Address Acknowledge From Target Data to Register Stop Condition Figure 7-10. Write to Configuration Registers

7.6.5.2 Reads

The bus controller must first send the TCAL6416R address with the LSB set to a logic 0 (see Figure 7-7 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte is sent by the TCAL6416R (see Figure 7-11 and Figure 7-12). Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is no limit on the number of data bytes received in one read transmission, but on the final byte received, the bus controller must not acknowledge the data. After a subsequent restart, the command byte contains the value of the next register to be read in the pair. For example, if Input Port 1 was read last before the restart, then the register that is read after the restart is the Input Port 0. 0 0 0 0 AD DR0 1 S 0 A A A R/W A PNA S 1 MSB LSB MSB L SB Target Address Acknowledge From Target Command Byte Data From Upper or Lower Byte of Register Last Byte Data Acknowledge From Target Acknowledge From TargetTarget Address Data From Lower or Upper Byte of Register First Byte Data No Acknowledge From Controller Acknowledge From Controller At this moment, controller transmitter becomes controller receiver, and target receiver becomes target transmitter. 0 0 0 0 AD DR0 1 R/W Stop Condition Figure 7-11. Read From Register TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

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Product Folder Links: TCAL6416R

<br/> SCL SDA INT Start Condition R/W Read From Port Data Into Port Stop Condition ACK From Controller NACK From Controller ACK From Target Data From PortTarget Address Data From Port 1 9 R765432 00 1S 00 0 AD DR 1 A Data 1 Data 4A NA P Data 2 Data 3 Data 4 Data 5 INT is cleared by Read from Port Stop not needed to clear INT tph tps tirtiv A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from P port (see Figure 7-11). Figure 7-12. Read Input Port Register www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCAL6416R

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

TCAL6416R is used in applications where this device is connected as a target to an I 2C controller (processor); the I2C bus may contain any number of other target devices. The TCAL6416R is in a remote location from the controller, placed close to the GPIOs to which the controller needs to monitor or control. A typical application of the TCAL6416R operates with a lower voltage on the controller side (V CCI), and a higher voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of devices such as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured as inputs to receive data from interrupts, alarms, status outputs, or push buttons.

8.2 Typical Application

Figure 8-1 shows an application in which the TCAL6416R can be used. TCAL6416R P00 P01 SCL SDA VCCI SCL SDA P02 P03 GND Target Controller GND VCCI Controlled Switch A B Enable INT VCCP INT 10 k SUBSYSTEM 1 ALARM(1) P04 P05 P06 P07 10 k10 k RESETRESET VCCP P10 P11 P12 P13 P14 P15 P16 P17 VCCI VCCI ADDR Keypad 10 k 10 k (×7) 0.1 μF 0.1 μFGND GND A. Device address configured as 0100000 for this example. B. P00 and P02–P10 are configured as inputs. C. P01 and P11–P17 are configured as outputs. D. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, then a resistor is not needed. Outputs (in the P port) do not need pullup resistors. Figure 8-1. Typical Application Schematic TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

Product Folder Links: TCAL6416R

8.2.1 Design Requirements

Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE I2C input voltage (VCCI) 1.8V P-port input/output voltage (VCCP) 3.6V Output current rating, P-port sinking (IOL) 25mA Output current rating, P-port sourcing (IOH) 10mA I2C bus clock (SCL) speed 1MHz

8.2.2 Detailed Design Procedure

The pull-up resistors, R P, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all targets on the I 2C bus. The minimum pull-up resistance is a function of V, VOL,(max), and IOL: R p m i n = V CC I − V OL max I OL (1) The maximum pull-up resistance is a function of the maximum rise time, t r (120ns for fast-mode-plus operation, fSCL = 1MHz) and bus capacitance, Cb: R p m ax = t r 0.8473 × C b (2) The maximum bus capacitance for an I 2C bus must not exceed 400pF for standard-mode or fast-mode operation, or 550pF for fast-mode-plus. The bus capacitance can be approximated by adding the capacitance of the TCAL6416R, C i for SCL, or C io for SDA. Plus the capacitance of wires, connections, traces, and the capacitance of additional targets on the bus.

8.2.2.1 Minimizing ICC When I/Os Control LEDs

As shown in Figure 8-2 , normally I/Os are connected to V CCP through a resistor when the I/Os are used to control LEDs. For a P-port configured as an input, current consumption increases as V I becomes lower than VCCP. The LEDs are diodes with threshold voltage V T, and are off when a P-port is configured as an input, but the voltages at the P-port will be equal to VCCPCC minus VT. For battery-powered applications, it is essential that the voltage of P-ports controlling the LEDs is greater than or equal to V CCP when the P-ports are configured as input to minimize current consumption. Figure 8-2 shows a high-value resistor in parallel with the LED. Figure 8-3 shows V CCP less than the LED supply voltage by at least V T. Both of these methods maintain the I/O V I at or above V CCP and prevent additional supply current consumption when the P-port is configured as an input and the LED is off. LED LEDx VCCP 100kΩ VCCP Figure 8-2. High-Value Resistor in Parallel with LED www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TCAL6416R

1.8 V 3.3 V LEDx VCCP Figure 8-3. Device Supplied by a Lower Voltage

8.2.3 Application Curves

Standard-mode: fSCL = 100kHz tr = 1 µs Fast-mode: fSCL = 400kHz tr = 300ns Fast-mode plus: fSCL = 1MHz tr = 120ns Figure 8-4. Maximum Pullup Resistance (Rp(max)) vs Bus Capacitance (Cb) TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

Product Folder Links: TCAL6416R

8.3 Power Supply Recommendations

8.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCAL6416R can be reset to its default conditions by using the power-on reset feature. Power-on reset requires the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. Figure 8-5 and Figure 8-6 shows the two types of power-on reset. VCCP Ramp-Up Re-Ramp-Up Time to Re-Ramp Time Ramp-Down VCC_RT VCC_RTVCC_FT VCC_TRR_GND Figure 8-5. VCCP is Lowered Below 0.2V or 0V and Then Ramped Up VCCP Ramp-Up Time to Re-Ramp Time Ramp-Down V drops below POR levelsIN VCC_RTVCC_FT VCC_TRR_VPOR50 Figure 8-6. VCCP is Lowered Below the POR Threshold, then Ramped Back Up Table 8-2 lists the performance of the power-on reset feature for both types of power-on reset. Table 8-2. Recommended Supply Sequencing and Ramp Rates PARAMETER(1) (2) MIN TYP MAX UNIT tFT Fall rate See Figure 8-5 0.1 2000 ms tRT Rise rate See Figure 8-5 0.1 2000 ms tTRR_GND Time to re-ramp (when VCC drops to GND) See Figure 8-5 1 μs tTRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50mV) See Figure 8-6 1 μs VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCP_GW = 1μs See Figure 8-7 1.0 V tGW Glitch width that will not cause a functional disruption when VCCP_GH = 0.5 × VCCx See Figure 8-7 10 μs VPORF Voltage trip point of POR on falling VCC 0.6 V VPORR Voltage trip point of POR on rising VCC 1.0 V (1) TA = 25°C (unless otherwise noted). (2) Not tested. Specified by design. Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (V CC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. For more information on how to measure these specifications, see Figure 8-7 and Table 8-2. www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TCAL6416R

VCC_GH VCC_GW Figure 8-7. Glitch Width and Glitch Height VPOR is critical to the power-on reset. V POR is the voltage level at which the reset condition is released and all the registers and the I 2C/SMBus state machine are initialized to their default states. The value of V POR differs based on the V CCP being lowered to or from 0. For more details on this specification, see Figure 8-8 and Table 8-2. VCCP VPOR VPORF Time POR Time Figure 8-8. VPOR TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

Product Folder Links: TCAL6416R

8.4 Layout

8.4.1 Layout Guidelines

For device reliability, follow common printed circuit board (PCB) layout practices. Additional concerns related to high-speed data transfer, such as matched impedance and differential pairs, are not a concern for I 2C signal speeds. It is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces in all PCB layouts. Bypass and decoupling capacitors are commonly used to control the voltage on the supply pins. Using a larger capacitor provides additional power in the event of a short power supply glitch, and using a smaller capacitor filters out high-frequency ripple. These capacitors should be placed as close to the TCAL6416R as possible. Figure 8-9 shows these best practices.

8.4.2 Layout Example

0.1 uF 0.1 uF Figure 8-9. TCAL6416R DTO Partial Example Layout (4-Layer) www.ti.com TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TCAL6416R

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2024) to Revision B (September 2025) Page Changes from Revision * (April 2024) to Revision A (June 2024) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TCAL6416R SCPS290B – APRIL 2024 – REVISED SEPTEMBER 2025 www.ti.com

Product Folder Links: TCAL6416R

www.ti.com 6-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCAL6416RADTOR Active Production X2QFN (DTO) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3OES TCAL6416RBDTOR Active Production X2QFN (DTO) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3ODS TCAL6416RDTOR Active Production X2QFN (DTO) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T64R TCAL6416RDTOR.A Active Production X2QFN (DTO) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T64R (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCAL6416RADTOR X2QFN DTO 24 3000 189.0 185.0 36.0 TCAL6416RBDTOR X2QFN DTO 24 3000 189.0 185.0 36.0 TCAL6416RDTOR X2QFN DTO 24 3000 189.0 185.0 36.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.4 0.3 1.6

0.4 TYP

1.6 (0.115) TYP (0.115) TYP 24X 0.22 0.12 (0.1) (0.25) 0.05 -0.01 B 2.05 1.95 A 2.05 1.95 4229652/C 10/2023 X2QFN - 0.4 mm max heightDTO0024A PLASTIC QUAD FLATPACK - NO LEAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is for Embedded Application only. PIN A1 INDEX AREA SEATING PLANE 0.05 C 0.05 C SCALE 8.000 PIN A1 SYMM SYMM 1 2 3 4 A B C D E

www.ti.com EXAMPLE BOARD LAYOUT (0.4) TYP (0.4) TYP (1.6) TYP (1.6) TYP 24X ( 0.17) (R0.05) TYP 0.0375 MAX 0.0375 MIN 4229652/C 10/2023 X2QFN - 0.4 mm max heightDTO0024A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 1 2 3 4 A B C D E NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK OPENING METAL EDGE SOLDER MASK DEFINED EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING

www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP (1.6) TYP (1.6) TYP 24X ( 0.17) (R0.05) TYP 4229652/C 10/2023 X2QFN - 0.4 mm max heightDTO0024A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.0625 mm THICK STENCIL SCALE:40X 1 2 3 4 A B C D E

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Product Information

TCAL6416RADTOR specifications and overview.

Summary

TCAL6416R 16-Bit Translating I2C-Bus, SMBus I/O Expander with Interrupt Output, Reset Input, and Sticky Registers for Agile I/O Configuration REVISED SEPTEMBER 2025

Description

TCAL6416R 16-Bit Translating I2C-Bus, SMBus I/O Expander with Interrupt Output, Reset Input, and Sticky Registers for Agile I/O Configuration REVISED SEPTEMBER 2025

Source title TCAL6416RADTOR Datasheet(PDF) - Texas Instruments

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TCAL6416R TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

Package Information

11 Mechanical, Packaging, and Orderable

2 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

4 Pin Configuration and Functions

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5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Thermal Information

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5.5 Electrical Characteristics

5.5 Electrical Characteristics (continued)

5.6 Timing Requirements

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5.7 I2C Bus Timing Requirements

5.7 I2C Bus Timing Requirements (continued)

5.8 Switching Characteristics

5.9 Typical Characteristics

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5.9 Typical Characteristics (continued)

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6 Parameter Measurement Information

1 I 2C address

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0.7 V× CCI

0.3 V× CCI

0.5 V× CCI

0.5 V× CCP

2 V× CCP

0.7 V× CCP

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0.3 V´ CCI

7 Detailed Description

7.1 Overview

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7.2 Functional Block Diagrams

16 Bits I/O

7.3 Feature Description

7.3.1 Voltage Translation

7.3.2 I/O Port

7.3.3 Adjustable Output Drive Strength

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7.3.4 Interrupt Output (INT)

7.3.5 Reset Input (RESET)

7.3.6 Software Reset Call

7.4 Device Functional Modes

7.4.1 Power-On Reset

7.5 Programming

7.5.1 I2C Interface

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7.6 Register Maps

7.6.1 Device Address

7.6.2 Multiple Power-Up Default Conditions

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7.6.3 Control Register and Command Byte

7.6.4 Register Descriptions

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7.6.5 Bus Transactions

7.6.5.1 Writes

7.6.5.2 Reads

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8 Application and Implementation

8.1 Application Information

8.2 Typical Application

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8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 Minimizing ICC When I/Os Control LEDs

8.2.3 Application Curves

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