TCA9536DGKR

TCA9536_V03 TI | Alldatasheet

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Technical content

TCA9536 Remote 4-Bit I2C and SMBus I/O Expander with Configuration Registers

1 Features

• I2C to GPIO expander
• Operating power-supply voltage range of 1.65 V to 5.5 V
• 5-V Tolerant I/O ports
• Software Reset via I2C General Call
• Software-enabled integrated pull-up resistors on P ports
• P3 can be repurposed as INT output
• 1-MHz Fast mode plus I2C bus
• Input and output configuration register
• Polarity inversion register
• Internal power-on reset
• Power-up with all channels configured as inputs
• Noise filter on SCL and SDA inputs
• Latched outputs with high-current drive maximum capability for directly driving LEDs
• ESD protection exceeds JESD 22 – 2000-V Human-body model (A114-A) – 1000-V Charged-device model (C101)

2 Applications

• Personal electronics – Wearables – Mobile phones – Gaming consoles
• Servers
• Routers

3 Description

The TCA9536 is a 4-bit I/O expander for the I 2C bus and is designed for 1.65-V to 5.5-V V CC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface. The system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. There is an additional special function register that can be used to disable the internal pull-up resistors and P3 override to an INT output. The TCA9536 open-drain interrupt output ( when P3 is configured as INT in the special function register) is activated when any input differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed. The system processor can reset the TCA9536 in the event of a timeout or other improper operation by using an I 2C soft reset command, which puts the registers in their default state. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TCA9536 X2SON (8) 1.35 mm × 0.80 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. spacer I2C or SMBus Controller (e.g. Processor) TCA9536 GND SCL SDA VCC P3 / INT RESET, ENABLE, or control inputs INT or status outputs LEDs Buttons Peripheral Devices TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..27

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision * (July 2021) to Revision A (December 2021) Page TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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5 Pin Configuration and Functions

5 SCL

6 SDA

7 VCC

Figure 5-1. DTM Package, 8-Pin X2SON, Top View 1P0 8 V CC 2P1 7 SDA 3P2 6 SCL 4GND 5 P3/INT Not to scale Figure 5-2. DGK Package, 8-Pin VSSOP, Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION DGK DTM NAME 1 1 P0 I/O P-port input-output. Push-pull design structure. Internal pull-up resistor enabled by default. 2 8 P1 I/O P-port input-output. Push-pull design structure. Internal pull-up resistor enabled by default. 3 2 P2 I/O P-port input-output. Push-pull design structure. Internal pull-up resistor enabled by default. 4 3 GND — Ground 5 4 P3/INT I/O P-port input-output. Push-pull design structure. When configured as INT, operates as open drain. Internal pull-up resistor enabled by default. 6 5 SCL I/O Serial clock bus. Connect to VCC through a pull-up resistor 7 6 SDA I/O Serial data bus. Connect to VCC through a pull-up resistor 8 7 VCC — Supply voltage www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCA9536

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply current –0.5 6 V VI Input voltage(2) –0.5 6 V VO Output voltage(2) –0.5 6 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input-output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –50 mA ICC Continuous current through GND –250 mA Continuous current through VCC 160 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ ESDA/JEDEC JS-001(1) Pins P0-P3, VCC ±4000 VPins SDA, SCL ±2000 Charged device model (CDM), per ANSI/ ESDA/JEDEC specification JS-002(2) All pins ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 1.65 5.5 V VI Input voltage SCL, SDA 0 5.5 V P0-P3(1) 0 5.5 IOH High-level output current P3-P0 –10 mA IOL Low-level output current (VCC > 1.8 V) P3-P0 25 mA Low-level output current (VCC ≤ 1.8 V) P3-P0 15 mA TA Ambient temperature –40 125 °C TJ Junction temperature 125 °C (1) When the internal pull up resistors are enabled, input voltages above VCC will result in current flowing to VCC from the port. TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) TCA9536 UNITDGK (VSSOP) DTM (X2SON) 8-PIN 8-PIN RθJA Junction-to-ambient thermal resistance 183.7 193.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 76.9 110.7 °C/W RθJB Junction-to-board thermal resistance 104.9 110.4 °C/W ΨJT Junction-to-top characterization parameter 18.7 5.9 °C/W ΨJB Junction-to-board characterization parameter 103.4 110.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIK Input diode clamp voltage II = -18 mA 1.65 V to 5.5 V –1.2 V VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.6 V VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V VIH High-level input voltage SDA,SCL 1.65 to 5.5 V 0.7 × VCC V VIH High-level input voltage P ports 1.65 to 5.5 V 0.7 × VCC V VIL Low-level input voltage SDA,SCL 1.65 to 5.5 V 0.4 × VCC V VIL Low-level input voltage P ports 1.65 to 5.5 V 0.3 × VCC V VOH P-port high-level output voltage(1) IOH = -8 mA 1.65 V 1.2 V 2.3 V 1.8 3 V 2.6 4.5 V 4.1 4.75 V 4.1 IOH = -10 mA

1.65 V 1

2.3 V 1.7 3 V 2.5

4.5 V 4

4.75 V 4

IOL Low-level output current SDA VOL = 0.4 V 1.65 V to 5.5 V mA P0-P3 VOL = 0.5 V 8 VOL = 0.7 V 10 IOL Low-level output current INT (2) VOL = 0.4 V 1.65 V to 5.5 V 4 mA II Input leakage current P ports VI = VCC 1.65 V to 5.5 V 0 ±1 µA VI = 5.5 V ( TA ≤ 105 ℃) 0 V 0 ±1 VI = 5.5 V 0 V 0 ±2 VI = GND, PU Disabled 1.65 V to 5.5 V 0 ±1 www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCA9536

6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT II Input leakage current P ports VI = GND, PU Enabled 1.65 V to 5.5 V -100 -40 µA II Input leakage current SCL, SDA input leakage VI = VCC or GND 1.65 V to 5.5 V 0 ±1 µA ICC Quiescent current Operating mode VI = VCC or GND (PU Disabled), I/O = inputs, fSCL = 400 kHz, tr = tf = 300 ns

5.5 V 22 40

µA

3.6 V 11 20

2.7 V 8 10

1.95 V 5 8

ICC Quiescent current Operating mode VI = GND, I/O = inputs, fSCL = 400 kHz, tr = tf = 300 ns, PU Enabled

5.5 V 225 390

µA

3.6 V 175 280

2.7 V 125 200

1.95 V 100 150

ICC Quiescent current Operating mode VI = VCC or GND (PU Disabled), I/O = inputs, fSCL =

1 MHz, tr = tf =

5.5 V 100

µA

3.6 V 40

2.7 V 25

1.95 V 15

ICC Quiescent current Operating mode VI = GND, I/O = inputs, fSCL = 120 ns, PU Enabled

5.5 V 225 425

µA

3.6 V 175 250

ICC Quiescent current Standby mode VI = VCC, IO = 0, I/0 = inputs, fSCL = 0 kHz 5.5 V 1.5 3.9 µA 3.6 V 0.9 2.2 2.7 V 0.6 1.8 1.95 V 0.6 1.5 ICC Quiescent current Standby mode VI = GND, I/0 = inputs, fSCL = 0 kHz, PU Enabled

5.5 V 225 350

µA CI Input pin capacitance SCL VI = VCC or GND 1.65 V to 5.5 V 4 5 pF CIO Input-output pin capacitance SDA VIO = VCC or GND 1.65 V to 5.5 V 7 10 pF P port VIO = VCC or GND 1.65 V to 5.5 V 7 10 (1) Each I/O must be externally limited to a maximum of 25 mA (2) P3 can be repurposed as INT (open-drain interrupt output) in the special function register

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Device tREADY Power on to start condition time 10 µs TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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6.7 I2C Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT I2C Bus - Standard Mode fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 ns tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capactive load 400 pF I2C Bus - Fast Mode fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns ticf I2C input fall time 20 × (VCC / 5.5 300 ns tocf I2C output fall time 10-pF to 400-pF bus 20 × (VCC / 5.5 300 ns tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 µs tvd(data) Valid data time SCL low to SDA output valid 0.9 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 µs Cb I2C bus capactive load 400 pF I2C Bus - Fast Mode Plus fscl I2C clock frequency 0 1000 kHz tsch I2C clock high time 0.26 µs tscl I2C clock low time 0.5 µs www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCA9536

6.7 I2C Bus Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT tsp I2C spike time 50 ns tsds I2C serial-data setup time 50 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 120 ns ticf I2C input fall time 20 × (VCC / 5.5 120 ns tocf I2C output fall time 10-pF to 550-pF bus 20 × (VCC / 5.5 120 ns tbuf I2C bus free time between stop and start 0.5 µs tsts I2C start or repeated start condition setup 0.26 µs tsth I2C start or repeated start condition hold 0.26 µs tsps I2C stop condition setup 0.26 µs tvd(data) Valid data time SCL low to SDA output valid 0.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.45 µs Cb I2C bus capactive load 550 pF

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX UNIT tiv Interrupt valid time P port INT 4 µs tir Interrupt reset delay time SCL INT 4 µs tpv Output data valid; For VCC ≥ 2.3 V SCL P port 200 ns Output data valid; For VCC < 2.3 V 400 ns tps Input data setup time P port SCL 100 ns tph Input data hold time P port SCL 300 ns TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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6.9 Typical Characteristics

TA = 25°C (unless otherwise noted) Figure 6-1. Supply Current (Standby) vs Supply Voltage for Different Temperature (TA) V CC - Supply Voltage (V) ICC - Supply Current (µA) 100 125 150 175 200 225 250 275 125 C 85 C 25 C -40 C Figure 6-2. Supply Current vs Supply Voltage for Different Temperature (TA) Temperature( C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 0.5 1.5 2.5 V CC = 5.5V V CC = 5V V CC = 3.3V V CC = 2.5V V CC = 2.3V V CC = 1.8V V CC = 1.65V Figure 6-3. Standby Supply Current vs Temperature for Different Supply Voltage (VCC) Temperature( C) ICC - Supply Current (µA) -40 -25 -10 5 20 35 50 65 80 95 110 125 100 150 200 250 300 350 400 450 500 550 V CC = 5.5V V CC = 5V V CC = 3.3V V CC = 2.5V V CC = 2.3V V CC = 1.8V V CC = 1.65V Figure 6-4. Supply Current vs Temperature for Different Supply Voltage (VCC) Temperature( C) VCC -VOH - I/O High Voltage (V) -40 -15 10 35 60 85 110 125 0.1 0.2 0.3 0.4 0.5 0.6 5.5V, 10 mA 5V, 10 mA 3.3V, 10 mA 2.3V, 10 mA 1.65V, 10 mA Figure 6-5. VCC – VOH Voltage vs Temperature for Different VCC Temperature( C) VOL - Output Low Voltage (mV) -40 -15 10 35 60 85 110 125 100 150 200 250 300 350 5.5V, 10 mA 5V, 10 mA 3.3V, 10 mA 2.3V, 10 mA 1.65V, 10 mA Figure 6-6. VOL vs Temperature for Different VCC www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCA9536

6.9 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) V CC - Supply Voltage (V) VCC -VOH - I/O High Voltage (mV) 120 150 180 210 240 270 300 330 360 390 IOH = -10mA IOH = -8mA Figure 6-7. VCC – VOH Voltage at 25°C for Different VCC IOL - Sink Current (mA) VOL - Output Low Voltage (V) 0 5 10 15 20 25 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 125 C 85 C 25 C -40 C Figure 6-8. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 2.3 V IOL - Sink Current (mA) VOL - Output Low Voltage (V) 0 5 10 15 20 25 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 125 C 85 C 25 C -40 C Figure 6-9. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 3.3 V IOL - Sink Current (mA) VOL - Output Low Voltage (V) 0 5 10 15 20 25 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 125 C 85 C 25 C -40 C Figure 6-10. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 5.5 V IOL - Sink Current (mA) VOL - Output Low Voltage (V) 0 2.5 5 7.5 10 12.5 15 17.5 20 22 0.3 0.6 0.9 1.2 1.5 1.8 125 C 85 C 25 C -40 C Figure 6-11. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 1.8 V IOL - Sink Current (mA) VOL - Output Low Voltage (V) 0 3 6 9 12 15 18 0.3 0.6 0.9 1.2 1.5 1.8 125 C 85 C 25 C -40 C Figure 6-12. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 1.65 V TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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7 Parameter Measurement Information

0.7 x VCC 0.3 x VCC 0.7 x VCC 0.3 x VCC DUT CL = 50 pF (see Note A) VCC RL = 1 NŸ SDA VOLTAGE WAVEFORMS Three Bytes for Complete Device Programming SDA LOAD CONFIGURATION Stop Condition (P) Start Condition (S) Address Bit 7 (MSB) Address Bit 6 Address Bit 1 R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) A. CL include probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCA9536

500 CL = 50 pF

(see Note A) 0.7 x VCC 0.3 x VCC SCL SDA P0 A Target ACK Unstable Data Last Stable Bit tpv (see Note B) P-PORT LOAD CONFIGURATION WRITE MODE (R/W = 0) P3AP0SCL Pn tps tph 0.7 x VCC 0.3 x VCC 0.7 x VCC 0.3 x VCC READ MODE (R/W = 1) A. CL include probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 7-2. P-Port Load Circuit and Voltage Waveforms TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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8 Detailed Description

8.1 Overview

The TCA9536 device is a 4-bit I/O expander for the I2C bus and is designed for 1.65-V to 5.5-V V CC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface. The TCA9536 consists of a configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) , and special function registers. At power-on, the I/Os are configured as inputs with a weak pull-up to V CC. The system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. There is an additional special function register that can be used to disable the internal pull-up resistors and P3 override to an INT output. All registers can be read by the system controller. The TCA9536 open-drain interrupt output ( when P3 is configured as INT in the special function register ) is activated when any input differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed. The system processor can reset the TCA9536 in the event of a timeout or other improper operation by using an I2C soft reset command, which puts the registers in their default state. The device outputs (latched) have high-current drive capability for directly driving LEDs.

8.2 Functional Block Diagram

4 Bits I/O

Figure 8-1. Logic Diagram www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCA9536

P0 – P2 GND Input Port Register Data Polarity Register Data ESD Protection Diode 100 k FF D Q CK Q Pull-up Disable Bit (Special Function Register) Data From Shift Register Write Configuration Pulse Figure 8-2. Simplified Schematic Of P0 To P2 FF D Q CK Q FF D Q CK Q FF D Q CK Q FF D Q CK Q Data From Shift Register Data From Shift Register Write Configuration Pulse Write Pulse Read Pulse Data From Shift Register Write Polarity Pulse Configuration Register Output Port Register Input Port Register Polarity Inversion Register Output Port Register Data VCC P3 / INT GND Input Port Register Data Polarity Register Data ESD Protection Diode 100 k FF D Q CK Q Pull-up Disable Bit (Special Function Register) Data From Shift Register Write Configuration Pulse FF D Q CK Q Data From Shift Register Write Pulse INT Output Mode Enable (Special Function Register) INT Asserted Figure 8-3. Simplified Schematic Of P3 / INT TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off , creating a high-impedance input with a weak pull-up (100 k Ω typical with roughly 20% tolerance) to V CC. This internal weak pull-up can be disabled via the special function register if desired. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either V CC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.

8.3.2 P3 or Interrupt (INT) Output

The TCA9536 has a combination P3 and INT output pin. The function of the pin is selected by the special function register. When the pin is configured as an INT output, the internal-pull up resistor is enabled by default, but will depend on the state of the PU Disable bit in the special function register. See Table 8-7 for more information. The below text describes the functionality of the pin when configured as an INT output. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. INT has an open-drain structure and requires a pull-up resistor to VCC of moderate value (typically about 10 kΩ).

8.3.3 Pull-up Disable Functionality

The TCA9536 has internal 100 k Ω resistors pulled up to V CC by default. The special function register contains a bit which will disable the pull-up resistors on all P-ports. See Table 8-7 for more information. If the P3 port has been configured as an interrut output, the pull-up resistor will depend on the disable bit, the same as any other P-port.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to V CC, an internal power-on reset holds the device in a reset condition until VCC has reached V POR. At that time, the reset condition is released and the TCA9536 registers and I 2C/SMBus state machine initialize to their default states. See Section 10.1 for more details.

8.4.2 Powered-Up

When power has been applied to VCC above VPORR, and the POR has taken place, the device is in a functioning mode. In this state, the device is ready to accept any incoming I2C requests and is monitoring for changes on the input ports.

8.5 Programming

8.5.1 I2C Interface

The TCA9536 has a standard bidirectional I 2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I 2C bus has a specific device address to differentiate between other target devices that are on the same I 2C bus. Many target devices require configuration upon startup to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCA9536

registers where data is stored, written, or read. For more information see Understanding the I2C Bus application report, SLVA704. The physical I 2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to V CC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I 2C lines. For further details, see I2C Pull-up Resistor Calculation application report, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Interface Definition. Figure 8-4 and Figure 8-5 show the general procedure for a controller to access a target device: 1. If a controller wants to send data to a target:

• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition. 2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter.
• Controller-receiver terminates the transfer with a STOP condition. SCL SDA START Condition STOP Condition Data Transfer Figure 8-4. Definition of Start and Stop Conditions SCL SDA MSB Bit Bit Bit Bit Bit Bit LSB Byte: 1010 1010 ( 0xAAh ) 1 0 1 0 1 0 1 0 SDA line stable while SCL line is high ACK ACK Figure 8-5. Bit Transfer TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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8.5.1.1 Writes

To write on the I 2C bus, the controller sends a START condition on the bus with the address of the target, as well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the controller then sends the register address of the register to which it wishes to write. The target acknowledges again, letting the controller know it is ready. After this, the controller starts sending the register data to the target until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller terminates the transmission with a STOP condition. See the Control Register and Command Byte section to see list of the TCA9536 internal registers and a description of each one. Figure 8-6 shows an example of writing a single byte to a target register. S A6 A5 A4 A3 A2 A1 A0 0 Device (Target) Address (7 bits) B7 B6 B5 B4 B3 B2 B1 B0 A Register Address N (8 bits) D7 D6 D5 D4 D3 D2 D1 D0 A Data Byte to Register N (8 bits) A P START R/W=0 ACK ACK ACK STOP Write to one register in a device Controller controls SDA line Target controls SDA line Figure 8-6. Write to Register Figure 8-7 shows the Write to Output Port Registers. Data 1x x x x x x x 0 A A AS 0 0 0 0 0 1 1 P0 1 2 3 4 6 7 8 9 Start Condition ACK From Target ACK From Target ACK From TargetR/W Target Address Command Byte Data to Register SCL SDA Write to Port tpv Data Out From Port Data 1 Valid Figure 8-7. Write to Output Port Register

8.5.1.2 Reads

The bus controller first must send the TCA9536 address with the LSB set to a logic 0 (see Table 8-1 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA9536 (see Figure 8-9 ). The command byte does not increment automatically. If multiple bytes are read, data from the specified command byte/register is going to be continuously read. Figure 8-8 shows an example of reading a single byte from a target register. www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCA9536

Read from one register in a device S A6 A5 A4 A3 A2 A1 A0 0 Device (Target) Address (7 bits) B7 B6 B5 B4 B3 B2 B1 B0 A Register Address N (8 bits) A START ACK ACK Sr A6 A5 A4 A3 A2 A1 A0 Device (Target) Address (7 bits) Repeated START

1 A D7 D6 D5 D4 D3 D2 D1 D0 NA

Data Byte from Register N (8 bits) P NACK STOPACK Controller controls SDA line Target controls SDA line R/W=0 R/W=1 Figure 8-8. Read from Register After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte, additional bytes may be read, but the same register specified by the command byte is read. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus controller must not acknowledge the data. Data 4A6 A5 A4 A3 A2 A1 A0 1 A A NAS P 1 2 3 4 6 7 8 9 Start Condition ACK From Controller ACK From Controller NACK from ControllerR/W Target Address Data From Port Data From Port SCL SDA Read From Port tps Data Into From Port Data 1 Valid INT Data 1 Data 2 Data 3 Data 4 Data 5 tph tirtiv Data 1 A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register). B. This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from the P port (see Figure 8-8 for these details). Figure 8-9. Read Input Port Register

8.5.2 Software Reset Call

The Software Reset call is a command send from the controller on the I 2C bus that instructs all devices that support the command to be reset to power-up values. In order for it to function as expected, the I 2C bus must be functional and no devices can be hanging the bus. The Software Reset Call is defined as the following steps: 1. A START condition is sent by the I2C bus controller. 2. The address used is the reserved General Call I2C bus address '0000 000' with the R/W bit set to 0. The byte sent is 0x00. 3. Any devices supporting the General Call functionality will ACK. If the R/W bit is set to 1 (read), the device will NACK. 4. Once the General Call address is acknowledged, the controller sends only 1 byte of data equal to 0x06. If the data byte is any other value, the device will NOT acknowledge or reset. If more than 1 byte is sent, no more bytes will be acknlowedged, and the device will ignore this I2C message, considering it invalid. TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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1. After the 1 byte of data (0x06) is sent, the controller sends a STOP condition to end the Software Reset sequence. A repeated START condition will be ignored by the device, and no reset is performed. Once the above steps are completed successfully, the device will perform a reset. This will clear all register values back to power-on defaults. All P-ports will be configured as inputs , regardless of the port mode configuration of the P3 port.

8.6 Register Maps

8.6.1 Device Address

Table 8-1 shows the fixed 7-bit address of the device. Note that I 2C uses a 7-bit address with a 1-bit READ/ WRITE bit for the LSB. Table 8-1. Device Address Device A6 A5 A4 A3 A2 A1 A0 Hex Decimal TCA9536 1 0 0 0 0 0 1 0x41 65 TCA9536A 1 0 0 0 0 0 0 0x40 64 TCA9536B 1 0 0 0 0 1 1 0x43 67 TCA9536C 1 0 0 0 0 1 0 0x42 66 The last bit of the 8-bit address byte defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte that is stored in the control register in the TCA9536. This data byte state the operation (read or write) and the internal register (Input, Output, Polarity Inversion, Configuration , or Special Function ) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Table 8-2. Command Byte COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT 0x00 Input Port Read byte 1111 XXXX 0x01 Output Port Read/write byte 1111 1111 0x02 Polarity Inversion Read/write byte 0000 0000 0x03 Configuration Read/write byte 1111 1111 0x50 Special Function Read/write byte 0000 0000

8.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 8-3. Before a read operation, a write transmission is sent with the command byte to instruct the I 2C device that the Input Port register will be accessed next. Table 8-3. Register 0 (Input Port Register) BIT I7 I6 I5 I4 I3 I2 I1 I0 Not Used DEFAULT 1 1 1 1 X X X X www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCA9536

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table 8-4. Table 8-4. Register 0x01 (Output Port Register) BIT O7 O6 O5 O4 O3 O2 O1 O0 Not Used DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained. See Table 8-5. Table 8-5. Register 0x02 (Polarity Inversion Register) BIT N7 N6 N5 N4 N3 N2 N1 N0 Not Used DEFAULT 0 0 0 0 0 0 0 0 The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. See Table 8-6. Table 8-6. Register 0x03 (Configuration Register) BIT C7 C6 C5 C4 C3 C2 C1 C0 Not Used DEFAULT 1 1 1 1 1 1 1 1 The Special Function register (register 0x50) configures the directions of the I/O pins. If P3 as INT is set to 1, the function of P3 will change to an INT output. If PU Disabled is set to 1, all the internal pull-up resistors on the P ports are disabled, this includes the P3 port if it's configured as an INT output. See Table 8-6. Table 8-7. Register 0x50 (Special Function Register) BIT S7 S6 S5 S4 S3 S2 S1 S0 P3 as INT PU Disabled Not Used DEFAULT 0 0 0 0 0 0 0 0 TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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9 Application Information Disclaimer

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

This section discusses a typical application in which the device is used to both handle an interrupt input, and output several control signals. I2C Controller Subsystem 1 (e.g., temperature sensor) Subsystem 2 (e.g., counter) ENABLE A B SCL SDA GND SCL SDA GND VCC VCC VCC INT RESET 10 kΩ 10 k Ω 2 kΩ A. P0, P2, and P3 are configured as outputs. B. P1 is configured as an input. Note P3 is configured as GPIO, not an interrupt output. Figure 9-1. Typical Application

9.2.1 Design Requirements

9.2.1.1 Minimizing ICC When I/Os Control LEDs

When the I/Os are used to control LEDs, they are normally connected to V CC through a resistor as shown in Section 9.2. The LED acts as a diode so, when the LED is off, the I/O V IN is about 1.2 V less than V CC. The supply current, ICC, increases as VIN becomes lower than VCC. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V CC when the LED is off. Figure 9-2 shows a high-value resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V IN at or above VCC and prevent additional supply-current consumption when the LED is off. www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCA9536

100 NŸ Figure 9-2. High-Value Resistor in Parallel with the LED VCC Pn LED

3.3 V 5 V

Figure 9-3. Device Supplied by a Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, R P, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all slaves on the I 2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL as shown in Equation 1: CC OL(max) p(min) OL V V R I /c45 /c61 (1) The maximum pull-up resistance is a function of the maximum rise time, t r (300 ns for fast-mode operation, f SCL = 400 kHz) and bus capacitance, Cb as shown in Equation 2: r p(max) b tR 0.8473 C/c61 /c180 (2) The maximum bus capacitance for an I 2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9536, Ci for SCL or Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus. TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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9.2.3 Application Curves

Standard mode (fSCL = 100 kHz, tr = 1 μs) Fast mode (fSCL = 400 kHz, tr = 300 ns) Fast mode plus (fSCL = 1000 kHz, tr = 120 ns) Figure 9-4. Maximum Pullup Resistance (Rp(max)) vs Bus Capacitance (Cb) VDPUX < 2 V VDPUX > 2 V VOL = 0.2 x VDPUX , IOL = 2 mA when VDPUX ≤ 2 V VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V Figure 9-5. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VDPUX) www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCA9536

10 Power Supply Recommendations

10.1 Power-On Reset

In the event of a glitch or data corruption, the TCA9536 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in and Figure 10-1. VCC Ramp-Up Time to Re-Ramp Time Ramp-Down VCC drops below V 50 mVPORF – VCC_RTVCC_FT VCC_TRR Figure 10-1. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 10-1 specifies the performance of the power-on reset feature for the device for both types of power-on reset. Table 10-1. Recommended Supply Sequencing And Ramp Rates PARAMETER(1) MIN MAX UNIT VCC_FT Fall rate See Figure 10-1 1 ms VCC_RT Rise rate See Figure 10-1 0.1 ms VCC_TRR Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) See Figure 10-1 2 μs VCC_GH Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 µs See Figure 10-2 1.2 V VCC_GW Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC (For VCC > 3 V) See Figure 10-2 10 μs (1) All supply sequencing and ramp rate values are measured at TA = 25°C Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (V CC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 10-2 and Table 10-1 provide more information on how to measure these specifications. VCC Time VCC_GH VCC_GW Figure 10-2. Glitch Width and Glitch Height VPOR is critical to the power-on reset. V POR is the voltage level at which the reset condition is released and all the registers and the I 2C/SMBus state machine are initialized to their default states. The value of V POR differs based on the V CC being lowered to or from 0. Figure 10-3 and Table 10-1 provide more details on this specification. TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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Figure 10-3. VPOR www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCA9536

11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9536, common PCB layout practices must be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These capacitors must be placed as close to the TCA9536 as possible. For the layout example provided, it would be possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated.

11.2 Layout Example

Figure 11-1. Layout Example (DGK) TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 www.ti.com

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• I2C Bus Pull-Up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• Choosing the Correct I2C Device for New Designs

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TCA9536 SCPS275A – JULY 2021 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCA9536

www.ti.com 14-Jul-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TCA9536ADTMR ACTIVE X2SON DTM 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 1IR Samples TCA9536BDTMR ACTIVE X2SON DTM 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 1IS Samples TCA9536CDTMR ACTIVE X2SON DTM 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 1IT Samples TCA9536DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2I1T Samples TCA9536DTMR ACTIVE X2SON DTM 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 1IQ Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 14-Jul-2023 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9536ADTMR X2SON DTM 8 5000 205.0 200.0 33.0 TCA9536BDTMR X2SON DTM 8 5000 205.0 200.0 33.0 TCA9536CDTMR X2SON DTM 8 5000 205.0 200.0 33.0 TCA9536DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 TCA9536DTMR X2SON DTM 8 5000 205.0 200.0 33.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 6X 0.25 0.15 0.5

0.4 MAX

0.04 0.00 6X 0.27 0.17 0.54 2X 0.27 0.17 B 0.85 0.75 A 1.4 1.3 (0.102) TYP 4224755/B 10/2022 X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.05 C

0.1 C B A

0.05 C SYMM SYMM PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT ( 0.22) 4X (0.079)

0.0325 MIN

ALL AROUND0.0325 MAX ALL AROUND 6X (0.2) (0.5) (0.78) (R0.05) TYP 6X (0.42) (0.27) (45 ) TYP 4X (0.1) X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD 4224755/B 10/2022 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). NON SOLDER MASK DEFINED LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X SYMM SYMM SEE SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS SOLDER MASK OPENING METAL EDGE EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.411) 4X (0.42) 6X (0.2) (0.5) (0.78) PINS: 1,3,5,7 (0.27) (R0.05) TYP ( 0.22) (0.2) TYP 4X (0.079) (45 ) TYP 4X (0.128) X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD 4224755/B 10/2022 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 40X EXPOSED METAL

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