TCA9535PWR

TCA9535_17 TI1 | Alldatasheet

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Technical content

(e.g. Processor) SCL INT VCC GND P00 P01 P02 P03 P04 P05 P06 P07 Peripheral Devices x RESET, EN or Control Inputs x INT or status outputs x LEDs x Keypad P10 P11 P12 P13 P14 P15 P16 P17 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TCA9535 SCPS201D –AUGUST 2009–REVISED JULY 2016 TCA9535Low-Voltage16-BitI2CandSMBusLow-PowerI/OExpander withInterruptOutputandConfigurationRegisters

1 Features

1• I2C to Parallel Port Expander

• Wide Power Supply Voltage Range of 1.65 V to 5 V
• Low Standby-Current Consumption
• Open-Drain Active-Low Interrupt Output
• 5-V Tolerant I/O Ports
• 400-kHz Fast I2C Bus
• Polarity Inversion Register
• Address by Three Hardware Address Pins for Use of up to Eight Devices
• Latched Outputs With High-Current Drive Capability for Directly Driving LEDs
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101)

2 Applications

• Servers
• Routers (Telecom Switching Equipment)
• Personal Computers
• Personal Electronics (For Example, Gaming Consoles)
• Industrial Automation
• Products With GPIO-Limited Processors

3 Description

The TCA9535 is a 24-pin device that provides 16 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus or (SMBus) protocol. The device can operate with a power supply voltage ranging from 1.65 V to 5.5 V. The TCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The TCA9535 is identical to the TCA9555, except that the TCA9535 does not include the internal I/O pull-up resistor, which requires pull-ups and pull- downs on unused I/O pins when configured as an input and undriven. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TCA9535 TSSOP (24) 7.80 mm x 4.40 mm SSOP (24) 6.20 mm x 5.30 mm WQFN (24) 4.00 mm x 4.00 mm VQFN (24) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram

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12.2 Receiving Notification of Documentation Updates 32

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2016) to Revision D Page Changes from Revision B (August 2015) to Revision C Page Changes from Revision A (September 2009) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

V CC INT Exposed Center Pad TCA9535 www.ti.com SCPS201D –AUGUST 2009–REVISED JULY 2016 Product Folder Links: TCA9535 Submit Documentation FeedbackCopyright © 2009–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

24-Pin WQFN, VQFN Top View The exposed center pad, if used, must be connected as a secondary ground or left electrically open. (1) If port is unused, it must be tied to either VCC or GND through a resistor of moderate value (about 10 kΩ) Pin Functions PIN TYPE DESCRIPTION NAME NO. DB, PW RTW, RGE A0 21 18 Input Address input 0. Connect directly to VCC or ground A1 2 23 Input Address input 1. Connect directly to VCC or ground A2 3 24 Input Address input 2. Connect directly to VCC or ground GND 12 9 — Ground INT 1 22 Output Interrupt output. Connect to VCC through an external pull-up resistor P00(1) 4 1 I/O P-port I/O. Push-pull design structure. At power on, P00 is configured as an input P01(1) 5 2 I/O P-port I/O. Push-pull design structure. At power on, P01 is configured as an input P02(1) 6 3 I/O P-port I/O. Push-pull design structure. At power on, P02 is configured as an input P03(1) 7 4 I/O P-port I/O. Push-pull design structure. At power on, P03 is configured as an input P04(1) 8 5 I/O P-port I/O. Push-pull design structure. At power on, P04 is configured as an input P05(1) 9 6 I/O P-port I/O. Push-pull design structure. At power on, P05 is configured as an input P06(1) 10 7 I/O P-port I/O. Push-pull design structure. At power on, P06 is configured as an input P07(1) 11 8 I/O P-port I/O. Push-pull design structure. At power on, P07 is configured as an input P10(1) 13 10 I/O P-port I/O. Push-pull design structure. At power on, P10 is configured as an input P11(1) 14 11 I/O P-port I/O. Push-pull design structure. At power on, P11 is configured as an input P12(1) 15 12 I/O P-port I/O. Push-pull design structure. At power on, P12 is configured as an input P13(1) 16 13 I/O P-port I/O. Push-pull design structure. At power on, P13 is configured as an input P14(1) 17 14 I/O P-port I/O. Push-pull design structure. At power on, P14 is configured as an input P15(1) 18 15 I/O P-port I/O. Push-pull design structure. At power on, P15 is configured as an input P16(1) 19 16 I/O P-port I/O. Push-pull design structure. At power on, P16 is configured as an input P17(1) 20 17 I/O P-port I/O. Push-pull design structure. At power on, P17 is configured as an input SCL 22 19 Input Serial clock bus. Connect to VCC through a pull-up resistor SDA 23 20 Input Serial data bus. Connect to VCC through a pull-up resistor VCC 24 21 — Supply voltage

SCPS201D –AUGUST 2009–REVISED JULY 2016 www.ti.com Product Folder Links: TCA9535 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 6 V VI Input voltage(2) –0.5 6 V VO Output voltage(2) –0.5 6 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input-output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –50 mA ICC Continuous current through GND –250 mA Continuous current through VCC 160 mA Tj(MAX) Maximum junction temperature 100 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) For voltages applied above VCC, an increase in ICC results. (2) The values shown apply to specific junction temperatures, which depend on the RθJA of the package used. See the Calculating Junction Temperature and Power Dissipation section on how to calculate the junction temperature.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 1.65 5.5 V VIH High-level input voltage SCL, SDA 0.7 × VCC VCC (1) V A2–A0, P07–P00, P17–P10 0.7 × VCC 5.5 V VIL Low-level input voltage SCL, SDA, A2–A0, P07–P00, P17–P10 –0.5 0.3 × VCC V IOH High-level output current P07–P00, P17–P10 –10 mA IOL Low-level output current(2) P07–P00, P17–P10 Tj ≤ 65°C 25 mATj ≤ 85°C 18 Tj ≤ 100°C 11 IOL Low-level output current(2) INT, SDA Tj ≤ 85°C 6 mA Tj ≤ 100°C 3.5 TA Operating free-air temperature –40 85 °C

www.ti.com SCPS201D –AUGUST 2009–REVISED JULY 2016 Product Folder Links: TCA9535 Submit Documentation FeedbackCopyright © 2009–2016, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TCA9535 UNITPW (TSSOP) DB (SSOP) RTW (WQFN) RGE (VQFN)

24 PINS 24 PINS 24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 108.8 92.9 43.6 48.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 54 53.5 46.2 58.1 °C/W RθJB Junction-to-board thermal resistance 62.8 50.4 22.1 27.1 °C/W ψJT Junction-to-top characterization parameter 11.1 21.9 1.5 3.3 °C/W ψJB Junction-to-board characterization parameter 62.3 50.1 22.2 27.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 10.7 15.3 °C/W (1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C. (2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA. (3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V –1.2 V VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.5 V VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V VOH P-port high-level output voltage(2) IOH = –8 mA 1.65 V 1.2 V 2.3 V 1.8 3 V 2.6 4.75 V 4.1 IOH = –10 mA

1.65 V 1

2.3 V 1.7 3 V 2.5

4.75 V 4

SDA VOL = 0.4 V 1.65 V to 5.5 V 3 mAP port(3) VOL = 0.5 V 1.65 V to 5.5 V 8 VOL = 0.7 V 1.65 V to 5.5 V 10 INT VOL = 0.4 V 1.65 V to 5.5 V 3 II Input leakage current SCL, SDA Input leakage VI = VCC or GND 1.65 V to 5.5 V ±1 μA A2–A0 Input leakage VI = VCC or GND 1.65 V to 5.5 V ±1 IIH Input high leakage current P port VI = VCC 1.65 V to 5.5 V 1 μA IIL Input low leakage current P port VI = GND 1.65 V to 5.5 V –1 μA

SCPS201D –AUGUST 2009–REVISED JULY 2016 www.ti.com Product Folder Links: TCA9535 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT ICC Quiescent current Operating mode VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz, No load

5.5 V 22 40

μA

3.6 V 11 30

2.7 V 8 19

1.95 V 5 11

VI = VCC, IO = 0, I/O = inputs, fSCL = 0 kHz, No load 5.5 V 1.5 3.9 3.6 V 0.9 2.2 2.7 V 0.6 1.8 1.95 V 0.6 1.5 VI = GND, IO = 0, I/O = inputs, fSCL = 0 kHz, No load 5.5 V 1.5 8.7 3.6 V 0.9 4 2.7 V 0.6 3 1.95 V 0.4 2.2 CI Input capacitance SCL VI = VCC or GND 1.65 V to 5.5 V 3 8 pF Cio Input-output pin capacitance SDA VIO = VCC or GND 1.65 V to 5.5 V 3 9.5 pF P port VIO = VCC or GND 1.65 V to 5.5 V 3.7 9.5

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 20) MIN MAX UNIT I2C BUS— STANDARD MODE fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 ns tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capacitive load 400 pF I2C BUS— FAST MODE fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns

www.ti.com SCPS201D –AUGUST 2009–REVISED JULY 2016 Product Folder Links: TCA9535 Submit Documentation FeedbackCopyright © 2009–2016, Texas Instruments Incorporated I2C Interface Timing Requirements (continued) over recommended operating free-air temperature range (unless otherwise noted) (see Figure 20) MIN MAX UNIT ticf I2C input fall time 20 × (VCC /

5.5 V) 300 ns

tocf I2C output fall time 10-pF to 400-pF bus 20 × (VCC / tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 µs tvd(data) Valid data time SCL low to SDA output valid 0.9 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 µs Cb I2C bus capacitive load 400 pF

6.7 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 20 and Figure 21) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tiv Interrupt valid time P port INT 4 μs tir Interrupt reset delay time SCL INT 4 μs tpv Output data valid; For VCC = 2.3 V–5.5 V SCL P port 200 ns Output data valid; For VCC = 1.65 V–2.3 V 300 ns tps Input data setup time P port SCL 150 ns tph Input data hold time P port SCL 1 μs

6.8 Typical Characteristics

Figure 1. Supply Current vs Temperature for Different Figure 2. Standby Supply Current vs Temperature for Figure 3. Supply Current vs Supply Voltage for Different Figure 4. I/O Sink Current vs Output Low Voltage for Figure 5. I/O Sink Current vs Output Low Voltage for Figure 6. I/O Sink Current vs Output Low Voltage for

1.8 V, 1 mA

1.8 V, 10 mA

3.3 V, 1mA

3.3 V, 10 mA

5 V, 1 mA

5 V, 10 mA

Figure 7. I/O Sink Current vs Output Low Voltage for Figure 8. I/O Sink Current vs Output Low Voltage for Figure 9. I/O Sink Current vs Output Low Voltage for Figure 10. I/O Low Voltage vs Temperature for Different VCC Figure 11. I/O Source Current vs Output High Voltage for Figure 12. I/O Source Current vs Output High Voltage for

1.65 V, 10 mA

2.5 V, 10 mA

3.6 V, 10 mA

5.5 V, 10 mA

Figure 13. I/O Source Current vs Output High Voltage for Figure 14. I/O Source Current vs Output High Voltage for Figure 15. I/O Source Current vs Output High Voltage for Figure 16. I/O Source Current vs Output High Voltage for Figure 17. VCC – VOH Voltage vs Temperature for Different Figure 18. Δ ICC vs Temperature for Different VCC (VI = VCC –

7 Parameter Measurement Information

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 19. I2C Interface Load Circuit and Voltage Waveforms

1 A Data 1 Data 4A NA P

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 20. Interrupt Load Circuit and Voltage Waveforms

A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 21. P-Port Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The TCA9535 device is a 16-bit I/O expander for the I2C bus and is designed for 1.65-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface. The TCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The TCA9535 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9535 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption. The TCA9535 device is similar to the PCA9555, except for the removal of the internal I/O pull-up resistor, which greatly reduces power consumption when the I/Os are held low. The TCA9535 is equivalent to the PCA9535 with lower voltage support (down to VCC = 1.65 V), and also improved power-on-reset circuitry for different application scenarios. Three hardware pins (A0, A1 and A2) are used to program and vary the fixed I2C address and allow up to 8 devices to share the same I2C bus or SMBus.

8.2 Functional Block Diagram

Pin numbers shown are for the PW package. All I/Os are set to inputs at reset. Figure 22. Logic Diagram (Positive Logic)

At power-on reset, all registers return to default values. Figure 23. Simplified Schematic of P-Port I/Os

8.3 Feature Description

voltage stays within VIH and VIL of the device as described in the Electrical Characteristics section.

8.3.2 Hardware Address Pins

tied either to VCC or GND and cannot be left floating.

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8.3.3 Interrupt (INT) Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa. INT has an open-drain structure and requires a pull-up resistor to VCC of moderate value (typically about 10 kΩ).

8.4 Device Functional Modes

8.4.1 Power-On Reset (POR)

When power (from 0 V) is applied to VCC, an internal power-on reset circuit holds the TCA9535 in a reset condition until VCC has reached VPORR. At that time, the reset condition is released, and the TCA9535 registers and I2C-SMBus state machine initialize to their default states. After that, VCC must be lowered to below VPORF and back up to the operating voltage for a power-reset cycle.

8.4.2 Powered-Up

When power has been applied to VCC above VPORR, and the POR has taken place, the device is in a functioning mode. In this state, the device is ready to accept any incoming I2C requests and is monitoring for changes on the input ports.

8.5 Programming

8.5.1 I2C Interface

The TCA9535 has a standard bidirectional I2C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I2C bus has a specific device address to differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see Understanding the I2C Bus application report, SLVA704. The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I2C lines. For further details, see I2C Pull-up Resistor Calculation application report, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Table 1. Figure 24 and Figure 25 show the general procedure for a master to access a slave device: 1. If a master wants to send data to a slave: – Master-transmitter sends a START condition and addresses the slave-receiver. – Master-transmitter sends data to slave-receiver. – Master-transmitter terminates the transfer with a STOP condition. 2. If a master wants to receive or read data from a slave: – Master-receiver sends a START condition and addresses the slave-transmitter. – Master-receiver sends the requested register to read to slave-transmitter. – Master-receiver receives data from the slave-transmitter.

– Master-receiver terminates the transfer with a STOP condition. Figure 24. Definition of Start and Stop Conditions Figure 25. Bit Transfer Table 1 shows the interface definition. Table 1. Interface Definition

8.5.1.1 Bus Transactions

accomplished by reading from or writing to registers in the slave device.

registers in order to instruct the slave device to perform a task.

8.5.1.1.1 Writes

transmission with a STOP condition. Figure 26 shows an example of writing a single byte to a slave register. Figure 26. Write to Register Figure 27 shows the Write to the Polarity Inversion Register. Figure 27. Write to the Polarity Inversion Register Figure 28 shows the Write to Output Port Registers.

1 A D7 D6 D5 D4 D3 D2 D1 D0 NA

Figure 28. Write to Output Port Registers

8.5.1.1.2 Reads

master-receiver, and the slave becomes the slave-transmitter. The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data. slave to halt communications and release the bus. The master follows this up with a STOP condition. Figure 29 shows an example of reading a single byte from a slave register. Figure 29. Read from Register

acknowledge the data. Figure 30 and Figure 31 show two different scenarios of Read Input Port Register. call and actual data transfer from the P port. Figure 30. Read Input Port Register, Scenario 1

call and actual data transfer from the P port. Figure 31. Read Input Port Register, Scenario 2

8.5.2 Device Address

Figure 32 shows the address byte of the TCA9535. Figure 32. TCA9535 Address Table 2 shows the address reference of the TCA9535. Table 2. Address Reference

operation, while a low (0) selects a write operation.

8.5.3 Control Register and Command Byte

can be written or read through the I2C bus. The command byte is sent only during a write transmission. new command byte has been sent. Figure 33 shows the control register bits. Figure 33. Control Register Bits Table 3. Command Byte

8.6 Register Maps

8.6.1 Register Descriptions

Input Port registers are accessed next. Table 4. Registers 0 and 1 (Input Port Registers) Table 5. Registers 2 and 3 (Output Port Registers)

Table 5. Registers 2 and 3 (Output Port Registers) (continued) is inverted. If a bit in this register is cleared (written with a 0), the corresponding pin's original polarity is retained. Table 6. Registers 4 and 5 (Polarity Inversion Registers) a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 7. Registers 6 and 7 (Configuration Registers)

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

placed close to the GPIOs to which the master needs to monitor or control. controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.

9.2 Typical Application

Figure 34 shows an application in which the TCA9535 can be used. Device address is configured as 0100100 for this example. P00, P02, and P03 are configured as outputs. P01, P04–P07, and P10–P17 are configured as inputs. Pin numbers shown are for the PW package. Figure 34. Application Schematic

9.2.1 Design Requirements

shows some key parameters which must not be violated. Table 8. Design Parameters

9.2.1.1 Calculating Junction Temperature and Power Dissipation

When designing with this device, it is important that the Recommended Operating Conditions not be violated. Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2. port is the VOL of the port multiplied by the current it is sinking.

9.2.1.2 Minimizing ICC When I/O is Used to Control LED

When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 34. LED is off to minimize current consumption. supply current consumption when the LED is off.

3.3 V 5 V

Figure 35. High-Value Resistor in Parallel With LED Figure 36. Device Supplied by Lower Voltage

9.2.2 Detailed Design Procedure

VCC, VOL,(max), and IOL as shown in Equation 5. 400 kHz) and bus capacitance, Cb as shown in Equation 6. Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus. For further details, refer to I2C Pull-up Resistor Calculation application report, SLVA689.

9.2.3 Application Curves

Figure 37. Maximum Pull-Up Resistance (Rp(max)) vs Bus Figure 38. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up

10 Power Supply Recommendations

reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 39 and Figure 40. Figure 39. VCC is Lowered Below 0.2 V or 0 V and then Ramped Up to VCC Figure 40. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC Table 9 specifies the performance of the power-on reset feature for TCA9535 for both types of power-on reset. Table 9. Recommended Supply Sequencing and Ramp Rates(1)

0603 Cap

11 Layout

11.1 Layout Guidelines

not a concern for I2C signal speeds. by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND).

11.2 Layout Example

Figure 43. TCA9535 Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• I2C Bus Pull-Up Resistor Calculation, SLVA689
• Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695
• Introduction to Logic, SLVA700
• Understanding the I2C Bus, SLVA704
• IO Expander EVM User's Guide, SLVUA59A

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 14-Jun-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TCA9535DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535DBT ACTIVE SSOP DB 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535MRGER PREVIEW VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TD9535 TCA9535PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TD9535 TCA9535RTWR ACTIVE WQFN RTW 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 14-Jun-2017 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9535DBR SSOP DB 24 2000 367.0 367.0 38.0 TCA9535DBT SSOP DB 24 250 367.0 367.0 38.0 TCA9535PWR TSSOP PW 24 2000 367.0 367.0 38.0 TCA9535RGER VQFN RGE 24 3000 367.0 367.0 35.0 TCA9535RTWR WQFN RTW 24 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2016 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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