TCA9535

TCA9535 Low-Voltage 16-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output and Configuration Registers datasheet (Rev. E)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCPS201,E]
• PDF pages: 47

Technical content

TCA9535 Low-Voltage 16-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output and Configuration Registers

1 Features

• I2C to Parallel port expander
• Wide power supply voltage range of 1.65 V to 5 V
• Low standby-current consumption
• Open-drain active-low interrupt output
• 5-V tolerant I/O ports
• 400-kHz Fast I2C bus
• Polarity inversion register
• Address by three hardware address pins for use of up to eight devices
• Latched outputs with high-current drive capability for directly driving LEDs
• Latch-up performance exceeds 100 mA per JESD 78, class II
• ESD protection exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101)

2 Applications

• Servers
• Routers (telecom switching equipment)
• Personal computers
• Personal electronics (for example, gaming consoles)
• Industrial automation
• Products with GPIO-limited processors

3 Description

The TCA9535 is a 24-pin device that provides 16 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I 2C bus or (SMBus) protocol. The device can operate with a power supply voltage ranging from 1.65 V to 5.5 V. The TCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power on, the I/Os are configured as inputs. The system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The TCA9535 is identical to the TCA9555, except that the TCA9535 does not include the internal I/O pull-up resistor, which requires pull-ups and pull-downs on unused I/O pins when configured as an input and undriven. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TCA9535 TSSOP (24) 7.80 mm x 4.40 mm SSOP (24) 6.20 mm x 5.30 mm WQFN (24) 4.00 mm x 4.00 mm VQFN (24) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TCA9535 SDA I2C or SMBus Controller (e.g. Processor) SCL INT VCC GND P00 P01 P02 P03 P04 P05 P06 P07 Peripheral Devices x RESET, EN or Control Inputs x INT or status outputs x LEDs x Keypad P10 P11 P12 P13 P14 P15 P16 P17 Block Diagram TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.2 Receiving Notification of Documentation Updates.. 30

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (June 2016) to Revision E (May 2022) Page Changes from Revision C (May 2016) to Revision D (June 2016) Page Changes from Revision B (August 2015) to Revision C (May 2016) Page Changes from Revision A (September 2009) to Revision B (August 2015) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. DB, PW (TSSOP) Package 24-Pin (Top View) P17 P16 P15 P14 P13 24 22 21 20 19 SDAA2 A1 SCL 7 9 10 11 128 P00 P01 P02 P03 P04 P05 P10P1 1P06 P07 P12GND V CC INT Exposed Center Pad The exposed center pad, if used, must be connected as a secondary ground or left electrically open. Figure 5-2. RTW (WQFN), RGE (VQFN) Package 24-Pin (Top View) Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. DB, PW RTW, RGE A0 21 18 Input Address input 0. Connect directly to VCC or ground A1 2 23 Input Address input 1. Connect directly to VCC or ground A2 3 24 Input Address input 2. Connect directly to VCC or ground GND 12 9 — Ground INT 1 22 Output Interrupt output. Connect to VCC through an external pull-up resistor P00(1) 4 1 I/O P-port I/O. Push-pull design structure. At power on, P00 is configured as an input P01(1) 5 2 I/O P-port I/O. Push-pull design structure. At power on, P01 is configured as an input P02(1) 6 3 I/O P-port I/O. Push-pull design structure. At power on, P02 is configured as an input P03(1) 7 4 I/O P-port I/O. Push-pull design structure. At power on, P03 is configured as an input P04(1) 8 5 I/O P-port I/O. Push-pull design structure. At power on, P04 is configured as an input P05(1) 9 6 I/O P-port I/O. Push-pull design structure. At power on, P05 is configured as an input P06(1) 10 7 I/O P-port I/O. Push-pull design structure. At power on, P06 is configured as an input P07(1) 11 8 I/O P-port I/O. Push-pull design structure. At power on, P07 is configured as an input P10(1) 13 10 I/O P-port I/O. Push-pull design structure. At power on, P10 is configured as an input P11(1) 14 11 I/O P-port I/O. Push-pull design structure. At power on, P11 is configured as an input P12(1) 15 12 I/O P-port I/O. Push-pull design structure. At power on, P12 is configured as an input P13(1) 16 13 I/O P-port I/O. Push-pull design structure. At power on, P13 is configured as an input P14(1) 17 14 I/O P-port I/O. Push-pull design structure. At power on, P14 is configured as an input P15(1) 18 15 I/O P-port I/O. Push-pull design structure. At power on, P15 is configured as an input P16(1) 19 16 I/O P-port I/O. Push-pull design structure. At power on, P16 is configured as an input P17(1) 20 17 I/O P-port I/O. Push-pull design structure. At power on, P17 is configured as an input SCL 22 19 Input Serial clock bus. Connect to VCC through a pull-up resistor SDA 23 20 Input Serial data bus. Connect to VCC through a pull-up resistor VCC 24 21 — Supply voltage (1) If port is unused, it must be tied to either VCC or GND through a resistor of moderate value (about 10 kΩ) www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCA9535

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 6 V VI Input voltage(2) –0.5 6 V VO Output voltage(2) –0.5 6 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input-output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –50 mA ICC Continuous current through GND –250 mA Continuous current through VCC 160 mA Tj(MAX) Maximum junction temperature 100 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 1.65 5.5 V VIH High-level input voltage SCL, SDA 0.7 × VCC VCC (1) V A2–A0, P07–P00, P17–P10 0.7 × VCC 5.5 V VIL Low-level input voltage SCL, SDA, A2–A0, P07–P00, P17–P10 –0.5 0.3 × VCC V IOH High-level output current P07–P00, P17–P10 –10 mA IOL Low-level output current(2) P07–P00, P17–P10 Tj ≤ 65°C 25 mATj ≤ 85°C 18 Tj ≤ 100°C 11 IOL Low-level output current(2) INT, SDA Tj ≤ 85°C 6 mA Tj ≤ 100°C 3.5 TA Operating free-air temperature –40 85 °C (1) For voltages applied above VCC, an increase in ICC results. (2) The values shown apply to specific junction temperatures, which depend on the RθJA of the package used. See the Calculating Junction Temperature and Power Dissipation section on how to calculate the junction temperature. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) TCA9535 UNITPW (TSSOP) DB (SSOP) RTW (WQFN) RGE (VQFN)

24 PINS 24 PINS 24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 108.8 92.9 43.6 48.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 54 53.5 46.2 58.1 °C/W RθJB Junction-to-board thermal resistance 62.8 50.4 22.1 27.1 °C/W ψJT Junction-to-top characterization parameter 11.1 21.9 1.5 3.3 °C/W ψJB Junction-to-board characterization parameter 62.3 50.1 22.2 27.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 10.7 15.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V –1.2 V VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.5 V VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V VOH P-port high-level output voltage(2) IOH = –8 mA 1.65 V 1.2 V 2.3 V 1.8 3 V 2.6 4.75 V 4.1 IOH = –10 mA

1.65 V 1

2.3 V 1.7 3 V 2.5

4.75 V 4

SDA VOL = 0.4 V 1.65 V to 5.5 V 3 mAP port(3) VOL = 0.5 V 1.65 V to 5.5 V 8 VOL = 0.7 V 1.65 V to 5.5 V 10 INT VOL = 0.4 V 1.65 V to 5.5 V 3 II Input leakage current SCL, SDA Input leakage VI = VCC or GND 1.65 V to 5.5 V ±1 μA A2–A0 Input leakage VI = VCC or GND 1.65 V to 5.5 V ±1 IIH Input high leakage current P port VI = VCC 1.65 V to 5.5 V 1 μA IIL Input low leakage current P port VI = GND 1.65 V to 5.5 V –1 μA www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCA9535

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT ICC Quiescent current Operating mode VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz, No load

5.5 V 22 40

μA

3.6 V 11 30

2.7 V 8 19

1.95 V 5 11

VI = VCC, IO = 0, I/O = inputs, fSCL = 0 kHz, No load 5.5 V 1.5 3.9 3.6 V 0.9 2.2 2.7 V 0.6 1.8 1.95 V 0.6 1.5 VI = GND, IO = 0, I/O = inputs, fSCL = 0 kHz, No load 5.5 V 1.5 8.7 3.6 V 0.9 4 2.7 V 0.6 3 1.95 V 0.4 2.2 CI Input capacitance SCL VI = VCC or GND 1.65 V to 5.5 V 3 8 pF Cio Input-output pin capacitance SDA VIO = VCC or GND 1.65 V to 5.5 V 3 9.5 pF P port VIO = VCC or GND 1.65 V to 5.5 V 3.7 9.5 (1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C. (2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA. (3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2) MIN MAX UNIT I2C BUS—STANDARD MODE fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 ns tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capacitive load 400 pF I2C BUS—FAST MODE fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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6.6 I2C Interface Timing Requirements (continued)

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2) MIN MAX UNIT tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns ticf I2C input fall time 20 × (VCC /

5.5 V) 300 ns

tocf I2C output fall time 10-pF to 400-pF bus 20 × (VCC / tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 µs tvd(data) Valid data time SCL low to SDA output valid 0.9 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 µs Cb I2C bus capacitive load 400 pF

6.7 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-2 and Figure 7-3) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tiv Interrupt valid time P port INT 4 μs tir Interrupt reset delay time SCL INT 4 μs tpv Output data valid; For VCC = 2.3 V–5.5 V SCL P port 200 ns Output data valid; For VCC = 1.65 V–2.3 V 300 ns tps Input data setup time P port SCL 150 ns tph Input data hold time P port SCL 1 μs www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCA9535

6.8 Typical Characteristics

TA = 25°C (unless otherwise noted) TA - Temperature (°C) ICC - Supply Current (µA) -40 -15 10 35 60 85 D001 Vcc = 1.65 V Vcc = 1.8 V Vcc = 2.5 V Vcc = 3.3 V Vcc = 3.6 V Vcc = 5 V Vcc = 5.5V Figure 6-1. Supply Current vs Temperature for Different Supply Voltage (VCC) TA - Temperature (°C) ICC - Supply Current (µA) -40 -15 10 35 60 85 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 D002 Vcc = 1.65 V Vcc = 1.8 V Vcc = 2.5 V Vcc = 3.3 V Vcc = 3.6 V Vcc = 5 V Vcc = 5.5V Figure 6-2. Standby Supply Current vs Temperature for Different Supply Voltage (VCC) VCC - Supply Voltage (V) ICC - Supply Current (µA) D003 -40qC 25qC 85qC Figure 6-3. Supply Current vs Supply Voltage for Different Temperature (TA) VOL - Output Low Voltage (V) IOL - Sink Current (mA) D004 VCC = 1.65 V -40qC 25qC 85qC Figure 6-4. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 1.65 V VOL - Output Low Voltage (V) IOL - Sink Current (mA) D005 VCC = 1.8 V -40qC 25qC 85qC Figure 6-5. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 1.8 V VOL - Output Low Voltage (V) IOL - Sink Current (mA) D006 VCC = 2.5 V -40qC 25qC 85qC Figure 6-6. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 2.5 V TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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6.8 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) VOL - Output Low Voltage (V) IOL - Sink Current (mA) D007 VCC = 3.3 V -40qC 25qC 85qC Figure 6-7. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 3.3 V VOL - Output Low Voltage (V) IOL - Sink Current (mA) D009 VCC = 5 V -40qC 25qC 85qC Figure 6-8. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 5 V VOL - Output Low Voltage (V) IOL - Sink Current (mA) D010 VCC = 5.5 V -40qC 25qC 85qC Figure 6-9. I/O Sink Current vs Output Low Voltage for Different Temperature (TA) for VCC = 5.5 V TA - Temperature (°C) VOL - Output Low Voltage (V) -40 -15 10 35 60 85 100 150 200 250 300 D011

1.8 V, 1 mA

1.8 V, 10 mA

3.3 V, 1mA

3.3 V, 10 mA

5 V, 1 mA

5 V, 10 mA

Figure 6-10. I/O Low Voltage vs Temperature for Different VCC and IOL VCC-VOH - Output High Voltage (V) IOH - Source Current (mA) D012 VCC = 1.65 V -40qC 25qC 85qC Figure 6-11. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 1.65 V VCC-VOH - Output High Voltage (V) IOH - Source Current (mA) D013 VCC = 1.8 V -40qC 25qC 85qC Figure 6-12. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 1.8 V www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCA9535

TA = 25°C (unless otherwise noted) VCC-VOH - Output High Voltage (V) IOH - Source Current (mA) D014 VCC = 2.5 V -40qC 25qC 85qC Figure 6-13. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 2.5 V VCC-VOH - Output High Voltage (V) IOH - Source Current (mA) D015 VCC = 3.3 V -40qC 25qC 85qC Figure 6-14. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 3.3 V VCC-VOH - Output High Voltage (V) IOH - Source Current (mA) D016 VCC = 5 V -40qC 25qC 85qC Figure 6-15. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 5 V VCC-VOH - Output High Voltage (V) IOH - Source Current (mA) D017 VCC = 5.5 V -40qC 25qC 85qC Figure 6-16. I/O Source Current vs Output High Voltage for Different Temperature (TA) for VCC = 5.5 V TA - Temperature (°C) VCC-VOH - I/O High Voltage (mV) -40 -15 10 35 60 85 100 150 200 250 300 350 400 D018

1.65 V, 10 mA

2.5 V, 10 mA

3.6 V, 10 mA

5.5 V, 10 mA

Figure 6-17. VCC – VOH Voltage vs Temperature for Different VCC TA - Temperature (°C) Delta ICC (µA) -40 -15 10 35 60 85 D019 1.65 V 1.8 V 2.5 V 3.3 V 5 V 5.5 V Figure 6-18. Δ ICC vs Temperature for Different VCC (VI = VCC – 0.6 V) TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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Parameter Measurement Information A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCA9535

0.7 × VCC 0.3 × VCC 0.7 × VCC 0.3 × VCC 0.7 × VCC 0.3 × VCC 0.7 × VCC 0.3 × VCC INT SCL tiv Interrupt Load Configuration RL = 4.7 kΩ VCC CL = 100 pF (see Note A) DUT INT SCL SDA INT Start Condition R/W Read From Port Data Into Port Stop Condition ACK From Controller NACK From Controller ACK From Target Data From PortTarget Address Data From Port 8765432

1 A Data 1 Data 4A NA P

Port ( ) Pn A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 7-2. Interrupt Load Circuit and Voltage Waveforms TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 7-3. P-Port Load Circuit and Voltage Waveforms www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCA9535

7 Detailed Description

7.1 Overview

The TCA9535 device is a 16-bit I/O expander for the I 2C bus and is designed for 1.65-V to 5.5-V V CC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface. The TCA9535 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system controller. The TCA9535 open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system controller that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9535 can remain a simple target device. The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption. The TCA9535 device is similar to the PCA9555, except for the removal of the internal I/O pull-up resistor, which greatly reduces power consumption when the I/Os are held low. The TCA9535 is equivalent to the PCA9535 with lower voltage support (down to VCC = 1.65 V), and also improved power-on-reset circuitry for different application scenarios. Three hardware pins (A0, A1 and A2) are used to program and vary the fixed I 2C address and allow up to 8 devices to share the same I2C bus or SMBus.

7.2 Functional Block Diagram

Pin numbers shown are for the PW package. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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All I/Os are set to inputs at reset. Figure 7-1. Logic Diagram (Positive Logic) VCC CLK D Q FF Configuration Register Data From Shift Register Data From Shift Register QWrite Configuration Pulse CLK D Q FF QWrite Pulse Output Port Register GND I/O Pin Output Port Register Data CLK D Q FF Q Input Port Register Read Pulse CLK D Q FF Q Polarity Inversion Register Write Polarity Pulse Input Port Register Data Polarity Register Data To INT Data From Shift Register At power-on reset, all registers return to default values. Figure 7-2. Simplified Schematic of P-Port I/Os

7.3 Feature Description

7.3.1 5-V Tolerant I/O Ports The TCA9535 features I/O ports, which are tolerant up to 5 V. This allows the TCA9535 to be connected to a large array of devices. To minimize ICC, any input signals must be designed so the input voltage stays within V IH and VIL of the device as described in the Electrical Characteristics section.

7.3.2 Hardware Address Pins

The TCA9535 features 3 hardware address pins (A0, A1, and A2). The user selects the device I 2C address by pulling each pin to either V CC or GND to signify the bit value in the address. This allows up to 8 TCA9535 devices to be on the same bus without address conflicts. See the Functional Block Diagram for the 3 address pins. The voltage on the pins must not change while the device is powered up in order to prevent possible I 2C glitches as a result of the device address changing during a transmission. All of the pins must be tied either to VCC or GND and cannot be left floating. www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCA9535

7.3.3 Interrupt ( INT) Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or the interrupt caused by port 1 is not cleared by a read of port 0. INT has an open-drain structure. INT requires a pull-up resistor to VCC of moderate value (typically about 10 kΩ).

7.4 Device Functional Modes

7.4.1 Power-On Reset (POR)

When power (from 0 V) is applied to V CC, an internal power-on reset circuit holds the TCA9535 in a reset condition until VCC has reached VPORR. At that time, the reset condition is released. The TCA9535 registers and I2C-SMBus state machine initialize to their default states. Then, V CC must be lowered to below V PORF and back up to the operating voltage for a power-reset cycle.

7.4.2 Powered-Up

When power has been applied to VCC above VPORR, and the POR has taken place, the device is in a functioning mode. In this state, the device is ready to accept any incoming I2C requests and is monitoring for changes on the input ports.

7.5 Programming

7.5.1 I2C Interface

The TCA9535 has a standard bidirectional I 2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I 2C bus has a specific device address to differentiate between other target devices that are on the same I 2C bus. Many target devices require configuration upon startup to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see Understanding the I2C Bus application report, SLVA704. The physical I 2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to V CC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I 2C lines. For further details, see I2C Pull-up Resistor Calculation application report, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Table 7-1. Figure 7-3 and Figure 7-4 show the general procedure for a controller to access a target device: 1. If a controller wants to send data to a target:

• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition. 2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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• Controller-receiver terminates the transfer with a STOP condition. SCL SDA START Condition STOP Condition Data Transfer Figure 7-3. Definition of Start and Stop Conditions SCL SDA MSB Bit Bit Bit Bit Bit Bit LSB Byte: 1010 1010 ( 0xAAh ) 1 0 1 0 1 0 1 0 SDA line stable while SCL line is high ACK ACK Figure 7-4. Bit Transfer Table 7-1 shows the interface definition. Table 7-1. Interface Definition BYTE BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C target address L H L L A2 A1 A0 R/ W P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00 P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10

7.5.1.1 Bus Transactions

Data is exchanged between the controller and the TCA9535 through write and read commands, and this is accomplished by reading from or writing to registers in the target device. Registers are locations in the memory of the target which contain information, whether it be the configuration information or some sampled data to send back to the controller. The controller must write information to these registers in order to instruct the target device to perform a task. www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCA9535

7.5.1.1.1 Writes

To write on the I 2C bus, the controller sends a START condition on the bus with the address of the target, as well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the controller then sends the register address of the register to which it wishes to write. The target acknowledges again, letting the controller know it is ready. After this, the controller starts sending the register data to the target until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller terminates the transmission with a STOP condition. See the Control Register and Command Byte section to see list of the TCA9535 internal registers and a description of each one. Figure 7-5 shows an example of writing a single byte to a target register. Write to one register in a device S 0 1 0 0 A2 A1 A0 0 Device (Target) Address (7 bits) B7 B6 B5 B4 B3 B2 B1 B0 A Register Address N (8 bits) A START ACK ACK A Data Byte to Register N (8 bits) P STOPACK Controller controls SDA line Target controls SDA line R/W=0 D0D1D2D3D4D5D6D7 Figure 7-5. Write to Register Figure 7-6 shows the Write to the Polarity Inversion Register. S 0 1 0 0 A2 A1 A0 0 Device (Target) Address (7 bits) 1 0 00 0 0 0 0 A Register Address 0x02 (8 bits) D7 D6 D5 D4 D3 D2 D1 D0 A Data Byte to Register 0x02 (8 bits) A P START R/W=0 ACK ACK ACK STOP Controller controls SDA line Target controls SDA line Figure 7-6. Write to the Polarity Inversion Register Figure 7-7 shows the Write to Output Port Registers. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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00 0 0 0 0 0 1 0.7 0.0 Data 11.7 1.0 AS 0 1 0 0 A2 A1 A0 0 tpv P Target Address Command Byte Data to Port 0 Data to Port 1 Start Condition Acknowledge From Target Write to Port Data Out from Port 1 Data Out from Port 0 Data Valid Acknowledge From Target Acknowledge From Target Figure 7-7. Write to Output Port Registers

7.5.1.1.2 Reads

Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target, the controller must first instruct the target which register it wishes to read from. This is done by the controller starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. When the target acknowledges this register address, the controller sends a START condition again, followed by the target address with the R/ W bit set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases the SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller becomes the controller-receiver, and the target becomes the target-transmitter. The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it is ready for more data. When the controller has received the number of bytes it is expecting, it sends a NACK, signaling to the target to halt communications and release the bus. The controller follows this up with a STOP condition. See the Control Register and Command Byte section to see list of the TCA9535's internal registers and a description of each one. Figure 7-8 shows an example of reading a single byte from a target register. Read from one register in a device S 0 1 0 0 A2 A1 A0 0 Device (Target) Address (7 bits) B7 B6 B5 B4 B3 B2 B1 B0 A Register Address N (8 bits) A START ACK ACK A2Sr 0 1 0 0 A1 A0 Device (Target) Address (7 bits) Repeated START

1 A D7 D6 D5 D4 D3 D2 D1 D0 NA

Data Byte from Register N (8 bits) P NACK STOPACK Controller controls SDA line Target controls SDA line R/W=0 R/W=1 Figure 7-8. Read from Register After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCA9535

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus controller must not acknowledge the data. Figure 7-9 and Figure 7-10 show two different scenarios of Read Input Port Register. 1 2 3 4 5 6 7 8 9 S 10 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A I0.x 7 6 5 4 3 2 1 0 A I1.x 7 6 5 4 3 2 1 0 A I0.x 7 6 5 4 3 2 1 0 1 I1.x P R/W SCL SDA INT tirtiv Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 Acknowledge From Controller Acknowledge From Target Acknowledge From Controller Acknowledge From Controller No Acknowledge From Controller Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from the P port. Figure 7-9. Read Input Port Register, Scenario 1 1 2 3 4 5 6 7 8 9 S 1 00 0 A2 A1 A0 01 A A 10.x A 11.x A 10.x 11.x P R/W SCL SDAINT tirtiv t t t t ph iv iv ph 00 10 03 11 tps t t ph ir 11 12 Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 Data 02Data 01Data 00 Data 03 DataDataData 10 Acknowledge From Target Acknowledge From Controller Acknowledge From Controller Acknowledge From Controller No Acknowledge From Controller Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from the P port. Figure 7-10. Read Input Port Register, Scenario 2

7.5.2 Device Address

Figure 7-11 shows the address byte of the TCA9535. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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Figure 7-11. TCA9535 Address Table 7-2 shows the address reference of the TCA9535. Table 7-2. Address Reference INPUTS I2C BUS TARGET ADDRESS A2 A1 A0 L L L 32 (decimal), 0×20 (hexadecimal) L L H 33 (decimal), 0x21 (hexadecimal) L H L 34 (decimal), 0x22 (hexadecimal) L H H 35 (decimal), 0x23 (hexadecimal) H L L 36 (decimal), 0x24 (hexadecimal) H L H 37 (decimal), 0x25 (hexadecimal) H H L 38 (decimal), 0x26 (hexadecimal) H H H 39 (decimal), 0x27 (hexadecimal) The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.

7.5.3 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte shown in Table 7-3 that is stored in the control register in the TCA9535. Three bits of this data byte state the operation (read or write) and the internal register (input, output, polarity inversion, or configuration) that is affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. When a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Figure 7-12 shows the control register bits. 0 0 0 B2 B1 B000 Figure 7-12. Control Register Bits Table 7-3. Command Byte CONTROL REGISTER BITS COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULTB2 B1 B0 0 0 0 0x00 Input Port 0 Read byte xxxx xxxx 0 0 1 0x01 Input Port 1 Read byte xxxx xxxx 0 1 0 0x02 Output Port 0 Read-write byte 1111 1111 0 1 1 0x03 Output Port 1 Read-write byte 1111 1111 1 0 0 0x04 Polarity Inversion Port 0 Read-write byte 0000 0000 1 0 1 0x05 Polarity Inversion Port 1 Read-write byte 0000 0000 1 1 0 0x06 Configuration Port 0 Read-write byte 1111 1111 1 1 1 0x07 Configuration Port 1 Read-write byte 1111 1111 www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCA9535

7.6 Register Maps

7.6.1 Register Descriptions

The Input Port registers (registers 0 and 1) shown in Table 7-4 reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration Register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to let the I 2C device know that the Input Port registers are accessed next. Table 7-4. Registers 0 and 1 (Input Port Registers) Default X X X X X X X X Default X X X X X X X X The Output Port registers (registers 2 and 3) shown in Table 7-5 show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 7-5. Registers 2 and 3 (Output Port Registers) Default 1 1 1 1 1 1 1 1 Default 1 1 1 1 1 1 1 1 The Polarity Inversion registers (registers 4 and 5) shown in Table 7-6 allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding pin's original polarity is retained. Table 7-6. Registers 4 and 5 (Polarity Inversion Registers) Default 0 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 0 The Configuration registers (registers 6 and 7) shown in Table 7-7 configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 7-7. Registers 6 and 7 (Configuration Registers) Default 1 1 1 1 1 1 1 1 Default 1 1 1 1 1 1 1 1 TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

bus may contain any number of other target devices. The TCA9535 is typically in a remote location from the controller, placed close to the GPIOs to which the controller needs to monitor or control. IO Expanders such as the TCA9535 are typically used for controlling LEDs (for feedback or status lights), controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.

8.2 Typical Application

Figure 8-1 shows an application in which the TCA9535 can be used. P00 P01 P02 P03 P04 P05 A B P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 GND VCC VCC (5 V) Controlled Switch (e.g., CBT Device) GND INT SDA SCL INT Subsystem 1 (e.g., Temperature Sensor) Subsystem 2 (e.g., Counter) TCA9535 SDA SCL INT GND Keypad ALARM RESET ENABLE Subsystem 3 (e.g., Alarm) Controller VDD 100 k ( 3)X 2 k 10 k ( 5)X 10 k ( 4)X Device address is configured as 0100100 for this example. P00, P02, and P03 are configured as outputs. P01, P04–P07, and P10–P17 are configured as inputs. Pin numbers shown are for the PW package. Figure 8-1. Application Schematic

8.2.1 Design Requirements

The designer must take into consideration the system, to be sure not to violate any of the parameters. Table 8-1 shows some key parameters which must not be violated. www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TCA9535

Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE I2C and Subsystem Voltage (VCC) 5 V Output current rating, P-port sinking (IOL) 25 mA I2C bus clock (SCL) speed 400 kHz

8.2.1.1 Calculating Junction Temperature and Power Dissipation

When designing with this device, it is important that the Recommended Operating Conditions not be violated. Many of the parameters of this device are rated based on junction temperature. So junction temperature must be calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature is shown in Equation 1. /c40 /c41j A JA dT T P/c61 /c43 /c113 /c180 (1) θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2. /c40 /c41d CC _ STATIC CC d _ PORT _ L d _ PORT _ HP I V P P/c187 /c180 /c43 /c43 /c229 /c229 (2) Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the summation of power dissipated by each port (with a different equation based on if the port is outputting high, or outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power dissipation. /c40 /c41d _ PORT _ L OL OLP I V /c61 /c180 (3) Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the port is the VOL of the port multiplied by the current it is sinking. /c40 /c41/c40 /c41d _ PORT _H OH CC OHP I V V /c61 /c180 /c45 (4) Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the port is the current sourced by the port multiplied by the voltage drop across the device (difference between V CC and the output voltage).

8.2.1.2 Minimizing ICC When I/O is Used to Control LED

When an I/O is used to control an LED, normally it is connected to V CC through a resistor as shown in Figure 8-1. Because the LED acts as a diode, when the LED is off, the I/O V IN is about 1.2 V less than V CC. The ΔICC parameter in the Electrical Characteristics table shows how I CC increases as V IN becomes lower than V CC. For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to V CC when the LED is off to minimize current consumption. Figure 8-2 shows a high-value resistor in parallel with the LED. Figure 8-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V IN at or above V CC and prevent additional supply current consumption when the LED is off. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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100 kΩ Figure 8-2. High-Value Resistor in Parallel With LED VCC

3.3 V 5 V

Figure 8-3. Device Supplied by Lower Voltage

8.2.2 Detailed Design Procedure

The pull-up resistors, R P, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all targets on the I 2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL as shown in Equation 5. CC OL(max) p(min) OL V V R I /c45 /c61 (5) The maximum pull-up resistance is a function of the maximum rise time, t r (300 ns for fast-mode operation, f SCL = 400 kHz) and bus capacitance, Cb as shown in Equation 6. r p(max) b tR 0.8473 C/c61 /c180 (6) The maximum bus capacitance for an I 2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9535, C i for SCL or CIO for SDA, the capacitance of wires/connections/traces, and the capacitance of additional targets on the bus. For further details, refer to I2C Pull-up Resistor Calculation application report, SLVA689. www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCA9535

8.2.3 Application Curves

Bus Capacitance (pF) Maximum Pull-Up Resistance (k:) 0 50 100 150 200 250 300 350 400 450 D008 Standard-Mode Fast-Mode Standard-mode: fSCL = 100 kHz, tr = 1 µs Fast-mode: fSCL = 400 kHz, tr = 300 ns Figure 8-4. Maximum Pull-Up Resistance (Rp(max)) vs Bus Capacitance (Cb) Pull-Up Reference Voltage (V) Minimum Pull-Up Resistance (k:) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 D009 VDPUX > 2 V VDUPX </= 2 VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V VOL = 0.4 V, IOL = 3 mA when VCC > 2 V Figure 8-5. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VCC) TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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9 Power Supply Recommendations

In the event of a glitch or data corruption, TCA9535 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 9-1 and Figure 9-2. VCC Ramp-Up Re-Ramp-Up Time to Re-Ramp Time Ramp-Down VCC_RT VCC_RTVCC_FT VCC_TRR_GND Figure 9-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC VCC Ramp-Up Time to Re-Ramp Time Ramp-Down VIN drops below POR levels VCC_RTVCC_FT VCC_TRR_VPOR50 Figure 9-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC Table 9-1 specifies the performance of the power-on reset feature for TCA9535 for both types of power-on reset. Table 9-1. Recommended Supply Sequencing And Ramp Rates PARAMETER(1) MIN TYP MAX UNIT VCC_FT Fall rate See Figure 9-1 0.1 ms VCC_RT Rise rate See Figure 9-1 0.01 ms VCC_TRR Time to re-ramp (when VCC drops to VVOR_MIN – 50 mV or when VCC drops to GND) See Figure 9-1 1 µs VCC_GH The level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GW See Figure 9-3 1.2 V VCC_MV The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) See Figure 9-3 1.5 V VCC_GW Glitch width that will not cause a functional disruption See Figure 9-3 10 μs VPORF Voltage trip point of POR on falling VCC 0.75 1 1 V VPORR Voltage trip point of POR on rising VCC 1.2 1.5 V (1) TA = –40°C to 85°C (unless otherwise noted) Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (V CC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-3 and Table 9-1 provide more information on how to measure these specifications. www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCA9535

VCC_GH VCC_GW Figure 9-3. Glitch Width And Glitch Height VPORR is critical to the power-on reset. V PORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of V POR differs based on the VCC being lowered to or from 0. Figure 9-4 and Table 9-1 provide more details on this specification. VCC VPOR VPORF Time POR Time Figure 9-4. VPOR TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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10 Layout

10.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9535, common PCB layout practice must be followed, but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the V CC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These capacitors must be placed as close to the TCA9535 as possible. These best practices are shown in the Layout Example. For the layout example provided in the Layout Example , it must be possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (V CC) and ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to V CC, or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in the Layout Example.

10.2 Layout Example

0603 Cap

= Via to GND Plane Figure 10-1. TCA9535 Layout Example www.ti.com TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCA9535

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• I2C Bus Pull-Up Resistor Calculation, SLVA689
• Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695
• Introduction to Logic, SLVA700
• Understanding the I2C Bus, SLVA704
• IO Expander EVM User's Guide, SLVUA59A

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TCA9535 SCPS201E – AUGUST 2009 – REVISED MAY 2022 www.ti.com

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www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCA9535DBR Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535DBR.A Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535DBR.B Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535DBT Active Production SSOP (DB) | 24 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535DBT.A Active Production SSOP (DB) | 24 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535DBT.B Active Production SSOP (DB) | 24 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535MRGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535MRGER.A Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535MRGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535PWR Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535PWR.A Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535PWR.B Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535PWRG4 Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535PWRG4.A Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535PWRG4.B Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW535 TCA9535RGER Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535RGER.A Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535RGER.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535RGERG4 Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535RGERG4.A Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535RGERG4.B Active Production VQFN (RGE) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TD9535 TCA9535RTWR Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 TCA9535RTWR.A Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 TCA9535RTWR.B Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 TCA9535RTWRG4 Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 TCA9535RTWRG4.A Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 TCA9535RTWRG4.B Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PW535 (1) Status: For more details on status, see our product life cycle. Addendum-Page 1

www.ti.com 9-Nov-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9535DBR SSOP DB 24 2000 353.0 353.0 32.0 TCA9535DBT SSOP DB 24 250 353.0 353.0 32.0 TCA9535MRGER VQFN RGE 24 3000 346.0 346.0 33.0 TCA9535PWR TSSOP PW 24 2000 353.0 353.0 32.0 TCA9535PWRG4 TSSOP PW 24 2000 353.0 353.0 32.0 TCA9535RGER VQFN RGE 24 3000 346.0 346.0 33.0 TCA9535RGERG4 VQFN RGE 24 3000 346.0 346.0 33.0 TCA9535RTWR WQFN RTW 24 3000 353.0 353.0 32.0 TCA9535RTWRG4 WQFN RTW 24 3000 353.0 353.0 32.0 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 24X 0.3 0.2 2.45 0.1 24X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.00 20X 0.5 2.5 2X 2.5 A 4.1 3.9 B 4.1 3.9 0.3 0.2 0.5 0.3 VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 6 13 7 12 24 19 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD

25 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

24X (0.25) 24X (0.6) ( 0.2) TYP VIA 20X (0.5) (3.8) (3.8) ( 2.45) (R0.05) TYP (0.975) TYP VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 SYMM 7 12 1924 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 24X (0.6) 24X (0.25) 20X (0.5) (3.8) (3.8) 4X ( 1.08) (0.64) TYP (0.64) TYP (R0.05) TYP VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 7 12 1924

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTW 24 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.5 mm pitch 4224801/A

4219135/B 11/2016www.ti.com WQFN - 0.8 mm max heightPLASTIC QUAD FLATPACK-NO LEADRTW0024B A 0.08C0.1CAB0.05C B SYMMSYMM

NOTES: (continued)3.For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). EXAMPLE BOARD LAYOUT 4219135/B 11/2016www.ti.com WQFN - 0.8 mm max heightRTW0024B PLASTIC QUAD FLATPACK-NO LEADSYMMSYMM LAND PATTERN EXAMPLESCALE: 20X

NOTES: (continued)4.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations. EXAMPLE STENCIL DESIGN 4219135/B 11/2016www.ti.com WQFN - 0.8 mm max heightRTW0024B PLASTIC QUAD FLATPACK-NO LEADSYMMSYMMSOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILEXPOSED PAD 25:78% PRINTED COVERAGE BY AREA UNDER PACKAGESCALE: 20X METALTYP

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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