TCA9534APWRG4.A

TCA9534A TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 42

Technical content

(e.g. Processor) SDA SCL INT VCC GND

• , ENABLE, or control inputs
• or status outputs
• LEDs RESET INT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TCA9534A SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 TCA9534ALowVoltage8-BitI2CandSMBUSLow-PowerI/OExpanderWithInterrupt OutputandConfigurationRegisters

1 Features

1• Low Standby Current Consumption

• I2C to Parallel Port Expander
• Open-Drain Active-Low Interrupt Output
• Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
• 5-V Tolerant I/O Ports
• 400-kHz Fast I2C Bus
• Three Hardware Address Pins Allow up to Eight Devices on the I2C/SMBus
• Input and Output Configuration Register
• Polarity Inversion Register
• Internal Power-On Reset
• Power-Up With All Channels Configured as Inputs
• No Glitch on Power Up
• Noise Filter on SCL/SDA Inputs
• Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101)

2 Applications

• Servers
• Routers (Telecom Switching Equipment)
• Personal Computers
• Personal Electronics (for example: Gaming Consoles)
• Industrial Automation
• Products With GPIO-Limited Processors

3 Description

The TCA9534A is a 16-pin device that provides 8 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol. The device can operate with a power supply voltage ranging from 1.65 V to 5.5 V, which allows for use with a wide range of devices. The device supports both 100-kHz (Standard-mode) and 400-kHz (Fast-mode) clock frequencies. I/O expanders such as the TCA9534A provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and other similar devices. The features of the TCA9534A include an interrupt that is generated on the INT pin. This allows the master to know when an input port changes state. The A0, A1, and A2 hardware selectable address pins allow up to eight TCA9534A devices on the same I2C bus. The device can also be reset to its default sate by cycling the power supply and causing a power-on reset. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TCA9534A TSSOP (16) 5.00 mm × 4.40 mm SOIC (16) 10.30 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic

SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TCA9534A Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Table of Contents

12.2 Receiving Notification of Documentation Updates 30

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (December 2016) to Revision C Page Changes from Revision A (September 2014) to Revision B Page

www.ti.com SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 Product Folder Links: TCA9534A Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated Changes from Original (August 2014) to Revision A Page

SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TCA9534A Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

NO. NAME 1 A0 I Address input. Connect directly to VCC or ground 2 A1 I Address input. Connect directly to VCC or ground 3 A2 I Address input. Connect directly to VCC or ground 4 P0 I/O P-port input-output. Push-pull design structure. At power on, P0 is configured as an input 5 P1 I/O P-port input-output. Push-pull design structure. At power on, P1 is configured as an input 6 P2 I/O P-port input-output. Push-pull design structure. At power on, P2 is configured as an input 7 P3 I/O P-port input-output. Push-pull design structure. At power on, P3 is configured as an input

8 GND — Ground

9 P4 I/O P-port input-output. Push-pull design structure. At power on, P4 is configured as an input 10 P5 I/O P-port input-output. Push-pull design structure. At power on, P5 is configured as an input 11 P6 I/O P-port input-output. Push-pull design structure. At power on, P6 is configured as an input 12 P7 I/O P-port input-output. Push-pull design structure. At power on, P7 is configured as an input 13 INT O Interrupt output. Connect to VCC through a pull-up resistor 14 SCL I Serial clock bus. Connect to VCC through a pull-up resistor 15 SDA I/O Serial data bus. Connect to VCC through a pull-up resistor

16 VCC — Supply voltage

www.ti.com SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 Product Folder Links: TCA9534A Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage –0.5 6 V VI Input voltage (2) –0.5 6 V VO Output voltage (2) –0.5 6 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input-output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current through a single P-port VO = 0 to VCC 50 mA IOH Continuous output high current through a single P-port VO = 0 to VCC –50 mA ICC Continuous current through GND by all P-ports, INT, and SDA 250 mA Continuous current through VCC by all P-ports –160 TJ(MAX) Maximum junction temperature 100 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 Handling Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 (1) The SCL and SDA pins shall not be at a higher potential than the supply voltage VCC in the application, or an increase in leakage current, II, will result. (2) The values shown apply to specific junction temperatures. See the Calculating Junction Temperature and Power Dissipation section on how to calculate the junction temperature.

6.3 Recommended Operating Conditions

VCC Supply voltage 1.65 5.5 V VIH High-level input voltage SCL, SDA VCC = 1.65 V to 5.5 V 0.7 × VCC VCC (1) V A0, A1, A2, P7–P0 VCC = 1.65 V to 2.7 V 0.7 × VCC 5.5 VIL Low-level input voltage SCL, SDA VCC = 1.65 V to 5.5 V –0.5 0.3 × VCC V A0, A1, A2, P7–P0 VCC = 1.65 V to 2.7 V –0.5 0.3 × VCC VCC = 3 V to 5.5 V –0.5 0.2 × VCC IOH High-level output current Any P-port, P7–P0 –10 mA IOL Low-level output current(2) P00-P07, P10-P17 Tj ≤ 65°C 25 mA Tj ≤ 85°C 18 Tj ≤ 100°C 9 INT, SDA Tj ≤ 85°C 6 Tj ≤ 100°C 3 ICC Continuous current through GND All P-ports P7-P0, INT, and SDA 200 mA Continuous current through VCC All P-ports P7-P0 –80 TA Operating free-air temperature –40 85 °C

SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TCA9534A Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TCA9534A UNITPW (TSSOP) DW (SOIC)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 122 92.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.4 53.8 °C/W RθJB Junction-to-board thermal resistance 67.1 56.9 °C/W ψJT Junction-to-top characterization parameter 10.8 26.4 °C/W ψJB Junction-to-board characterization parameter 66.5 56.4 °C/W (1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C. (2) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os (P-ports P7-P0) through VCC must be limited to a maximum current of 80 mA. (3) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA. (4) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P- ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA. (5) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V –1.2 V VPOR R Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.5 V VPOR F Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V VOH P-port high-level output voltage(2) IOH = –8 mA 1.65 V 1.2 V 2.3 V 1.8 3 V 2.6 4.5 V 4.1 IOH = –10 mA

1.65 V 1

2.3 V 1.7 3 V 2.5

4.5 V 4

SDA(3) VOL = 0.4 V 1.65 V to 5.5 V 3 mAP port(4) VOL = 0.5 V 1.65 V to 5.5 V 8 VOL = 0.7 V 1.65 V to 5.5 V 10 INT (5) VOL = 0.4 V 1.65 V to 5.5 V 3 II SCL, SDA VI = VCC or GND 1.65 V to 5.5 V μA A2–A0 ±1 IIH P port VI = VCC 1.65 V to 5.5 V 1 μA IIL P port VI = GND 1.65 V to 5.5 V –1 μA

www.ti.com SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 Product Folder Links: TCA9534A Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT ICC Operating mode VI = VCC or GND, IO = 0, I/O = inputs, fscl = 400 kHz, no load

5.5 V 22 40

μA

3.6 V 11 30

2.7 V 8 19

1.65 5 11 Standby mode VI = GND, IO = 0, I/O = inputs, fscl = 0 kHz, no load VI = VCC 5.5 V 1.5 3.9 3.6 V 0.9 2.2 2.7 V 0.6 1.8 1.95 V 0.4 1.5 VI = GND 5.5 V 1.5 8.7 3.6 V 0.9 4 2.7 V 0.6 3 1.95 V 0.4 2.2 Ci SCL VI = VCC or GND 1.65 V to 5.5 V 3 8 pF Cio SDA VIO = VCC or GND 1.65 V to 5.5 V 3 9.5 pF P port 3.7 9.5

6.6 I2C Interface Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 19) MIN MAX UNIT STANDARD MODE fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 ns tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C start or repeated start condition hold 4 µs tsps I2C stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 ns tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capacitive load 400 pF FAST MODE fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns

SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TCA9534A Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated I2C Interface Timing Requirements (continued) over operating free-air temperature range (unless otherwise noted) (see Figure 19) MIN MAX UNIT ticf I2C input fall time 20 × (VDD /

5.5 V) 300 ns

tocf I2C output fall time 10-pF to 400-pF bus 20 × (VDD / tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 0.6 µs tsth I2C start or repeated start condition hold 0.6 µs tsps I2C stop condition setup 0.6 µs tvd(data) Valid data time SCL low to SDA output valid 0.9 ns tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 µs Cb I2C bus capacitive load 400 pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see Figure 20 and Figure 21) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT STANDARD and FAST MODE tiv Interrupt valid time P port INT 4 µs tir Interrupt reset delay time SCL INT 4 µs tpv Output data valid SCL P7–P0 350 ns tps Input data setup time P port SCL 100 ns tph Input data hold time P port SCL 1 μs

6.8 Typical Characteristics

Figure 1. Supply Current vs Temperature for Different Figure 2. Standby Supply Current vs Temperature for Figure 3. Supply Current vs Supply Voltage for Different Figure 4. I/O Sink Current vs Output Low Voltage for Figure 5. I/O Sink Current vs Output Low Voltage for Figure 6. I/O Sink Current vs Output Low Voltage for

1.8 V, 1 mA

1.8 V, 10 mA

3.3 V, 1mA

3.3 V, 10 mA

5 V, 1 mA

5 V, 10 mA

Figure 7. I/O Sink Current vs Output Low Voltage for Figure 8. I/O Sink Current vs Output Low Voltage for Figure 9. I/O Sink Current vs Output Low Voltage for Figure 10. II/O Low Voltage vs Temperature for Different VCC Figure 11. I/O Source Current vs Output High Voltage for Figure 12. I/O Source Current vs Output High Voltage for

1.65 V, 10 mA

2.5 V, 10 mA

3.6 V, 10 mA

5.5 V, 10 mA

Figure 13. I/O Source Current vs Output High Voltage for Figure 14. I/O Source Current vs Output High Voltage for Figure 15. I/O Source Current vs Output High Voltage for Figure 16. I/O Source Current vs Output High Voltage for Figure 17. VCC – VOH Voltage vs Temperature for Different Figure 18. Δ ICC vs Temperature for Different VCC (VI = VCC –

0.3 V/c180 CC

0.7 V/c180 CC

1 I C□address

7 Parameter Measurement Information

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 19. I2C Interface Load Circuit and Voltage Waveforms

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 20. Interrupt Load Circuit and Voltage Waveforms

A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 21. P-Port Load Circuit and Voltage Waveforms

www.ti.com SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 Product Folder Links: TCA9534A Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TCA9534A is an 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I2C interface (serial clock, SCL, and serial data, SDA, pins). The TCA9534A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The INT pin can be connected to the interrupt input of a micro-controller. By sending an interrupt signal on this line, the remote I/O can inform the micro-controller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9534A can remain a simple slave device. The device outputs (latched) have high- current drive capability for directly driving LEDs. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C slave address and allow up to eight devices to share the same I2C bus or SMBus. The system master can reset the TCA9534A in the event of a timeout or other improper operation by cycling the power supply and causing a power-on reset (POR). A reset puts the registers in their default state and initializes the I2C /SMBus state machine. The TCA9534A consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The TCA9534A is identical to the TCA9554 except for the removal of the internal I/O pull-up resistors, which greatly reduces power consumption when the I/Os are held LOW.

8.2 Functional Block Diagram

Pin numbers shown are for the PW package. Figure 22. Functional Block Diagram At power-on reset, all registers return to default values. Figure 23. Simplified Schematic Of P0 To P7

www.ti.com SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 Product Folder Links: TCA9534A Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pull-up resistor to VCC.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9534A in a reset condition until VCC has reached VPORR. At that point, the reset condition is released and the TCA9534A registers and SMBus/I2C state machine initialize to their default states. After that, VCC must be lowered to below VPORF and then back up to the operating voltage for a power-on reset cycle.

8.5 Programming

8.5.1 I2C Interface

The TCA9534A has a standard bidirectional I2C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I2C bus has a specific device address to differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see the Understanding the I2C Bus application report. The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I2C lines. For further details, see the I2C Pull-up Resistor Calculation application report. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. Figure 24 and Figure 25 show the general procedure for a master to access a slave device: 1. If a master wants to send data to a slave: – Master-transmitter sends a START condition and addresses the slave-receiver. – Master-transmitter sends data to slave-receiver. – Master-transmitter terminates the transfer with a STOP condition. 2. If a master wants to receive or read data from a slave: – Master-receiver sends a START condition and addresses the slave-transmitter. – Master-receiver sends the requested register to read to slave-transmitter. – Master-receiver receives data from the slave-transmitter.

8.6 Register Maps

8.6.1 Device Address

Figure 26 shows the address byte of the TCA9534A. Figure 26. TCA9534A Address Table 2 shows the TCA9534A address reference. Table 2. Address Reference is selected, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

register can be written or read through the I2C bus. The command byte is sent only during a write transmission. new command byte has been sent. Figure 27. Control Register Bits Table 3 shows the TCA9534A command byte. Table 3. Command Byte Table

8.6.3 Register Descriptions

registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 4. Input Port register is accessed next. Table 4. Register 0 (Input Port Register) Table Table 5. Register 1 (Output Port Register) Table register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6. Table 6. Register 2 (Polarity Inversion Register) Table cleared to 0, the corresponding port pin is enabled as an output. See Table 7. Table 7. Register 3 (Configuration Register) Table

8.6.3.1 Bus Transactions

Data is exchanged between the master and the TCA9534A through write and read commands.

8.6.3.1.1 Writes

transmission with a STOP condition. See Table 3 to see list of the internal registers and a description of each one. Figure 28 shows an example of writing a single byte to a slave register. Figure 28. Write to Register Figure 29 shows an example of writing to the output port register. Figure 29. Write to Output Port Register Figure 30 shows an example of writing to the configuration or polarity inversion registers.

1 A D7 D6 D5 D4 D3 D2 D1 D0 NA

Figure 30. Write to Configuration or Polarity Inversion Registers

8.6.3.1.2 Reads

master-receiver, and the slave becomes the slave-transmitter. The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data. slave to halt communications and release the bus. The master follows this up with a STOP condition. See Table 3 for the list of the internal registers and a description of each one. NACK until a command byte-register address is set as described above. Figure 31 shows an example of reading a single byte from a slave register. Figure 31. Read From Register acknowledge the data. See Figure 32.

1 A Data 1 Data 4A NA P

A. This figure assumes the command byte has previously been programmed with 00h. B. Transfer of data can be stopped at any moment by a Stop condition. call and actual data transfer from the P port. See the Reads section for these details. Figure 32. Read From Input Port Register

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 33 shows an application in which the TCA9534A can be used.

• Inputs from other ICs, such as interrupt signals from sensors
• Inputs from physical buttons (for detecting button presses)
• Outputs to control RESET or ENABLE signals on other ICs
• Outputs for controlling LEDs for visual feedback to a user

9.2 Typical Application

that can be powered on while VCC is powered off, then the supply current, ICC, increases as a result. Device address is configured as 0111000 for this example. P0, P2, and P3 are configured as outputs. P1, P4, and P5 are configured as inputs. P6 and P7 are not used and must be configured as outputs. Figure 33. Application Schematic

9.2.1 Design Requirements

9.2.1.1 Calculating Junction Temperature and Power Dissipation

When designing with the TCA9534A, it is important that the Recommended Operating Conditions not be violated. Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2. port is the VOL of the port multiplied by the current it is sinking.

9.2.1.2 Minimizing ICC When I/Os Control LEDs

Figure 33. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode, value resistor in parallel with the LED. Figure 35 shows VCC less than the LED supply voltage by at least VT. when the P-port is configured as an input and the LED is off. Figure 34. High-Value Resistor in Parallel With LED

3.3 V 5 V

Figure 35. Device Supplied by a Lower Voltage

9.2.2 Detailed Design Procedure

VCC, VOL,(max), and IOL as shown in Equation 5. 400 kHz) and bus capacitance, Cb as shown in Equation 6. Cio for SDA, the capacitance of wires, connections, traces, and the capacitance of additional slaves on the bus.

9.2.3 Application Curves

Figure 36. Maximum Pull-Up resistance (Rp(max)) vs Bus Figure 37. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in and Figure 38. Figure 38. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC Table 8. Recommended Supply Sequencing and Ramp Rates(1) information on how to measure these specifications. Figure 39. Glitch Width and Glitch Height

on the VCC being lowered to or from 0. Figure 40 and Table 8 provide more details on this specification. Figure 40. VPOR

8 GND 9P4

11 Layout

11.1 Layout Guidelines

not a concern for I2C signal speeds. capacitors must be placed as close to the TCA9534A as possible. These best practices are shown in Figure 41. routed to the opposite side of the board, but this technique is not demonstrated in Figure 41.

11.2 Layout Example

Figure 41. TCA9534A Layout

SCPS198C –SEPTEMBER 2014–REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TCA9534A Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Related Documentation

For related documentation see the following:

• I2C Bus Pull-Up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• IO Expander EVM User's Guide
• Choosing the Correct I2C Device for New Designs

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCA9534ADWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9534A TCA9534ADWR.A Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9534A TCA9534ADWR.B Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9534A TCA9534ADWT Active Production SOIC (DW) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9534A TCA9534ADWT.A Active Production SOIC (DW) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9534A TCA9534ADWT.B Active Production SOIC (DW) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TCA9534A TCA9534APWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 PW534A TCA9534APWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW534A TCA9534APWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW534A TCA9534APWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW534A TCA9534APWRG4.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW534A TCA9534APWRG4.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PW534A (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 7-Oct-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9534ADWR SOIC DW 16 2000 350.0 350.0 43.0 TCA9534APWR TSSOP PW 16 2000 353.0 353.0 32.0 TCA9534APWRG4 TSSOP PW 16 2000 353.0 353.0 32.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. SOIC - 2.65 mm max heightDW 16 SMALL OUTLINE INTEGRATED CIRCUIT7.5 x 10.3, 1.27 mm pitch 4224780/A

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

14X 1.27 16X 0.51 0.31 8.89 TYP0.33 0.10 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

(9.3) 14X (1.27) R0.05 TYP 16X (2) 16X (0.6) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN R0.05 TYP 16X (2) 16X (0.6) 14X (1.27) (9.3) 4220721/A 07/2016 SOIC - 2.65 mm max heightDW0016A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated