TCA9416

TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators datasheet (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SCPS238,A]
• PDF pages: 29

Technical content

TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators

1 Features

• 2-bit bidirectional translator for SDA and SCL lines in I2C applications
• Provides bidirectional voltage translation with no direction pin
• High-impedance output SCL_A, SDA_A, SCL_B, SDA_B pins when OE = 0 V or VCC = 0 V
• Internal 10-kΩ pull-up resistor on all SDA and SCL pins are enabled based on respective VCC voltage
• 1.08 V to 3.6 V on both A and B ports
• VCC Isolation feature: If either VCC input is at GND, both ports are in the high-impedance state (excluding pull-ups)
• No power-supply sequencing required: either VCCA or VCCB can be ramped first
• Low Ioff of 2.5 µA when either VCCA or VCCB = 0 V
• OE input can be tied directly to VCCA or controlled by GPIO
• Latch-up performance exceeds 100 mA per JESD 78, class II
• ESD Protection exceeds JESD 22 – 2500-V Human-body model (A114-B) – 1500-V Charged-device model (C101)

2 Applications

• Wearables
• Personal electronics
• Servers

3 Description

The TCA9416 is a 2-bit bidirectional I 2C and SMBus voltage-level translator with an output enable (OE) input and rising and falling edge accelerators. It is operational from 1.08 V to 3.6 V on both the A- side and B-side. This allows the device to interface between lower and higher logic signal levels at any of The OE input pin is referenced to V CCA, can be tied directly to V CCA, but it is also 3.6-V tolerant. The OE pin can also be controlled and set to a logic low to place all the SCL and SDA pins in a high-impedance state, which significantly reduces the quiescent current consumption. Under normal I 2C and SMBus configurations, the TCA9416 is compatible with standard speeds where the frequency of SCL is 100 kHz (Standard-mode), 400 kHz (Fast-mode), or 1 MHz (Fast-mode Plus). The TCA9416 features internal 10-kΩ pull-up resistors on SCL_A, SDA_A, SCL_B, and SDA_B. Additional external pull-up resistors can be added to the bus to reduce the total pull-up resistance and speed up rising edges. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TCA9416 X2SON (8) 1.35 mm × 0.80 mm SOT-23-T (8) 2.9 mm × 1.6 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. spacer Typical Application Block Diagram for TCA9416 TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.1 Receiving Notification of Documentation Updates..19

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (February 2021) to Revision A (August 2021) Page TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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5 Pin Configuration and Functions

1SCL_A 2VCCA 3SDA_A OE GND

5 SDA_B

6 VCCB

7 SCL_B

Figure 5-1. 8-PIN DTM, (Top View) 1SCL_A 8 SCL_B 2OE 7 VCCB 3VCCA 6 GND 4SDA_A 5 SDA_B Not to scale Figure 5-2. 8-PIN DDF, (Top View) Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME DTM DDF SCL_A 1 1 I/O Input/output A. Referenced to VCCA. VCCA 2 3 Power A-port supply voltage. 1.08 V ≤ VCCA ≤ 3.6 V SDA_A 3 4 I/O Input/output A. Referenced to VCCA. GND 4 6 GND Ground SDA_B 5 5 I/O Input/output B. Referenced to VCCB. VCCB 6 7 Power B-port supply voltage. 1.08 V ≤ VCCB ≤ 3.6 V SCL_B 7 8 I/O Input/output B. Referenced to VCCB. OE 8 2 Input Output enable (active High). Pull OE low to place all outputs in 3-state mode. Referenced to VCCA. www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCA9416

6 Specifications

6.1 Absolute Maximum Ratings

over recommended operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCA Supply voltage range –0.5 4 V VCCB Supply voltage range –0.5 4 V VI Input voltage range(1) A port –0.5 4 V B port –0.5 4 VO Voltage range applied to any output in the high-impedance or power-off state(1) A port –0.5 4 V B port –0.5 4 VO Voltage range applied to any output in the high or low state(1) (2) A port –0.5 4 V B port –0.5 4 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCCA, VCCB, or GND ±100 mA Tstg Storage temperature –65 150 °C (1) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (2) The value of VCCA and VCCB are provided in the recommended operating conditions table.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) A-Ports, B-Ports ±2500 V VCCA, VCCB, OE ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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6.3 Recommended Operating Conditions

over recommended operating free-air temperature range (unless otherwise noted) VCCA VCCB MIN MAX UNIT VCCA Supply voltage 1.08 3.6 V VCCB Supply voltage 1.08 3.6 V VI Input voltage A-port I/Os, B-port I/Os, OE 0 V to 3.6 V 0 V to 3.6 V 0 3.6 V VIH High-level VIL Low-level TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TCA9416 TCA9416 UNITDDF DTM

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 177.6 212.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 98.7 105.3 °C/W RθJB Junction-to-board thermal resistance 97.8 124.1 °C/W ψJT Junction-to-top characterization parameter 12.2 4.5 °C/W ψJB Junction-to-board characterization parameter 97.2 23.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCA9416

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT VUVLO_RIS E UVLO Rising Threshold VUVLO for VCCA and VCCB are independent 0 V to 3.6 V 0 V to 3.6 V 0.65 0.9 1 V VUVLO_FAL L UVLO Falling Threshold VUVLO for VCCA and VRTA (1) RTA(2) Activation Threshold 1.08 V to 3.6 V 1.08 V to 3.6 V VCCI × 0.30 VCCI × 0.45 V VFTA (1) FTA(2) Activation Threshold 1.08 V to 3.6 V 1.08 V to 3.6 V VCCI × 0.60 VCCI × 0.70 V Ioff A port VI = 3.6 V, VO = 0 V (TA ≤ 85 C) 0 V 0 V to 3.6 V ±0.1 ±0.5 μA B port VI = 3.6 V, VO = 0 V (TA ≤ 85 C) 0 to 3.6 V 0 V ±0.1 ±0.5 A port VI = 3.6 V, VO = 0 V (TA ≤ 125 C) 0 V 0 V to 3.6 V ±0.1 ±2.5 B port VI = 3.6 V, VO = 0 V (TA ≤ 125 C) 0 to 3.6 V 0 V ±0.1 ±2.5 ICC_OFF VCCA VI = VO = open, IO = 0, OE = 0 V 1.08 V to 3.6 V 1.08 V to 3.6 V 4 13 μA VCCB VI = VO = open, IO = 0, OE = 0 V 3 13 ICCA VI = VO = open, IO = 0, OE = VCCA 1.32 V 1.32 V to 3.6 V 3 6 μA 1.98 V 1.32 V to 3.6 V 4 10 3.6 V 1.32 V to 3.6 V 6 14 0 V 1.32 V to 3.6 V -0.5 0 1.32 V to 3.6 V 0 V 3 12 ICCB VI = VO = open, IO = 0, OE = VCCA 1.32 V to 3.6 V 1.32 V 1.5 6 μA 1.32 V to 3.6 V 1.98 V 2 8 1.32 V to 3.6 V 3.6 V 5 12 1.32 V to 3.6 V 0 V -0.5 0 0 V 1.32 V to 3.6 V 1 7 ICCA + ICCB VI = VO = open, IO = 0, OE = VCCA 1.32 V 1.32 V 4 12 μA1.98 V 1.98 V 6 15 3.6 V 3.6 V 11 23 Ron VI = 0.2 V, IO = 2 mA 1.08 V 1.08 V 28 50 Ω VI = 0.2 V, IO = 3 mA 1.65 V 1.65 V 15 25 VI = 0.2 V, IO = 6 mA 3.0 V 3.0 V 10 15 CI OE 3.3 V 3.3 V 2.5 4 pF Cio A or B port 0 V, 1.08 V, 3.6 V 0 V, 1.08 V, 3.6 V 7 10 pF (1) VCCI is the VCC associated with the input port. (2) RTA is "rise time accelerator" and FTA is "fall time accelerator" TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted). Typical specifications are at TA = 25 °C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRTA Time from VRTA to RTA disabling SDA,SCL = Hi-Z EN = VCC 80 210 ns www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCA9416

6.7 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPHL A B VCCA = 1.08 V 17 30 ns VCCA = 1.8 V 10 20 VCCA = 2.5 V 7 25 VCCA = 3.6 V 6 23 tPLH A B VCCA = 1.08 V 9 25 ns VCCA = 1.8 V 5 20 VCCA = 2.5 V 4 20 VCCA = 3.6 V 2 20 tPHL B A VCCB = 1.08 V 17 30 ns VCCB = 1.8 V 10 20 VCCB = 2.5 V 7 25 VCCB = 3.6 V 6 23 tPLH B A VCCB = 1.08 V 9 25 ns VCCB = 1.8 V 5 20 VCCB = 2.5 V 4 20 VCCB = 3.6 V 2 20 tSK(O)-RISE Rising Channel-to-channel skew (Propagation) 8 ns tSK(O)-FALL Falling Channel-to-channel skew (Propagation) 8 ns ten OE A or B 70 350 ns tdis OE A or B 60 160 ns trA B-port A-port VCCA = 1.08 V 18 35 ns VCCA = 1.8 V 12 30 VCCA = 2.5 V 11 25 VCCA = 3.6 V 10 25 trB A-port B-port VCCB = 1.08 V 18 35 ns VCCB = 1.8 V 12 30 VCCB = 2.5 V 11 25 VCCB = 3.6 V 10 25 tfA B-port A-port VCCA = 1.08 V 13 30 ns VCCA = 1.8 V 12 30 VCCA = 2.5 V 12 35 VCCA = 3.6 V 11 40 tfB A-port B-port VCCB = 1.08 V 13 30 ns VCCB = 1.8 V 12 30 VCCB = 2.5 V 12 35 VCCB = 3.6 V 11 40 TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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6.8 Typical Characteristics

Min(VCCA, VCCB) (V) RON (Ohms) -40 C 25 C 125 C The Min(VCCA, VCCB) signifies that the lower voltage of VCCA or VCCB is used. As an example, if VCCA = 1.8 V and VCCB = 3.3 V, then the Min(VCCA, VCCB) is 1.8 V. Figure 6-1. RON (Ω) vs Min(VCCA, VCCB) (V) VCCA (V) ICCA (µA) 1 1.5 2 2.5 3 3.5 4 -40 C 25 C 125 C Figure 6-2. ICCA (μA) vs VCCA (V) VCCB (V) ICCB (µA) 1 1.5 2 2.5 3 3.5 4 -40 C 25 C 125 C Figure 6-3. ICCB (μA) vs VCCB (V) www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCA9416

7 Parameter Measurement Information

CL = 57 pF (see Note C) GND PULSE GENERATOR DUT RT (see Note B) TEST CIRCUIT FOR OPEN-DRAIN OUTPUT R (see Note A) L VCC VCC VIN VOUT VCC Copyright © 2017, Texas Instruments Incorporated Figure 7-1. Load Circuit for Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement 1. RL = 1.35 kΩ 2. RT termination resistance should be equal to ZOUT of pulse generators. 3. CL includes probe and jig capacitance. CL = 50 pF when on the B-side. 4. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. 5. tPLZ and tPHZ are the same as tdis. 6. tPZL and tPZH are the same as ten. 7. VCCI is the VCC associated with the input port. 8. VCCO is the VCC associated with the output port. TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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7.1 Voltage Waveforms

0.9 × VCCOV / 2CCO tr 0.1 × VCCO tf Figure 7-2. Propagation Delay Times spacer Output Waveform 1 S1 at 2 × V (see Note 2) CCO VOH VOL OE input Output Waveform 2 S1 at GND (see Note 2) tPZL tPZH tPLZ tPHZ V / 2CCAV / 2CCA 0 V V / 2CCO V / 2CCO 0 V VCCA VOH V × 0.9CCO V × 0.1CCO 1. CL includes probe and jig capacitance. 2. Waveform 1 in Figure 7-3 is for an output with internal such that the output is high, except when OE is high (see Figure 7-1). Waveform 2 in Figure 7-3 is for an output with conditions such that the output is low, except when OE is high. 3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. 4. The outputs are measured one at a time, with one transition per measurement. 5. tPLZ and tPHZ are the same as tdis. 6. tPZL and tPZH are the same as ten. 7. tPLH and tPHL are the same as tpd. 8. VCCI is the VCC associated with the input port. 9. VCCO is the VCC associated with the output port. Figure 7-3. Enable and Disable Times www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCA9416

8 Detailed Description

8.1 Overview

The TCA9416 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A and B ports are able to accept I/O voltages ranging from 1.08 V to 3.6 V. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to improve the overall data rate. 10-k Ω pull up resistors, commonly used in open-drain applications, have been conveniently integrated so that an external resistor is not needed. When TCA9416 is disabled the one shots are also disabled, but the internal pull ups are still enabled. Pull up resistors are gated on the supply voltage. When supply is above UVLO, the pull up resistor for that specific side (A vs B) is enabled.

8.2 Functional Block Diagram

SDA_A SCL_A SDA_B SCL_B OE

8.3 Feature Description

8.3.1 Architecture

The TCA9416 architecture (see Figure 8-1) is an auto-direction-sensing based translator that does not require a direction-control signal to control the direction of data flow from A to B or from B to A. TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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Figure 8-1. Architecture of a TCA9416 Cell These two bidirectional channels support both directions of data flow without a direction-control signal. By properly biasing the gate of the pass-FET, the FET can turn on (low RDSON), when either side input voltage drops to ~ 1 voltage threshold below the lowest of the two supplies. The TCA9416 is part of the TI "Switch" type voltage translator family and employs key circuits to enable this voltage translation: 1. An N-channel pass-gate transistor topology that ties the A-port to the B-port. 2. Output rise time accelerator circuitry to detect and accelerate rising edges on the A or B ports 3. Output fall time accelerator circuitry to detect and accelerate falling edges on the A or B ports For bidirectional voltage translation, pull up resistors are included on the device for dc current sourcing capability. The V GATE gate bias of the N-channel pass transistor is set to the lower supply voltage and can be represented with MIN(VCCA, VCCB). The rise and fall time accelerator (RTA and FTA, respectively) circuitry speeds up the output slew rate by monitoring the input edge for transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the rise time accelerator (RTA) circuit turns on to increase the current drive capability of the driver. This edge-rate acceleration provides high ac drive by bypassing the internal 10-k Ω pull up resistors during the low-to-high transition to speed up the signal. The output resistance of the driver is decreased to approximately 150 Ω during this acceleration phase. During a high-to-low signal falling edge, the fall time accelerator (FTA) turns on to increase the current drive capability of the driver, similar to the rise time accelerator. This helps reduce the fall time for large capacitive loads. For light capacitive loads, the fall time accelerator will not enable. Both the rise and fall time accelerators have logic to control the rate at which they turn on and off, in order to reduce ringing and over/undershoots.

8.3.2 Enable and Disable

The TCA9416 has an OE input that is used to disable the device by setting OE low, which prevents any signals from propagating across the device. This pin is referenced to the VCCA supply. The rise and fall time accelerators are also disabled. Note that the internal pull up resistors will still be enabled if the supply is above V UVLO. The disable time (t dis) indicates the delay between the time when OE goes low and when the outputs are disabled (Hi-Z). The enable time (t en) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high. www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCA9416

8.3.3 Pull up resistors on I/O Lines

Each A-port I/O has an internal 10-k Ω pull up resistor to V CCA, and each B-port I/O has an internal 10-k Ω pull up resistor to V CCB. If a smaller value of pull up resistor is required, an external resistor must be added from the I/O to V CCA or V CCB (in parallel with the internal 10-k Ω resistors). However, adding lower value pull up resistors effects V OL levels. It is recommended not to go below 1.5-k Ω. The internal pull ups of the TCA9416 are controlled by their respective supplies. The resistors have back-biasing protection, so that if a supply is off, the current cannot flow through the resistors back into the supply. If a supply is above V UVLO_RISE, the pull up resistor for its side is enabled.

8.4 Device Functional Modes

The TCA9416 device has two functional modes, enabled and disabled. To disable the device set the OE input low, which disables the rise time and fall time accelerators, and prevents signals from propagating across the channels. The internal pull up resistors are not affected by the OE input. Setting the OE input high enables the device. TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TCA9416 can be used to bridge the digital-switching compatibility gap between two voltage nodes to successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point topology for interfacing devices or systems operating at different interface voltages with one another. The primary target application use is for interfacing with open-drain drivers on the data I/Os such as I 2C or SMBus, where the data is bidirectional and no control signal is available.

9.2 Typical Application

0.1 /g1F 3.3 V VCCA VCCB OE Optional Resistors Controller I2C Bus I2C Bus Devices 1.8 V VCCA VCCB SCL_A SCL_B OE Optional Resistors SDA_A SDA_B OE is referenced to VCCA Figure 9-1. Typical Application Circuit

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.08 to 3.6 V Output voltage range 1.08 to 3.6 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range – Use the supply voltage of the device that is driving the TCA9416 device to determine the input voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the value must be less than the VIL of the input port.
• Output voltage range – Use the supply voltage of the device that the TCA9416 device is driving to determine the output voltage range – The TCA9416 device has 10-kΩ internal pull up resistors. External pull up resistors can be added to reduce the total RC of a signal trace if necessary. www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCA9416

9.2.2.1 Startup Considerations with Large Capacitive Load Mismatches

Due to the FET based architecture of this translator, there are some considerations a system designer must be aware of during powering up with large differences in capacitance between the sides. If one supply with smaller capacitance is already powered up, and the other is ramping (with OE pin high), the side with the heavier load can ramp slower than the power supply ramp, due to only having an internal 10k Ω pull up resistor. In this situation, once the rising POR threshold is met, the device enables all circuitry. If the heavy capacitance side has not yet risen above about 70% of supply, the device determines this as low, and briefly turns on the fall time accelerators to propagate a low. Once the fall time accelerator has timed out, the signals rise and sit idle high. This phenomenon can be eliminated by holding the OE pin low (disabled) until all supplies and busses have ramped up, since this explicitly disables the bus acceleration circuitry until the bus has completed power up. Slower supply ramps also help reduce this since the bus voltage follows the supply closer if the ramp is slow.

9.2.3 Application Curve

Figure 9-2. Level-Translation of a 1-MHz Signal TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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10 Power Supply Recommendations

The TCA9416 has no supply restrictions outside of the 1.08 V to 3.6 V range. V CCA can be higher than or lower than VCCB. The internal circuitry will select the appropriate supply automatically to correctly support translation. VCCA can also be the same as VCCB, and the device can be used as a buffer. The sequencing of each power supply does not damage the device during the power up operation, so either power supply can be ramped up first. The output-enable (OE) input circuit is designed so that when the (OE) input is low, the outputs are disabled. No signals may propagate, and the rise time and fall time accelerators are disabled, but the internal pull up resistors will remain unaffected. To make sure the signals do not pass through during power up or power down, the OE input pin must be tied to GND through a pull down resistor and should not be enabled until VCCA and VCCB are fully ramped and stable. If OE is tied to VCCA, this is OK, but might result in a glitch on the bus during power up depending on the capacitive load and ramp rates. The minimum value of the pull down resistor to ground is determined by the current-sourcing capability of the driver. www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCA9416

11 Layout

11.1 Layout Guidelines

For reliability of the device, the following common printed-circuit board layout guidelines are recommended: 1. Bypass capacitors should be used on power supplies and should be placed as close as possible to the VCCA, VCCB pin, and GND pin. 2. Short trace lengths should be used to avoid excessive loading. 3. Keep SCL and SDA lengths close to prevent skewing the signals. 4. PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 30 ns. Making sure that any reflection encounters low impedance at the source driver.

11.2 Layout Example

SCL_A SDA_A VCCB GND SCL_B SDA_B TCA9416 CAP VCCA GND GND VCCB To MCU Figure 11-1. TCA9416 Layout Example (DDF) TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 www.ti.com

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TCA9416 SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCA9416

www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCA9416DDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2JGF TCA9416DDFR.A Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2JGF TCA9416DTMR Active Production X2SON (DTM) | 8 5000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 LC TCA9416DTMR.A Active Production X2SON (DTM) | 8 5000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 LC TCA9416DTMRG4.A Active Production X2SON (DTM) | 8 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 LC (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TCA9416DDFR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9416DDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TCA9416DTMR X2SON DTM 8 5000 189.0 185.0 36.0 TCA9416DTMR X2SON DTM 8 5000 205.0 200.0 33.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 6X 0.25 0.15 0.5

0.4 MAX

0.04 0.00 6X 0.27 0.17 0.54 2X 0.27 0.17 B 0.85 0.75 A 1.4 1.3 (0.102) TYP 4224755/B 10/2022 X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.05 C

0.1 C B A

0.05 C SYMM SYMM PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT ( 0.22) 4X (0.079)

0.0325 MIN

ALL AROUND0.0325 MAX ALL AROUND 6X (0.2) (0.5) (0.78) (R0.05) TYP 6X (0.42) (0.27) (45 ) TYP 4X (0.1) X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD 4224755/B 10/2022 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). NON SOLDER MASK DEFINED LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X SYMM SYMM SEE SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS SOLDER MASK OPENING METAL EDGE EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.411) 4X (0.42) 6X (0.2) (0.5) (0.78) PINS: 1,3,5,7 (0.27) (R0.05) TYP ( 0.22) (0.2) TYP 4X (0.079) (45 ) TYP 4X (0.128) X2SON - 0.4 mm max heightDTM0008A PLASTIC SMALL OUTLINE - NO LEAD 4224755/B 10/2022 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 40X EXPOSED METAL

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6)

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

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