Interface

TCA8418

Texas Instruments

I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

Manufacturer: Texas Instruments

Document: 37 Pages / 853Kb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse T parts

Online Datasheet

Read TCA8418 online.

TCA8418 I2C Controlled Keypad Scan IC With Integrated ESD Protection datasheet (Rev. G)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SCPS215,G]
PDF pages: 53

Technical content

(for example, Processor) INT ROW1 ROW2 ROW3 COL0 COL1 COL2 1 2 3 4 5 6 7 8 9 * 0 # Copyright © 2016, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TCA8418 SCPS215G – SEPTEMBER 2009– REVISED JUNE 2018 TCA8418I2CControlledKeypadScanICWithIntegratedESDProtection

1 Features

1• Operating Power-Supply Voltage Range of 1.65-V to 3.6-V

Supports 80 Buttons With Use of 18 GPIOs
Supports QWERTY Keypad Operation Plus GPIO Expansion
Low Standby (Idle) Current Consumption: 3 μA
Supports 1-MHz Fast Mode Plus I2C Bus
10 Byte FIFO to Store 10 Key Presses and Releases
Open-Drain Active-Low Interrupt Output
Integrated Debounce Time of 50 μs
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs: Typical Vhys at 1.8 V is 0.18 V
Latch-Up Performance Exceeds 200 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 on all 18 GPIO Pins and non GPIO pins – 2000-V Human Body Model (A114-A) – 1000-V Charged Device Model (C101)

2 Applications

Smart Phones
Tablets
HMI Panels
GPS Devices
MP3 Players
Digital Cameras

3 Description

The TCA8418 is a keypad scan device with integrated ESD protection. It can operate from 1.65 V to 3.6 V and has 18 general purpose inputs/outputs (GPIO) that can be used to support up to 80 keys via the I2C interface. The key controller debounces inputs and maintains a 10 byte FIFO of key-press and release events which can store up to 10 keys with overflow wrap capability. An interrupt (INT) output can be configured to alert key presses and releases either as they occur, or at maximum rate. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TCA8418 WQFN (24) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic Only 7 GPIOs are shown out of the full 18 GPIOs

12.1 Receiving Notification of Documentation Updates 45

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (July 2017) to Revision G Page

Added sentence: " If debouncing is enabled, these registers return..." to GPIO Data Status Registers, Changes from Revision E (November 2015) to Revision F Page
Changed the WQFN Body Size From: 4.00 mm × 3.00 mm To: 4.00 mm × 4.00 mm and deleted the DSBGA (25) Changes from Revision D (July 2014) to Revision E Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Supportt section, and Changes from Revision B (March 2010) to Revision C Page

24 INT7ROW1

23 SCL8ROW0

22 SDA9COL0

21 VCC 10COL1

20 RESET11COL2

19 GND12COL3

5 Pin Configuration and Functions

No. NAME 1 ROW7 I/O GPIO or row 7 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 2 ROW6 I/O GPIO or row 6 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 3 ROW5 I/O GPIO or row 5 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 4 ROW4 I/O GPIO or row 4 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 5 ROW3 I/O GPIO or row 3 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 6 ROW2 I/O GPIO or row 2 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 7 ROW1 I/O GPIO or row 1 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 8 ROW0 I/O GPIO or row 0 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 9 COL0 I/O GPIO or column 0 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 10 COL1 I/O GPIO or column 1 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 11 COL2 I/O GPIO or column 2 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 12 COL3 I/O GPIO or column 3 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 13 COL4 I/O GPIO or column 4 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 14 COL5 I/O GPIO or column 5 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 15 COL6 I/O GPIO or column 6 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 16 COL7 I/O GPIO or column 7 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 17 COL8 I/O GPIO or column 8 in keypad matrix. If unused, connect to VCC through a pull-up resistor. 18 COL9 I/O GPIO or column 9 in keypad matrix. If unused, connect to VCC through a pull-up resistor.

19 GND – Ground

20 RESET I Active-low reset input. Connect to VCC through a pull-up resistor, if no active connection is used. 21 VCC - Supply voltage of 1.65 V to 3.6 V 22 SDA I/O Serial data bus. Connect to VCC through a pull-up resistor. 23 SCL I Serial clock bus. Connect to VCC through a pull-up resistor. 24 INT O Active-low interrupt output. Open drain structure. Connect to VCC through a pull-up resistor.

SCPS215G – SEPTEMBER 2009– REVISED JUNE 2018 www.ti.com Product Folder Links: TCA8418 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 4.6 V VI Input voltage range(2) –0.5 4.6 V VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V Output voltage range in the high or low state(2) –0.5 4.6 IIK Input clamp current VI < 0 ±20 mA IOK Output clamp current VO < 0 ±20 mA IOL Continuous output Low current P port, SDA VO = 0 to VCC mAINT 25 IOH Continuous output High current P port VO = 0 to VCC 50 Tstg Storage temperature range –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000

6.3 Recommended Operating Conditions

VCC Supply voltage 1.65 3.6 V VIH High-level input voltage SCL, SDA, ROW0–7, COL0–9, RESET 0.7 × VCC 3.6 V VIL Low-level input voltage SCL, SDA, ROW0–7, COL0–9, RESET –0.5 0.3 × VCC V IOH High-level output current ROW0–7, COL0–9 10 mA IOL Low-level output current ROW0–7, COL0–9 25 mA TA Operating free-air temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TCA8418 UNITRTW (WQFN)

24 PINS

RθJA Junction-to-ambient thermal resistance 38.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.6 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.6 °C/W

www.ti.com SCPS215G – SEPTEMBER 2009– REVISED JUNE 2018 Product Folder Links: TCA8418 Submit Documentation FeedbackCopyright © 2009–2018, Texas Instruments Incorporated (1) Assumes that one GPIO is enabled.

6.5 Electrical Characteristics

over recommended operating free-air temperature range, VCC = 1.65 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIK Input diode clamp voltage II = –18 mA 1.65 V to 3.6 V –1.2 V VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.65 V to 3.6 V 1.03 1.43 V VPORF Power-on reset voltage, VCC falling 0.76 1.15 VOH ROW0–7, COL0–9 high-level output voltage IOH = –1 mA 1.65 V 1.25 V IOH = –8 mA 1.65 V 1.2 2.3 V 1.8 3 V 2.6 IOH = –10 mA 1.65 V 1.1 2.3 V 1.7 3 V 2.5 VOL ROW0–7, COL0–9 low-level output voltage IOL = 1 mA 1.65 V 0.4 V IOL = 8 mA 1.65 V 0.45 2.3 V 0.25 3 V 0.25 IOL = 10 mA 1.65 V 0.6 2.3 V 0.3 3 V 0.25 IOL SDA VOL = 0.4 V 1.65 V to 3.6 V 3 mA INT and CAD_INT VOL = 0.4 V 1.65 V to 3.6 V 3 II SCL, SDA, ROW0–7, COL0–9, RESET VI = VCCI or GND 1.65 V to 3.6 V 1 μA RINT Internal pull-up resistor value ROW0–7, COL0–9 105 kΩ ICC Supply current VI on SDA, ROW0–7, COL0–9 = VCC or GND, IO = 0, I/O = inputs, fSCL = 0 kHz Oscillator OFF 1.65 V to 3.6 V μA Oscillator ON 18 fSCL = 400 kHz 1 key press

1.65 V 50

3.6 V 90

fSCL = 1 MHz

1.65 V 65

3.6 V 153

fSCL = 400 kHz GPI low (pull- up enable)(1) 1.65 V to 3.6 V fSCL = 1 MHz 65 fSCL = 400 kHz GPI low (pull- up disable) fSCL = 1 MHz 24 fSCL = 400 kHz

1 GPO active

fSCL = 1 MHz 65 CI SCL VI = VCCI or GND 1.65 V to 3.6 V 6 8 pF Cio SDA VIO = VCC or GND 1.65 V to 3.6 V 10 12.5 pF ROW0–7, COL0–9 5 6

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16) STANDARD MODE I2C BUS FAST MODE I2C BUS FAST MODE PLUS (FM+) I2C BUS UNIT MIN MAX MIN MAX MIN MAX fscl I2C clock frequency 0 100 0 400 0 1000 kHz tsch I2C clock high time 4 0.6 0.26 μs tscl I2C clock low time 4.7 1.3 0.5 μs tsp I2C spike time 50 50 50 ns tsds I2C serial data setup time 250 100 50 ns tsdh I2C serial data hold time 0 0 0 ns ticr I2C input rise time 1000 20 + 0.1Cb (1) 300 120 ns ticf I2C input fall time 300 20 + 0.1Cb (1) 300 120 ns tocf I2C output fall time; 10 pF to 400 pF bus 300 20 + 0.1Cb (1) 300 120 μs tbuf I2C bus free time between Stop and Start 4.7 1.3 0.5 μs tsts I2C Start or repeater Start condition setup time 4.7 0.6 0.26 μs tsth I2C Start or repeater Start condition hold time 4 0.6 0.26 μs tsps I2C Stop condition setup time 4 0.6 0.26 μs tvd(data) Valid data time; SCL low to SDA output valid 1 0.9 0.45 μs tvd(ack) Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low 1 0.9 0.45 μs (1) The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the same clock signal, presumably free-running, with a nominal period of 50 μs. When an input changes state, the new state is clocked into the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock, it will take anywhere from zero to 50 μs after the input transition to clock the signal into the first stage. Therefore, the total debounce time may be as long as 100 μs. Finally, to account for a slow clock, the spec further guard-banded at 120 μs.

6.7 Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19) STANDARD MODE, FAST MODE, FAST MODE PLUS (FM+) I2C BUS UNIT MIN MAX tW Reset pulse duration 120(1) μs tREC Reset recovery time 120(1) μs tRESET Time to reset 120(1) μs

6.8 Switching Characteristics

STANDARD MODE, FAST MODE, FAST MODE PLUS (FM+) I2C BUS UNIT MIN MAX tIV Interrupt valid time Key event or Key unlock or Overflow ROW0–7, COL0–9 INT 20 60 μsGPI_INT with Debounce_DIS_Low 40 120 GPI_INT with Debounce_DIS_High 10 30 tIR Interrupt reset delay time SCL INT 200 ns tPV Output data valid SCL ROW0–7, COL0–9 400 ns tPS Input data setup time P port SCL 0 ns tPH Input data hold time P port SCL 300 ns

6.9 Keypad Switching Characteristics

STANDARD MODE, FAST MODE, FAST MODE PLUS (FM+) I2C BUS UNIT MIN MAX Key press to detection delay 25 μs Key release to detection delay 25 μs Keypad unlock timer 7 s Keypad interrupt mask timer 31 s Debounce 60 ms

6.10 Typical Characteristics

Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature Figure 3. Supply Current vs Supply Voltage Figure 4. I/O Sink Current vs Output Low Voltage Figure 5. I/O Sink Current vs Output Low Voltage Figure 6. I/O Sink Current vs Output Low Voltage

1 I 2C address

7 Parameter Measurement Information

A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 16. I2C Interface Load Circuit And Voltage Waveforms

0.7 V/c180 CC

0.3 V CC/c180

0.5 V CC/c180

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 17. Interrupt Load Circuit And Voltage Waveforms

2 V/c180 CC

0.7 V CC/c180

A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 18. P Port Load Circuit And Timing Waveforms

0.3 V´ CC

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 19. Reset Load Circuits And Voltage Waveforms

8 Detailed Description

8.1 Overview

monitoring the keypad array, and any configured general purpose inputs (GPIs).

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Key Events

8.3.1.1 Key Event Table

read on. The tables below show the values that correspond to both types of configurations. Table 1. Key Event Table (Keypad Array)

Table 2. Key Event Table (Row GPI Events) Table 3. Key Event Table (Column GPI Events)

8.3.1.2 General Purpose Input (GPI) Events

as a Key Event Interrupt caused by a Key press. it will add it to the event table. The press and release will still be indicated by bit 7 in the event register. counter and table when the keypad is locked.

8.3.1.3 Key Event (FIFO) Reading

Registers will also be part of the event FIFO. When the host wishes to read the FIFO, the following procedure is recommended.

Read the INT_STAT (0x02) register to determine what asserted the INT line. If GPI_INT or K_INT is set, then

a key event has occurred, and the event is stored in the FIFO.

Read the KEY_LCK_EC (0x03) register, bits [3:0] to see how many events are stored in FIFO.
Read the KEY_EVENT_A (0x04) register. Bit 7 value '0' signifies key release, value 1 signifies key press.
Repeat step 3 until either KEY_LCK_EC[3:0] = 0 or KEY_EVENT_A = 0. This signifies that the FIFO is
Reset the INT_STAT interrupt flag which was causing the interrupt by writing a 1 to the specific bit.

As an example, consider the following key presses. Table 4. Example Key Sequence Table 5. Example Key Sequence

10 N/A N/A N/A

CFG Register, then the INT output will be asserted low to let the processor know that an overflow has occurred. OVR_FLOW_M bit in the CFG Register. Please see the Overflow Errata section for more information about overflow behavior. Table 6. OVR_FLOW_M Bit

1 Enabled Overflow data shifts with last event pushing first event out

0 Disabled (Default) Overflow data is not stored and lost

Table 7. Key Event Overflow Handling

8.3.2 Keypad Lock/Unlock

user will need to press two specific keys before an keylock interrupt is generated or keypad events are recorded.

Determine which keys will be used for the unlock sequence. The key value from the Key Event Tables needs

to be entered into the UNLOCK1 and UNLOCK2 registers.

The UNLOCK1 to UNLOCK2 timer duration must be set by entering the desired seconds (valid range is 0 to

7 seconds) into bits [2:0] of the KP_LCK_TMR register.

If an interrupt mask is desired (see Keypad Lock Interrupt Mask Timer), then the desired interrupt mask

duration (valid range is 0 to 31 seconds) must be entered into bits [7:3] of the KP_LCK_TMR register.

When the host is ready to lock the keypad, a 1 is to be written to the K_LCK_EN bit (BIT6) in the

KEY_LCK_EC register. This will lock the keypad.

If the host wishes to manually unlock the keypad, writing a '0' to the K_LCK_EN bit (BIT6) in the

KEY_LCK_EC register will unlock the keypad.

Figure 20. Keypad Lock Flowchart

8.3.3 Keypad Lock Interrupt Mask Timer

this interrupt mask timer can also be used to limit the number of interrupts generated for a given amount of time. keypad is locked and the interrupt mask timer is set to a non-zero value, this will enable the interrupt mask timer. Figure 20.The procedure for an example is below.

Since the back light turns off after 10 seconds of no interrupts, the interrupt mask timer (

KP_LCK_TIMER[7:3] ) gets set to 10 seconds. Keypad is then locked.

When the first key press is detected, the TCA8418 sends an interrupt to the processor and starts a 10
If the correct unlock sequence is not entered within the 10 seconds, no interrupts are sent and the back
After the 10 second timer has expired, if another key press occurs while keypad is locked (regardless of

8.3.4 Control-Alt-Delete Support

The TCA8418 can support normal key presses, but it also can support a <Ctrl><Alt><Del> (CAD) key press. This feature allows the host to recognize a specific key press and alert the host that the combination has occurred. The TCA8418 will recognize a <Ctrl><Alt><Del> key press if keys 1, 11, and 21 are all pressed at the same time. These keys are referenced to the key values listed in the Key Event Table. Note that this key combination that triggers a CAD interrupt is not adjustable, and must be keys 1, 11, and 21. Please see CAD Interrupt Errata for more information.

8.3.5 Interrupt Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the input port register. The INT output has an open-drain structure and requires a pull-up resistor to VCC depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA8418, then the INT pin has to be connected to VCC. If not, the INT pin can be connected to VCC. 8.3.5.1 50 Micro-second Interrupt Configuration The TCA8418 provides the capability of deasserting the interrupt for 50 μs while there is a pending event. When the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already asserted results in a 50 μs deassertion. When the INT_CFG bit is cleared, INT remains asserted if the host tries to clear the interrupt. This feature is particularly useful for software development and edge triggering applications.

8.4 Device Functional Modes

8.4.1 Power-On Reset (POR)

When power (from 0 V) is applied to VCC, an internal power-on reset circuit holds the TCA8418 in a reset condition until VCC has reached VPORR. At that time, the reset condition is released, and the TCA8418 registers and I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below VPORF and back up to the operating voltage for a power-reset cycle. See Power Supply Recommendations for more information on power up reset requirements.

8.4.2 Powered (Key Scan Mode)

The TCA8418 can be used to read GPI from single buttons, or configured in key scan mode to read an array of keys. In key scan mode, there are two modes of operation.

8.4.2.1 Idle Key Scan Mode

Once the TCA8418 has had the keypad array configured, it will enter idle mode when no keys are being pressed. All columns configured as part of the keypad array will be driven low and all rows configured as part of the keypad array will be set to inputs, with pull-up resistors enabled. During idle mode, the internal oscillator is turned off so that power consumption is low as the device awaits a key press.

8.4.2.2 Active Key Scan Mode

When the TCA8418 is in idle key scan mode, the device awaits a key press. Once a key is pressed in the array, a low signal on one of the ROW pin inputs triggers an interrupt, which will turn on the internal oscillator and enter the active key scan mode. At this point, the TCA8418 will start the key scan algorithm to determine which key is being pressed, and/or it will use the internal oscillator for debouncing. Once all keys have been released, the device will enter idle key scan mode.

8.5 Programming

8.5.1 I2C Interface

registers where data is stored, written, or read.

If a master wants to send data to a slave:

– Master-transmitter sends a START condition and addresses the slave-receiver. – Master-transmitter sends data to slave-receiver. – Master-transmitter terminates the transfer with a STOP condition.

If a master wants to receive or read data from a slave:

– Master-receiver sends a START condition and addresses the slave-transmitter. – Master-receiver sends the requested register to read to slave-transmitter. – Master-receiver receives data from the slave-transmitter. – Master-receiver terminates the transfer with a STOP condition. Figure 21. Definition of Start and Stop Conditions

Figure 22. Bit Transfer

8.5.2 Bus Transactions

registers in the slave device. registers in order to instruct the slave device to perform a task. skipping the register number.

8.5.2.1 Writes

transmission with a STOP condition. Figure 23 shows an example of writing a single byte to a register.

1 A D7 D6 D5 D4 D3 D2 D1 D0 NA

8.5.2.2 Reads

become the master-receiver, and the slave will become the slave-transmitter. Figure 25 shows an example of reading a single byte from a slave register. Figure 25. Read from Register

8.6 Register Maps

8.6.1 Device Address

The address of the TCA8418 is shown in Table 8. Table 8. TCA8418 Device Addresses operation, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

information. All registers can be read and written to by the system master. Table 9 shows all the registers within this device and their descriptions. The default value in all registers is 0. Table 9. Register Descriptions

2 KLEC1 KLEC0

2 UK1_1 UK1_0

2 UK2_1 UK2_0

Table 9. Register Descriptions (continued)

0 C9DS C8DS

8.6.2.1 Configuration Register (Address 0x01)

Auto-increment for read and write operations; See below table for more information 0 = disabled 1 = enabled

6 GPI_E_CFG

GPI event mode configuration 0 = GPI events are tracked when keypad is locked 1 = GPI events are not tracked when keypad is locked

5 OVR_FLOW_M

0 = disabled; Overflow data is lost 1 = enabled; Overflow data shifts with last event pushing first event out

4 INT_CFG

0 = processor interrupt remains asserted (or low) if host tries to clear interrupt while there is still a pending key press, key release or GPI interrupt 1 = processor interrupt is deasserted for 50 μs and reassert with pending interrupts

3 OVR_FLOW_IEN

0 = disabled; INT is not asserted if the FIFO overflows 1 = enabled; INT becomes asserted if the FIFO overflows

2 K_LCK_IEN

Keypad lock interrupt enable 0 = disabled; INT is not asserted after a correct unlock key sequence 1 = enabled; INT becomes asserted after a correct unlock key sequence

1 GPI_IEN

GPI interrupt enable to host processor 0 = disabled; INT is not asserted for a change on a GPI 1 = enabled; INT becomes asserted for a change on a GPI

0 KE_IEN

Key events interrupt enable to host processor 0 = disabled; INT is not asserted when a key event occurs 1 = enabled; INT becomes asserted when a key event occurs Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the register defined by the command byte. If bit 7 is high, the value of the command byte is automatically incremented after each byte is written, and the next data byte is stored in the corresponding register. Registers are written in the sequence shown in Table 9. Once the GPIO_PULL3 register (0x2E) is written to, the command byte returns to register 0. Registers 0 and 2F are reserved and a command byte that references these registers is not acknowledged by the TCA8418. The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see Interrupt Status Register) bit is set.

8.6.2.2 Interrupt Status Register, INT_STAT (Address 0x02)

7 N/A Always 0

6 N/A Always 0

5 N/A Always 0

4 CAD_INT

CTRL-ALT-DEL key sequence status. Requires writing a 1 to clear interrupts. 0 = interrupt not detected 1 = interrupt detected

3 OVR_FLOW_INT

Overflow interrupt status. Requires writing a 1 to clear interrupts. 0 = interrupt not detected 1 = interrupt detected

2 K_LCK_INT

Keypad lock interrupt status. This is the interrupt to the processor when the keypad lock sequence is started. Requires writing a 1 to clear interrupts. 0 = interrupt not detected 1 = interrupt detected

1 GPI_INT

GPI interrupt status. Requires writing a 1 to clear interrupts. 0 = interrupt not detected 1 = interrupt detected Can be used to mask interrupts

0 K_INT

Key events interrupt status. Requires writing a 1 to clear interrupts. 0 = interrupt not detected 1 = interrupt detected (1) KEC[3:0] indicates how many key events are in the FIFO. For example, KEC[3:0] = 0b0000 = 0 events, KEC[3:0] = 0b0001 = 1 event and KEC[3:0] = 0b1010 = 10 events. As events happen (press or release), the count increases accordingly. The INT_STAT register is used to check which type of interrupt has been triggered. If the corresponding interrupt enable bits are set in the Configuration Register, then a value of 1 in the corresponding bit will assert the INT line low. An exception to this is the CAD_INT bit, which will assert the CAD_INT pin on YFP packages. A read to this register will return which types of events have occurred. Writing a 1 to the bit will clear the interrupt, unless there is still data which has set the Interrupt (unread keys in the FIFO).

8.6.2.3 Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)

6 K_LCK_EN

0 = disabled; Write a 0 to this bit to unlock the keypad manually 1 = enabled; Write a 1 to this bit to lock the keypad

5 LCK2

0 = unlock (if LCK1 is 0 too) 1 = locked (if LCK1 is 1 too)

4 LCK1

0 = unlock (if LCK2 is 0 too) 1 = locked (if LCK2 is 1 too)

3 KEC3(1) Key event count, Bit 3

2 KEC2 Key event count, Bit 2

1 KEC1 Key event count, Bit 1

0 KEC0 Key event count, Bit 0

8.6.2.4 Key Event Registers (FIFO), KEY_EVENT_A–J (Address 0x04–0x0D)

ADDRESS REGISTER NAME(1) REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x04 KEY_EVENT_A Key event register A KEA7 KEA6 KEA5 KEA4 KEA3 KEA2 KEA1 KEA0 These registers – KEY_EVENT_A-J – function as a FIFO stack which can store up to 10 key presses and releases. The user first checks the INT_STAT register to see if there are any interrupts. If so, then the Key Lock and Event Counter Register (KEY_LCK_EC, register 0x03) is read to see how many interrupts are stored. The INT_STAT register is then read again to ensure no new events have come in. The KEY_EVENT_A register is then read as many times as there are interrupts. Each time a read happens, the count in the KEY_LCK_EC register reduces by 1. The data in the FIFO also moves down the stack by 1 too (from KEY_EVENT_J to KEY_EVENT_A). Once all events have been read, the key event count is at 0 and then KE_INT bit can be cleared by writing a ‘1’to it. In the KEY_EVENT_A register, KEA[6:0] indicates the key # pressed or released. A value of 0 to 80 indicate which key has been pressed or released in a keypad matrix. Values of 97 to 114 are for GPI events. Bit 7 or KEA[7] indicate if a key press or key release has happened. A ‘0’means a key release happened. A ‘1’ means a key has been pressed (which can be cleared on a read). For example, 3 key presses and 3 key releases are stored as 6 words in the FIFO. As each word is read, the user knows if it is a key press or key release that occurred. Key presses such as CTRL+ALT+DEL are stored as 3 simultaneous key presses. Key presses and releases generate key event interrupts. The KE_INT bit and /INT pin will not cleared until the FIFO is cleared of all events. All registers can be read but for the purpose of the FIFO, the user should only read KEY_EVENT_A register. Once all the events in the FIFO have been read, reading of KEY_EVENT_A register will yield a zero value.

8.6.2.5 Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0x0E)

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x0E KP_LCK_TIMER Keypad lock interrupt mask timer and lock 1 to lock 2 timer KL7 KL6 KL5 KL4 KL3 KL2 KL1 KL0 KL[2:0] are for the Lock1 to Lock2 timer KL[7:3] are for the interrupt mask timer Lock1 to Lock2 timer must be non-zero for keylock to be enabled. The lock1 to lock2 bits ( KL[2:0] ) define the time in seconds the user has to press unlock key 2 after unlock key 1 before the key lock sequence times out. For more information, please see Keypad Lock/Unlock. If the keypad lock interrupt mask timer is non-zero, a key event interrupt (K_INT) will be generated on any first key press. The second interrupt (K_LCK_IN) will only be generated when the correct unlock sequence has been completed. If either timer expires, the keylock state machine will reset. When the interrupt mask timer is disabled (‘0’), a key lock interrupt will trigger only when the correct unlock sequence is completed. The interrupt mask timer should be set for the time it takes for the LCD to dim or turn off. For more information, please see Keypad Lock Interrupt Mask Timer.

8.6.2.6 Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address 0x0F-0x10)

ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x0F Unlock1 Unlock key 1 UK1_7 UK1_6 UK1_5 UK1_4 UK1_3 UK1_2 UK1_1 UK1_0 0x10 Unlock2 Unlock key 2 UK2_7 UK2_6 UK2_5 UK2_4 UK2_3 UK2_2 UK2_1 UK2_0 UK1[6:0] contains the key number used to unlock key 1 UK2[6:0] contains the key number used to unlock key 2 A ‘0’in either register disables the keylock function.

8.6.2.7 GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0x11–0x13)

These registers are used to check GPIO interrupt status. If the GPI_INT bit is set in INT_STAT register, then the GPI which set the interrupt is marked with a 1 in the corresponding table. To clear the GPI_INT bit, these registers must all be 0x00. A read to the register clears the bit. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x11 GPIO_INT_STAT1 GPIO Interrupt Status 1 R7IS R6IS R5IS R4IS R3IS R2IS R1IS R0IS 0x12 GPIO_INT_STAT2 GPIO Interrupt Status 2 C7IS C6IS C5IS C4IS C3IS C2IS C1IS C0IS 0x13 GPIO_INT_STAT3 GPIO Interrupt Status 3 N/A N/A N/A N/A N/A N/A C9IS C8IS

8.6.2.8 GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0x14–0x16)

These registers show the GPIO state when read for inputs and outputs. Read these twice to clear them. If debouncing is enabled, these registers return their default values until a change of state occurs at an input. Initial pin states can be read by disabling debouncing. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x14 GPIO_DAT_STAT1 GPIO Data Status 1 R7DS R6DS R5DS R4DS R3DS R2DS R1DS R0DS 0x15 GPIO_DAT_STAT2 GPIO Data Status 2 C7DS C6DS C5DS C4DS C3DS C2DS C1DS C0DS 0x16 GPIO_DAT_STAT3 GPIO Data Status 3 N/A N/A N/A N/A N/A N/A C9DS C8DS

8.6.2.9 GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0x17–0x19)

These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This sets the output for the corresponding GPIO output. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x17 GPIO_DAT_OUT1 GPIO Data Out 1 R7DO R6DO R5DO R4DO R3DO R2DO R1DO R0DO 0x18 GPIO_DAT_OUT2 GPIO Data Out 2 C7DO C6DO C5DO C4DO C3DO C2DO C1DO C0DO 0x19 GPIO_DAT_OUT3 GPIO Data Out 3 N/A N/A N/A N/A N/A N/A C9DO C8DO

8.6.2.10 GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0x1A–0x1C)

These registers enable interrupts (bit value 1) or disable interrupts (bit value '0') for general purpose inputs (GPI) only. If the input changes on a pin which is setup as a GPI, then the GPI_INT bit will be set in the INT_STAT register. A bit value of '0' in any of the unreserved bits disables the corresponding pin's ability to generate an interrupt when the state of the input changes. This is the default value. A bit value of 1 in any of the unreserved bits enables the corresponding pin's ability to generate an interrupt when the state of the input changes. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x1A GPIO_INT_EN1 GPIO Interrupt Enable 1 R7IE R6IE R5IE R4IE R3IE R2IE R1IE R0IE 0x1B GPIO_INT_EN2 GPIO Interrupt Enable 2 C7IE C6IE C5IE C4IE C3IE C2IE C1IE C0IE 0x1C GPIO_INT_EN3 GPIO Interrupt Enable 3 N/A N/A N/A N/A N/A N/A C9IE C8IE

8.6.2.11 Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0x1D–0x1F)

A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A pin in GPIO mode can be configured as an input or an output in the GPIO_DIR1-3 registers. This is the default value. A 1 in any of these bits puts the pin in key scan mode and becomes part of the keypad array, then it is configured as a row or column accordingly (this is not adjustable). ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x1D KP_GPIO1 Keypad/GPIO Select 1 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 0x1E KP_GPIO2 Keypad/GPIO Select 2 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 0x1F KP_GPIO3 Keypad/GPIO Select 3 N/A N/A N/A N/A N/A N/A COL9 COL8

8.6.2.12 GPI Event Mode Registers, GPI_EM1–3 (Address 0x20–0x22)

A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. This is the default value. A 1 in any of these bits means it is part of the event FIFO. When a pin is setup as a GPI and has a value of 1 in the Event Mode register, then any key presses will be added to the FIFO. Please see Key Event Table for more information. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x20 GPI_EM1 GPI Event Mode Select 1 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 0x21 GPI_EM2 GPI Event Mode Select 2 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 0x23 GPI_EM3 GPI Event Mode Select 3 N/A N/A N/A N/A N/A N/A COL9 COL8

8.6.2.13 GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0x23–0x25)

A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. This is the default value. A 1 in any of these bits sets the pin as an output. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x23 GPIO_DIR1 GPIO Direction 1 R7DD R6DD R5DD R4DD R3DD R2DD R1DD R0DD 0x24 GPIO_DIR2 GPIO Direction 2 C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD 0x25 GPIO_DIR3 GPIO Direction 3 N/A N/A N/A N/A N/A N/A C9DD C8DD

V H T IALID IGH RIGGER NTERRUPT 50 s/c109 V LOW T IALID RIGGER NTERRUPT 50 s/c109 D DISABLEDEBOUNCE GPI with INT INT V H T IALID IGH RIGGER NTERRUPT V LOW T IALID RIGGER NTERRUPT TCA8418 www.ti.com SCPS215G – SEPTEMBER 2009– REVISED JUNE 2018 Product Folder Links: TCA8418 Submit Documentation FeedbackCopyright © 2009–2018, Texas Instruments Incorporated

8.6.2.14 GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0x26–0x28)

A bit value of '0' indicates that interrupt will be triggered on a high-to-low/low-level transition for the inputs in GPIO mode. This is the default value. A bit value of 1 indicates that interrupt will be triggered on a low-to-high/high-level value for the inputs in GPIO mode. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x26 GPIO_INT_LVL1 GPIO Edge/Level Detect 1 R7IL R6IL R5IL R4IL R3IL R2IL R1IL R0IL 0x27 GPIO_INT_LVL2 GPIO Edge/Level Detect 2 C7IL C6IL C5IL C4IL C3IL C2IL C1IL C0IL 0x28 GPIO_INT_LVL3 GPIO Edge/Level Detect 3 N/A N/A N/A N/A N/A N/A C9IL C8IL

8.6.2.15 Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0x29–0x2B)

This is for pins configured as inputs. A bit value of ‘0’in any of the unreserved bits enables the debounce. This is the default value A bit value of ‘1’disables the debounce. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x29 DEBOUNCE_DIS1 Debounce Disable 1 R7DD R6DD R5DD R4DD R3DD R2DD R1DD R0DD 0x30 DEBOUNCE_DIS2 Debounce Disable 2 C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD 0x2B DEBOUNCE_DIS3 Debounce Disable 3 N/A N/A N/A N/A N/A N/A C9DD C8DD Debounce disable will have the same effect for GPI mode or for rows in keypad scanning mode. The RESET input always has a 50-μs debounce time. The debounce time for inputs is the time required for the input to be stable to be noticed. This time is 50 μs. The debounce time for the keypad is for the columns only. The minimum time is 25 ms. All columns are scanned once every 25 ms to detect any key presses. Two full scans are required to see if any keys were pressed. If the first scan is done just after a key press, it takes 25 ms to detect the key press. If the first scan is down much later than the key press, it will take 40 ms to detect a key press.

8.6.2.16 GPIO pull-up Disable Register, GPIO_PULL1–3 (Address 0x2C–0x2E)

This register enables or disables pull-up registers from inputs. A bit value of '0' will enable the internal pull-up resistors. This is the default value. A bit value of 1 will disable the internal pull-up resistors. ADDRESS REGISTER NAME REGISTER DESCRIPTION BIT 7 6 5 4 3 2 1 0 0x2C GPIO_PULL1 GPIO pull-up Disable 1 R7PD R6PD R5P D R4PD R3PD R2P D R1PD R0P D 0x3D GPIO_PULL2 GPIO pull-up Disable 2 C7PD C6PD C5P D C4PD C3PD C2P D C1PD C0P D 0x2E GPIO_PULL3 GPIO pull-up Disable 3 N/A N/A N/A N/A N/A N/A C9PD C8P D

8.6.3 CAD Interrupt Errata

8.6.3.1 Description

sequence. Certain key press sequences trigger this bit to register a CAD_INT improperly. Table 10. Interrupt Status Register, INT_STAT (Address 0x02) CTRL-ALT-DEL key sequence status. Requires writing a 1 to clear interrupts. Overflow interrupt status. Requires writing a 1 to clear interrupts. lock sequence is started. Requires writing a 1 to clear interrupts. GPI interrupt status. Requires writing a 1 to clear interrupts. Key events interrupt status. Requires writing a 1 to clear interrupts.

1 + 11
1 + 21
21 + 1 + 11

8.6.3.2 System Impact

8.6.3.3 System Workaround

8.6.4 Overflow Errata

8.6.4.1 Description

high, no overflow interrupt is generated. Table 11. Configuration Register (Address 0x01)

6 CPI_E_CFG

Overflow data shifts with last event pushing first event out interrupt configuration.

8.6.4.2 System Impact

Enabling the Overflow improperly may lead to data loss.

8.6.4.3 System Workaround

that stack has begun to overflow, meaning data is already being lost.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Ghosting Considerations

positions to avoid ghosting (or appearing like a 4th key has been pressed). To avoid ghosting, it is best to keep 3-button combinations that are pressed on separate rows and columns. Consider the situation with the keypad described in Figure 26. Figure 26. Example Keypad of the ROWs are configured as inputs with pullup resistors. The COLs are configured as outputs, driving low. column, the TCA8418 will read the ROW inputs, to determine which keys on a column are being pressed. being pressed) are being pressed.

9.2 Typical Application

layout is used. This number pad has keys for numbers 0 to 9, *, and #. Figure 29. Typical Application

9.2.1 Design Requirements

The system designer needs to know a few key pieces in order to design their system for the TCA8418.

The number of keys desired
Whether the keys will be multiplexed or not
The layout of the multiplexed keys
Unused keys be tied to VCC through a pullup resistor (10 kΩ)

9.2.2 Detailed Design Procedure

9.2.2.1 Designing the Hardware Layout

example, we will not assume any of the other pins will be used.

All keys in the keypad array to be added to the FIFO upon a key press
Attempting to clear the interrupt before the proper registers have been cleared to de-assert the INT pin for 50 μs, then assert the INT pin.
No additional pins are being used, other than the keypad array
Keypad lock support, requiring that the unlock combination be ‘#, 1’which must be pressed within 2 seconds of each other
Keypad lock interrupt mask timer of 10 seconds to match the back light auto-turn off with 10 seconds of no interrupt
Hardware debouncing to be enabled

Figure 30. Example Keypad the TCA8418 values for the key locations. According to the key event table, the key presses are assigned in Table 12. Table 12. Key Press Assignment

that no external pullup resistors are needed, because the TCA8418 has integrated pullup resistors. Figure 31. Keypad Schematic

9.2.2.2 Configuring the Registers

The next step to design a keypad array for the TCA8418 is to configure the appropriate hardware registers.

9.2.3 Application Curves

Figure 32. Initial Key Press to Interrupt Output Figure 33. Zoom On Second Scan

10 Power Supply Recommendations

reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 34 and Figure 35. Figure 34. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC Figure 35. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 13 specifies the performance of the power-on reset feature for TCA8418 for both types of power-on reset. Table 13. Recommended Supply Sequencing and Ramp Rates(1)

11 Layout

11.1 Layout Guidelines

not a concern for I2C signal speeds. capacitors should be placed as close to the TCA8418 as possible. the complexity of the layout.

11.2 Layout Example

Figure 38. RTW Package Layout Example

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCA8418RTWR Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PZ418 TCA8418RTWR.A Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PZ418 TCA8418RTWRG4 Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PZ418 TCA8418RTWRG4.A Active Production WQFN (RTW) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PZ418 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA8418RTWR WQFN RTW 24 3000 356.0 356.0 36.0 TCA8418RTWRG4 WQFN RTW 24 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTW 24 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.5 mm pitch 4224801/A

4219135/B 11/2016www.ti.com WQFN - 0.8 mm max heightPLASTIC QUAD FLATPACK-NO LEADRTW0024B A 0.08C0.1CAB0.05C B SYMMSYMM

NOTES: (continued)3.For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). EXAMPLE BOARD LAYOUT 4219135/B 11/2016www.ti.com WQFN - 0.8 mm max heightRTW0024B PLASTIC QUAD FLATPACK-NO LEADSYMMSYMM LAND PATTERN EXAMPLESCALE: 20X

NOTES: (continued)4.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations. EXAMPLE STENCIL DESIGN 4219135/B 11/2016www.ti.com WQFN - 0.8 mm max heightRTW0024B PLASTIC QUAD FLATPACK-NO LEADSYMMSYMMSOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILEXPOSED PAD 25:78% PRINTED COVERAGE BY AREA UNDER PACKAGESCALE: 20X METALTYP

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025

Product Information

TCA8418 specifications and overview.

Summary

I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

Description

I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

Source title TCA8418 Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer