TCA7408

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A B C D 1 2 3 4 TCA7408 www.ti.com SCPS235 –NOVEMBER 2011 Low-Voltage8-BitI2C andSMBusI/OExpanderwithInterruptOutput,RESET,I/O DirectionRegisters,andProgrammablePull-up/Pull-down Check forSamples: TCA7408 1FEATURES • Programmable Edge DetectionforGenerating Interrupts• OperatingPower-Supply VoltageRange of

InterruptLatching1.65Vto3.6V
SoftwareReset• Allows BidirectionalVoltage-LevelTranslation and GPIO Expansion Between: • Input/OutputDirectionRegister – 1.8VSCL/SDA and 1.8V,2.5V,3.3VGPIO • Power Up With AllChannels Configuredas port Inputs – 2.5VSCL/SDA and 1.8V,2.5V,3.3VGPIO • No GlitchOn Power Up port • Latched Outputs With High-CurrentDrive – 3.3VSCL/SDA and 1.8V,2.5V,3.3VGPIO Maximum CapabilityforDirectlyDrivingLEDs port • Latch-Up Performance Exceeds 100 mA Per – 5V SCL/SDA and 1.8V,2.5V,3.3VGPIO port JESD 78,Class II
Standby CurrentConsumption of<2 µA at1.8V • ESD ProtectionExceeds JESD 22
ActiveCurrentConsumption of: – 2000-V Human-Body Model (A114-A) – <2 µA at1.8V100 kHz clock – 1000-V Charged-DeviceModel (C101) – <5 µA at1.8V400 kHz clock ZSZ PACKAGE
100-kHz,400-kHz FastMode (TOP THROUGH VIEW)
InternalPower-On-Reset and Watchdog Timer
FailsafeI2C, INT,and RESET lines
Noise Filteron SCL/SDA and Inputs
Schmitt-TriggerActionAllows Slow Input Transitionand BetterSwitchingNoise Immunity attheSCL and SDA Inputs – Vhys = 0.18VTyp at1.8V – Vhys = 0.25VTyp at2.5V 1 2 3 4– Vhys = 0.33VTyp at3.3V A GND GPIO7 GPIO6 GPIO5• Active-LowReset (RESET) Input B VCCI VCCP ADDR GPIO4
Open-Drain Active-LowInterrupt(INT)Output C SDA INT RESET GPIO3
Automatic power save mode D SCL GPIO0 GPIO1 GPIO2
Programmable Pull-up/Pull-downResistorsfor GPIO Inputs

DESCRIPTION

This8-bitI/Oexpanderforthetwo-linebidirectionalbus (I2C) isdesignedtoprovidegeneral-purposeremoteI/O expansionviatheI2C interface[serialclock(SCL)and serialdata(SDA)]. The majorbenefitofthisdeviceisitswide VCC range.Itcan operatefrom1.65V to3.6V on theGPIO-portside and 1.65V to 5.5V on the SDA/SCL side.This allows the TCA7408 to interfacewith next-generation microprocessorsand microcontrollerson theSDA/SCL side,where supplylevelsaredroppingdown toconserve power. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SCPS235 –NOVEMBER 2011 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. DESCRIPTION (CONTINUED) The bidirectionalvoltage-leveltranslationintheTCA7408 isprovidedthroughVCCI.VCCI shouldbe connectedto theVCC oftheexternalSCL/SDA lines.ThisindicatestheVCC leveloftheI2C bus totheTCA7408. The voltage levelon theGPIO-portoftheTCA7408 isdeterminedby VCCP . At power on,theI/Osareconfiguredas inputs.However,thesystem mastercan enabletheI/Osas eitherinputs oroutputsby writingtotheI/Odirectionbits.The dataforeach inputoroutputiskeptinthecorrespondingInput orOutputRegister.Allregisterscan be readby thesystemmaster. The system mastercan resettheTCA7408 intheeventofa timeoutorotherimproperoperationby assertinga low inthe RESET input.The power-on reset(POR) putsthe registersintheirdefaultstateand initializesthe I2C/SMBus statemachine.The RESET pincauses thesame reset/initializationtooccurwithoutdepoweringthe part.The system master can alsoexecutea softwareresetby assertingB0 in register01h. The POR, and hardwarereseteventswillresetthestatemachine and theregisterstothedefaultstate.A softwareresetwill onlyresettheregisterstothedefaultstateand willnotresetthestatemachine.Inadditionthewatch dog timer onlyresetsthestatemachine The TCA7408 open-draininterrupt(INT)outputisactivatedwhen any GPIO setas an inputhas a transitionto thestateoppositeofthatintheInputDefaultState(09h)registerand thecorrespondingbitintheInterruptMask Register(11h) is set to 0. Itis used to indicateto the system master thatan inputhas changed to a pre-determinedstate.INT isalsoactivatedaftereithera hardwareresetorsoftwarereset.Watch dog timerdoes notactivatetheINT pin. INT can be connectedtotheinterruptinputofa microcontroller.By sendingan interruptsignalon thisline,the remoteI/Ocan informthemicrocontrollerifthereisincomingdataon itsportswithouthavingtocommunicate via theI2C bus.Thus,theTCA7408 can remaina simpleslavedevice. One hardwarepin(ADDR) can be used toprogram theI2C addressand allowup totwo devicestosharethe same I2C bus orSMBus. The integratedwatchdog timerwillresettheI2C statemachine intheeventtheSDA isinternallyheldlow,after 200 ms (nominal).Thisresetdoes notresettheregistersas theyretaintheirpreviousvalue. ORDERING INFORMATION (1) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to85°C µCSP – ZSZ package Tape and reel TCA7408ZSZR ZUQ (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging.

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www.ti.com SCPS235 –NOVEMBER 2011 DEVICE INFORMATION TOP THROUGH VIEW 1 2 3 4 A GND GPIO7 GPIO6 GPIO5 B VCCI VCCP ADDR GPIO4 C SDA INT RESET GPIO3 D SCL GPIO0 GPIO1 GPIO2 PIN FUNCTIONS µCSP (ZSZ) PIN NO. NAME B1 VCCI SupplyvoltageofI2C bus.ConnectdirectlytotheVCCI oftheexternalI2C master.Providesvoltagelevel translation. B3 ADDR Addressinput.ConnectdirectlytoVCCI orground. C3 RESET Active-lowresetinput.ConnecttoVCCI througha pull-upresistor,ifno activeconnectionisused. D2 GPIO0 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO0 isconfiguredas an input. D3 GPIO1 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO1 isconfiguredas an input. D4 GPIO2 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO2 isconfiguredas an input. C4 GPIO3 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO3 isconfiguredas an input. A1 GND Ground B4 GPIO4 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO4 isconfiguredas an input. A4 GPIO5 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO5 isconfiguredas an input. A3 GPIO6 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO6 isconfiguredas an input. A2 GPIO7 GPIO-portinput/output(push-pulldesignstructure).Atpower on,GPIO7 isconfiguredas an input. C2 INT Active-lowinterruptoutput.ConnecttoVCCI througha pull-upresistor. D1 SCL Serialclockbus.ConnecttoVCCI througha pull-upresistor. C1 SDA Serialdatabus.ConnecttoVCCI througha pull-upresistor. B2 VCCP SupplyvoltageofTCA7408 forGPIO-port VOLTAGE TRANSLATION VCCI VCCP (SCL AND SDA OF I2C MASTER) (GPIO-PORT) (V) (V) 1.8 1.8 1.8 2.5 1.8 3.3 2.5 1.8 2.5 2.5 2.5 3.3 3.3 1.8 3.3 2.5 3.3 3.3 5 1.8 5 2.5 5 3.3 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TCA7408

Shift Reg. Write PD/PU PDZ / PU Register D Q OFF QZ PD/PU Data PULL ENAB Register Data From Shift Reg. Write PULL ENAB D Q OFF QZ PULL ENAB Data Data From Shift Reg. Write OUT STATE OUT STATE Register OUT STATE Data D Q OFF QZ Write OUT HIGHZ Data From Shift Reg. OUT HIGHZ DataD Q OFF QZ OUT HIGHZ Register IO DIR. Register Data From Shift Reg. IO DIR Data Write IO DIRECTION D Q OFF QZ IN DEFAULT Register Data From Shift Reg. Write INPUT DEFAULT D Q OFF QZ INPUT DEF STATE Data INPUT STATUS Data D Q OFF QZ Data From Shift Reg. Write INT MASK INT MASK Register INT STAT Register D Q OFF QZ INTERUPT STATUS Data VDD ESD Protection Diode R1 100k GPIO 100kR2 ESD Protection Diode GND INT MASK Data To INTz (One of ANDed 8) TCA7408 SCPS235 –NOVEMBER 2011 www.ti.com SIMPLIFIED LOGIC DIAGRAM (POSITIVE LOGIC) On power up orreset,allregistersreturntodefaultvalues. I/Oport When an I/Oisconfiguredas an input,FETs Q1 and Q2 areoff,whichcreatesa high-impedanceinput. IftheI/Oisconfiguredas an output,Q1 orQ2 isenableddependingon thestateoftheOutputPortRegister.In thiscase,thereare low impedance pathsbetween the I/Opinand eitherVCCP or GND. The externalvoltage appliedtothisI/Opinshouldnotexceed therecommended levelsforproperoperation. Q4 isturnedon at power-on to enable the pulldown resistor.Q3 and Q4 are enabled accordinglyto the Pull-up/-downSelectRegisterand thePull-up/-downEnableRegister. When theGPIO-portissetas an outputtheinputbuffersaredisabledsuch thatthebus isallowedtofloat. I2C INTERFACE The bidirectionalI2C bus consistsof the serialclock(SCL) and serialdata (SDA) lines.Both linesmust be connectedtoVCCI througha pull-upresistorwhen connectedtotheoutputstagesofa device.Data transfermay be initiatedonlywhen thebus isnotbusy. I2C communicationwiththisdeviceisinitiatedby a mastersendinga Startcondition,a high-to-lowtransitionon theSDA input/output,whiletheSCL inputishigh.AftertheStartcondition,thedeviceaddressbyteissent,most significantbit(MSB) first,includingthedatadirectionbit(R/W). Afterreceivingthe validaddress byte,thisdeviceresponds withan acknowledge (ACK), a low on the SDA input/outputduringthehighoftheACK-relatedclockpulse.The address(ADDR) inputoftheslavedevicemust notbe changed between theStartand theStopconditions. On theI2C bus,onlyone databitistransferredduringeach clockpulse.The dataon theSDA linemust remain stableduringthehighpulseoftheclockperiod,as changes inthedatalineatthistimeareinterpretedas control commands (StartorStop).

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Start Condition Stop Condition SDA SCL Data Line Change Data Output by Transmitter Data Output by Receiver SCL From Master NACK ACK Start Condition Clock Pulse for Acknowledgment TCA7408 www.ti.com SCPS235 –NOVEMBER 2011 A Stop condition,a low-to-hightransitionon the SDA input/outputwhilethe SCL inputishigh,issentby the master. Any number of data bytescan be transferredfrom the transmitterto receiverbetween the Startand the Stop conditions.Each byteofeightbitsisfollowedby one ACK bit.The transmittermust releasetheSDA linebefore thereceivercan send an ACK bit.The devicethatacknowledgesmust pulldown theSDA lineduringtheACK clockpulse,so thattheSDA lineisstablelow duringthehighpulseoftheACK-relatedclockperiod.When a slavereceiverisaddressed,itmust generatean ACK aftereach byteisreceived.Similarly,the master must generatean ACK aftereach bytethatitreceivesfromtheslavetransmitter.Setup and holdtimesmust be met to ensureproperoperation. A masterreceiversignalsan end ofdatatotheslavetransmitterby notgeneratingan acknowledge(NACK) after thelastbytehas been clockedoutoftheslave.Thisisdone by themasterreceiverby holdingtheSDA linehigh. Inthisevent,thetransmittermust releasethedatalinetoenablethemastertogeneratea Stopcondition. Figure1. DefinitionofStartand Stop Conditions Figure2. BitTransfer Figure3. Acknowledgment on I2C Bus Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TCA7408

1000 0001, 0x02, 0x02, 0x02, … Command byte: B7 = 1 enables auto -increment mode B6 = 0 B5 = 0 B4-B0 = 0 0001 points to Device ID and Control register Data byte write to Device ID and Control Register Data byte write to I/O Direction Register Data byte write to Output State Register TCA7408 SCPS235 –NOVEMBER 2011 www.ti.com DEVICE ADDRESS The addressofthedeviceisshown below ADDRESS REFERENCE SLAVE ADDRESS ADDR I2C BUS SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 0 1 1 0 (W) 134 (decimal),86(h) 0 1 0 0 0 0 1 1 1 (R) 135 (decimal),87(h) 1 1 0 0 0 1 0 0 0 (W) 136 (decimal),88(h) 1 1 0 0 0 1 0 0 1 (R) 137 (decimal),89(h) The lastbitoftheslaveaddressdefinestheoperation(readorwrite)tobe performed.A high(1)selectsa read operation,whilea low(0)selectsa writeoperation. CONTROL REGISTER AND COMMAND BYTE Followingthesuccessfulacknowledgementoftheaddressbyte,thebus mastersends a command byte,whichis storedintheControlRegisterintheTCA7408. Fivebitsofthisdatabytestatetheoperation(readorwrite)and theinternalregistersthatwillbe affected.Thisregistercan be writtenorreadthroughtheI2C bus.The command byteissentonlyduringa writetransmission. AUTO INCREMENT MODE An automaticincrementfeatureas been added tothecontrolregisterforblockwrites.The mastercan writetoall 10 registerswith1 command bytebeingsentinitially.Inauto-incrementmode thelastfivebitsofthecommand byteareautomaticallyincrementedafterthebyteiswrittenand thenextdatabyteisstoredinthecorresponding register.Registersarewrittenintheordershown intheregistermap shown below.Writesattemptedtoreadonly registersdo notchange thevalueintheregister. IfB7=0, allthedatabytesarewrittentoorreadfromtheregisterdefinedby B4 throughB0 ina non-incremented fashion.B6 and B5 shouldalwaysbe 0.

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www.ti.com SCPS235 –NOVEMBER 2011 REGISTER MAP CONTROL REGISTER BITS COMMAND POWER-UPREGISTER PROTOCOLBYTE (HEX) DEFAULTB7 B6 B5 B4 B3 B2 B1 B0 AI 0 0 0 0 0 0 1 01h DeviceID and Control Read (B7-B1)Write(B0) 0100 0010 AI 0 0 0 0 0 1 1 03h I/ODirection Read/writebyte 0000 0000 AI 0 0 0 0 1 0 1 05h OutputState Read/writebyte 0000 0000 AI 0 0 0 0 1 1 1 07h OutputHigh-Impedance Read/writebyte 1111 1111 AI 0 0 0 1 0 0 1 09h InputDefaultState Read/writebyte 0000 0000 AI 0 0 0 1 0 1 1 0Bh Pull-up/downEnable Read/writebyte 1111 1111 AI 0 0 0 1 1 0 1 0Dh Pull-up/downSelect Read/writebyte 0000 0000 AI 0 0 0 1 1 1 1 0Fh InputStatus Read byte xxxxxxxx AI 0 0 1 0 0 0 1 11h InterruptMask Read/writebyte 0000 0000 AI 0 0 1 0 0 1 1 13h InterruptStatus Read byte 0000 0000 REGISTER DESCRIPTIONS Register01h – Device ID and Control The Device ID and Controlregistercontainsthe manufacturerID and firmwarerevision.The Controlregister indicateswhetherthedevicehas been resetand thedefaultvalueshave been set.

The Reset InterruptissetB1=1 when the deviceiseitherresetby the RESET pin,a power on reset,or softwarereset.
ResetInterruptisthenclearedafterbeingreadby themaster.
WritingtoB7–B1 has no effecton thesebitsintheregister.
A softwareresetisissuedwhen themasterwritesB0=1.
When readingfromB0,thevaluereadwillalwaysbe 0. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION ManufacturerID FirmwareRevision ResetInterrupt SoftwareReset DEFAULT 0 1 0 0 0 0 1 0 Register03h – I/ODirection The I/ODirectionRegisterconfiguresthedirectionoftheI/Opins.
Ifa bitinthisregisterissetto0,thecorrespondingportpinisenabledas an input
Ifa bitinthisregisterissetto1,thecorrespondingportpinisenabledas an output.
When theportissetas an outputtheinputbuffersaredisabledsuch thatthebus can float. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 0 0 0 0 0 0 0 0 Register05h – Output PortRegister The OutputPortRegistersetstheoutgoinglogiclevelsofthepinsdefinedas outputs.
When Bx issetto0,GPIOx = L
When Bx issetto1,GPIOx = H
Bitvaluesinthisregisterhave no effecton pinsdefinedas inputs
Reads fromthisregisterreflectthevaluethatisintheflip-flopcontrollingtheoutputselection,nottheactual pinvalue. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 0 0 0 0 0 0 0 0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com Register07h – Output High-Impedance The OutputHigh-ImpedanceRegisterdetermineswhetherpinssetas outputareenabledorhigh-impedance

When a bitinthisregisterissetto0,thecorrespondingGPIO-portoutputstatefollowsregistertheoutputport register(05h).
When a bitinthisregisterissetto1,thecorrespondingGPIO-portoutputissettohigh-impedance.
Bitvaluesinthisregisterhave no effecton pinsdefinedas inputs.Inturn,readsfromthisregisterreflectthe valuethatisintheflip-flopcontrollingtheoutputselection,nottheactualpinvalue. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 1 1 1 1 1 1 1 1 Register09h – InputDefaultState The InputDefaultStateRegistersetsthedefaultstateoftheGPIO-portinputforgeneratinginterrupts.
When a bitinthisregisterissetto0,thedefaultforthecorrespondinginputissettoLOW
When a bitinthisregisterissetto1,thedefaultforthecorrespondinginputissettoHIGH
Bitvaluesinthisregisterhave no effecton pinsdefinedas outputs.Inturn,readsfromthisregisterreflectthe valuethatisintheflip-flopcontrollingthedefaultstate,nottheactualpinvalue. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 1 1 1 1 1 1 1 1 Register0Bh – Pull-up/-downEnable The Pull-up/-downEnableRegisterenablesordisablesthepull-up/downresistoron theGPIO-portas definedin thePull-up/downSelectRegister(0Dh).
When a bitinthisregisterissetto0,thepull-up/downon thecorrespondingGPIO isdisabled.
When a bitinthisregisterissetto1,thepull-up/downon thecorrespondingGPIO isenabled. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 1 1 1 1 1 1 1 1 Register0Dh – Pull-up/-downSelect The Pull-up/downSelectRegisterallowstheusertoselecteithera pull-upor pull-downon theGPIO-port.This registeronlyselectsthepull-up/downresistoron theGPIO-port,whiletheenabling/disablingiscontrolledby the Pull-up/downEnableRegister(0Bh).
When a bitinthisregisterissetto0,thepull-downon thecorrespondingGPIO isselected.
When a bitinthisregisterissetto1,thepull-upon thecorrespondingGPIO isselected. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 0 0 0 0 0 0 0 0

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www.ti.com SCPS235 –NOVEMBER 2011 Register0Fh – InputStatusRegister The InputStatusRegisterreflectstheincominglogiclevelsoftheGPIOs setas inputs.

The defaultvalue,X,isdeterminedby theexternallyappliedlogiclevel.
Itonlyactson readoperation.Attemptedwritestothisregisterhave no effect.
ForGPIOs setas outputsthisregisterwillreadHIGH. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT X X X X X X X X Register11h – InterruptMask Register The InterruptMask Registercontrolsthegenerationofan interrupttotheINT pinwhen theGPIO-portinputstate changes state.
When a bitinthisregisterissetto0,an interruptgeneratedby theinterruptstatusregistercausestheINT pin tobe assertedLOW.
When a bitinthisregisterissetto1,theinterruptforthecorrespondingGPIO isdisabled.The corresponding bitintheInterruptStatusRegister(13h)willstillbe asserted.
INT isnotaffectedwhen GPIO-portisdefinedas outputs. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 0 0 0 0 0 0 0 0 Register13h – InterruptStatusRegister The InterruptStatusRegisterbitisassertedwhen thebitchanges toa valueoppositetothedefaultvaluedefined intheInputDefaultStateRegister(09h).
Thisbitisclearedand theINT pinisde-assertedupon readofthisregister.
The inputmust be assertedback tothedefaultstatebeforethisbitissetagain.
IftheGPIO-portpinisdefinedas an output,thisbitisneverset.
Attemptedwritestothisregister,have no effect. BIT B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DEFAULT 0 0 0 0 0 0 0 0 POWER-ON RESET When power (from0V) isappliedtoVCCP ,an internalpower-onresetholdstheTCA7408 ina resetconditionuntil VCCP has reachedVPOR .At thattime,theresetconditionisreleased,and theTCA7408 registersand I2C/SMBus statemachine initializetotheirdefaultstates.Afterthat,VCCP must be loweredtobelowVPORF and back up tothe operatingvoltagefora power-resetcycle.
Duringpower up,ifVCCI ramps beforeVCCP ,a power on reseteventoccursand theI2C registersarereset.
IfVCCP ramps up beforeVCCI,thenthedevicewithresetas ifRESET = 0
The deviceisresetregardlessofwhichVCCx ramps first. RESET (RESET) INPUT The RESET inputcan be assertedtoinitializethesystem whilekeepingVCCP atitsoperatinglevel.A resetcan be accomplishedby holdingtheRESET pinlow fora minimum of tW . The TCA7408 registersand I2C/SMBus statemachine are changed totheirdefaultstateonce RESET islow (0).Only when RESET ishigh(1),GPIO registerscan be accessedby theI2C pin.Thisinputrequiresa pull-upresistortoVCCI,ifno activeconnectionis used. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com INTERRUPT (INT)OUTPUT An interruptisgeneratedby a risingorfallingedge oftheportinputsintheinputmode. Aftertimetiv,thesignal INT isvalid.Resettingtheinterruptcircuitisachievedby readingtheInterruptStatusRegister.Resettingoccurs inthe read mode at the acknowledge (ACK) or not acknowledge (NACK) bitafterthe risingedge of the SCL signal.Each change oftheI/Osafterresettingisdetectedand istransmittedas INT.The valuesintheinterrupt statusregisterare sampled on the risingedge of SCL duringthe read addressacknowledge.Ifan interrupt occursbeforethisevent,itwillbe reflectedinthisregisterinthenextreadcycle.Ifan interruptoccursveryclose tothisevent,itmay be reflectedinboththecurrentand thenextreadcycle.At no pointisa validinterruptever missed. Reading fromorwritingtoanotherdevicedoes notaffecttheinterruptcircuit,and a pinconfiguredas an output cannotcause an interrupt.Changing an I/Ofroman outputtoan inputmay cause a falseinterrupttooccur,ifthe stateofthepindoes notmatch thecontentsoftheInputDefaultStateRegister. The INT outputhas an open-drainstructureand requiresa pullupresistorto VCCP or VCCI dependingon the application.INT shouldbe connectedtothevoltagesourceofthedevicethatrequirestheinterruptinformation. BUS TRANSACTIONS Data isexchanged between themasterand TCA7408 throughwriteand readcommands. Writes Data istransmittedtotheTCA7408 by sendingthedeviceaddressand settingtheleastsignificantbit(LSB)toa logic0.The command byteissentaftertheaddressand determineswhichregisterreceivesthedatathatfollows thecommand byte.Thereisno limitationon thenumber ofdatabytessentinone writetransmission. Figure4. WritetoOutput stateRegister(Note:ADDR = 0) Figure5. WritetoI/ODirectionRegister(Note:ADDR = 0)

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www.ti.com SCPS235 –NOVEMBER 2011 Reads The bus masterfirstmust send theTCA7408 addresswiththeLSB settoa logic0.The command byteissent aftertheaddressand determineswhichregisterisaccessed. Aftera restart,thedeviceaddressissentagainbut,thistime,theLSB issettoa logic1.Data fromtheregister definedby thecommand bytethenissentby theTCA7408. Data isclockedintotheregisteron therisingedge oftheACK clockpulse. Figure6. Read From Register NOTE: ADDR = 0 Figure7. Read From InputStatusRegister Transferofdatacan be stoppedatany timeby a Stop condition.When thisoccurs,datapresentatthelatest acknowledgephase isvalid(outputmode).Itisassumed thatthecommand bytepreviouslyhas been setto0Fh (readInputStatusRegister).Thisfigureeliminatesthecommand bytetransfer,a restart,and slaveaddresscall between theinitialslaveaddresscalland actualdatatransferfromGPIO. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1)(2)(3) MIN MAX UNIT VCCI –0.3 6 Supplyvoltagerange V VCCP –0.3 4 VI Inputvoltagerange –0.3 6 V VO Outputvoltagerange –0.3 6 V IIK Inputclamp current ADDR, RESET, SCL VI< 0 ±20 mA IOK Outputclamp current INT VO < 0 ±20 mA GPIO port VO < 0 orVO > VCCP ±20 IIOK Input/outputclamp current mA SDA VO < 0 orVO > VCCI ±20 GPIO port VO = 0 toVCCP 10ContinuousoutputlowIOL mAcurrent SDA, INT VO = 0 toVCCI 10 ContinuousoutputhighIOH GPIO port VO = 0 toVCCP 10 mAcurrent ContinuouscurrentthroughGND 200 mA ICC ContinuouscurrentthroughVCCP 160 ContinuouscurrentthroughVCCI 10 θJA Package thermalimpedance ZSZ package TBD °C/W Tstg Storagetemperaturerange –65 150 °C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings” may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions” isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) The inputnegative-voltageand outputvoltageratingsmay be exceeded iftheinputand outputcurrentratingsareobserved. (3) The package thermalimpedance iscalculatedinaccordancewithJESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VCCI 1.65 5.5 Supplyvoltage V VCCP 1.65 3.6 SCL, SDA 0.7× VCCI 5.5 V VIH High-levelinputvoltage RESET, ADDR 0.65× VCCI 5.5 GPIO7 –GPIO0 0.65× VCCP 3.6 SCL, SDA –0.3 0.3× VCCI V VIL Low-levelinputvoltage RESET, ADDR –0.3 0.35x VCCI GPIO7 –GPIO0 –0.3 0.35× VCCP IOH High-leveloutputcurrent GPIO7 –GPIO0 10 mA IOL Low-leveloutputcurrent GPIO7 –GPIO0 10 mA TA Operatingfree-airtemperature –40 85 °C

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www.ti.com SCPS235 –NOVEMBER 2011

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS VCCI VCCP MIN TYP MAX UNIT 1.65V 1.65V 1.2 IOH = –6 mA 2.3V 2.3V 1.8 V 3 V 3 V 2.6 VOH GPIO-porthigh-leveloutputvoltage 1.65V 1.65V 1.1 IOH = –10 mA 2.3V 2.3V 1.7 V 3 V 3 V 2.5 1.65V 1.65V 0.45 IOL = 6 mA 2.3V 2.3V 0.25 V 3 V 3 V 0.25 VOL GPIO-portlow-leveloutputvoltage 1.65V 1.65V 0.6 IOL = 10 mA 2.3V 2.3V 0.3 V 3 V 3 V 0.25 1.65V to5.5V 1.65V to3.6V 10 SDA (2) INT 1.65V to5.5V 1.65V to3.6V 3 II SCL, SDA, RESET, ADDR μA VI= VCCP orGND ±0.1 IIH VI= VCCP 1.65V to5.5V 1.65V to3.6V 1 GPIO port μA IIL VI= GND 1 (1) When power (from0 V) isappliedtoVCCP ,an internalpower-onresetholdstheTCA7408 ina resetconditionuntilVCCP has reached VPOR .Atthattime,theresetconditionisreleased,and theTCA7408 registersand I2C/SMBus statemachine initializetotheirdefault states.Afterthat,VCCP must be loweredtobelow0.2V and back up totheoperatingvoltagefora power-resetcycle. (2) IOL forSDA isspecifiedforstandardmode, fastmode, and fastmode pluscapability(at2.3V). ELECTRICAL CHARACTERISTICS (Continued) PARAMETER TEST CONDITIONS VCCI VCCP MIN TYP (1) MAX UNIT VI on SDA, ADDR, and RESET = VCCI or 3.6V to5.5V 3.6V TBD TBD GND, VI on GPIO port= VCCP orFastMode SDA, GPIO port, 2.3V to3.6V 2.3V to3.6V TBD TBD μAADDR, RESET GND, IO = 0,I/O= inputs,Operatingmode 1.65V to2.3V 1.65V to2.3V TBD TBDfSCL = 400 kHzICC (ICCI + ICCP ) VI on SDA, ADDR, and RESET= VCCI or 3.6V to5.5V 3.6V TBD TBD GND, VI on GPIO port= VCCP orFastMode+ SDA, GPIO port, μAADDR, RESET GND, IO = 0,I/O= inputs,Operatingmode 2.3V to3.6V 2.3V to3.6V TBD TBD fSCL = 1MHz C i SCL VI = VCCI orGND 1.65V to5.5V 1.65V to3.6V 6 TBD pF SDA VIO = VCCI orGND 7 TBD C io 1.65V to5.5V 1.65V to3.6V pF GPIO port VIO = VCCP orGND 7.5 TBD R PU Pullup resistor VI = GND 1.65V to5.5V 1.65V to3.6V 100 kΩ R PD Pulldown resistor VI = VCCP 1.65V to5.5V 1.65V to3.6V 100 kΩ (1) Alltypicalvaluesareatnominalsupplyvoltage(1.8V,2.5V,3.3V,or5V VCC) and TA = 25°C. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com I2C INTERFACE TIMING REQUIREMENTS FAST MODE PLUSSTANDARD MODE FAST MODE UNIT(FM+) I2C BUSI2C BUS I2C BUSPARAMETER (VDDI = 2.3– 5.5V) MIN MAX MIN MAX MIN MAX fscl 0 100 0 400 0 1000 kHzI2C clockfrequency tsch 4 0.6 0.26 μsI2C clockhightime tscl 4.7 1.3 0.5 μsI2C clocklowtime tsp 50 50 50 nsI2C spiketime tsds 250 100 50 nsI2C serialdatasetuptime tsdh 0 0 0 nsI2C serialdataholdtime ticr 1000 20 + 0.1Cb 300 120 nsI2C inputrisetime ticf 300 20 + 0.1Cb 300 120 nsI2C inputfalltime tocf 300 20 + 0.1Cb 300 120 μsI2C outputfalltime;10 pF to400 pF bus tbuf 4.7 1.3 0.5 μsI2C bus freetimebetween Stopand Start tsts 4.7 0.6 0.26 μsI2C StartorrepeaterStartconditionsetuptime tsth 4 0.6 0.26 μsI2C StartorrepeaterStartconditionholdtime tsps 4 0.6 0.26 μsI2C Stopconditionsetuptime tvd(data) Validdatatime;SCL lowtoSDA outputvalid 1 0.3 0.9 0.45 μs ValiddatatimeofACK condition;ACK signalfromSCL lowtotvd(ack) 1 0.3 0.9 0.45 μsSDA (out)low RESET TIMING REQUIREMENTS STANDARD MODE, FAST MODE, FAST MODE PLUS (FM+) PARAMETER UNITI2C BUS MIN MAX tW Resetpulseduration 250 ns tREC Resetrecoverytime TBD ns tRESET Time toreset 250 ns SWITCHING CHARACTERISTICS STANDARD MODE, FAST MODE, FAST MODE PLUS (FM+)FROM TOPARAMETER UNITI2C BUS(INPUT) (OUTPUT) MIN MAX tiv Interruptvalidtime GPIO port INT 20 ns tir Interruptresetdelaytime SCL INT 250 ns tpv Outputdatavalid SCL GPIO7 –GPIO0 250 ns tps Inputdatasetuptime GPIO port SCL 0 ns tph Inputdataholdtime GPIO port SCL 300 ns

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ProductFolderLink(s):TCA7408

www.ti.com SCPS235 –NOVEMBER 2011 PARAMETER MEASUREMENT INFORMATION NOTE: C L includesprobe and jigcapacitance.tocf ismeasured withC L of 10 pF or 400 pF. Allinputsare suppliedby generatorshaving the followingcharacteristics:PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. Allparametersand waveformsarenotapplicabletoalldevices. Figure8. I2C InterfaceLoad Circuitand VoltageWaveforms Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) NOTE: C L includesprobeand jigcapacitance.Allinputsaresuppliedby generatorshavingthefollowingcharacteristics:PRR ≤ 10 MHz, ZO = 50 Ω,tr/tf≤ 30 ns.Allparametersand waveformsarenotapplicabletoalldevices. Figure9. InterruptLoad Circuitand VoltageWaveforms

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ProductFolderLink(s):TCA7408

www.ti.com SCPS235 –NOVEMBER 2011 PARAMETER MEASUREMENT INFORMATION (continued) NOTE: C L includesprobeand jigcapacitance.tpvismeasured from0.7× VCC on SCL to50% I/O(Pn)output.Allinputsare suppliedby generatorshavingthefollowingcharacteristics:PRR ≤ 10 MHz, ZO = 50 Ω,tr/tf ≤ 30 ns.The outputsare measured one ata time,withone transitionpermeasurement.Allparametersand waveforms arenotapplicabletoall devices. Figure10. GPIO-portLoad Circuitand Timing Waveforms Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) NOTE: C L includesprobeand jigcapacitance.Allinputsaresuppliedby generatorshavingthefollowingcharacteristics:PRR ≤ 10 MHz, ZO = 50 Ω,tr/tf ≤ 30 ns.The outputsare measured one ata time,withone transitionper measurement. I/Osareconfiguredas inputs.Allparametersand waveformsarenotapplicabletoalldevices. Figure11. Reset Load Circuitsand VoltageWaveforms

ProductFolderLink(s):TCA7408

www.ti.com SCPS235 –NOVEMBER 2011

APPLICATION INFORMATION

POWER-ON RESET REQUIREMENTS Intheeventofa glitchordatacorruption,TCA7408 can be resettoitsdefaultconditionsby usingthepower-on resetfeature.Power-on resetrequiresthatthe devicego througha power cycleto be completelyreset.This resetalsohappens when thedeviceispowered on forthefirsttimeinan application. The two typesofpower-onresetareshown inthefiguresbelow: Figure12. VCC isLowered Below 0.2V or 0 V and Then Ramped Up toVCC Figure13. VCC isLowered Below thePOR Threshold,Then Ramped Back Up toVCC Glitchesinthepower supplycan alsoaffectthepower-onresetperformanceofthisdevice.The glitchwidth(tGW ) and height(tGH ) are dependent on each other.The bypass capacitance,source impedance, and device impedance are factorsthataffectpower-onresetperformance.Figure14 providesmore informationon how to measure thesespecifications. Figure14. GlitchWidth and GlitchHeight VPOR iscriticaltothepower-onreset.VPOR isthevoltagelevelatwhichtheresetconditionisreleasedand allthe registersand theI2C/SMBus statemachine areinitializedtotheirdefaultstates.The valueofVPOR differsbased on theVCC beingloweredtoorfrom0.Figure15 providesmore detailson thisspecification. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):TCA7408

SCPS235 –NOVEMBER 2011 www.ti.com Figure15. VPOR The tablebelow specifiestheperformanceofthepower-onresetfeatureforTCA7408 forbothtypesofpower-on reset. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES AT TA = 25°C (1) PARAMETER DESCRIPTION MIN TYP MAX UNIT tFT Fallrate 1 100 ms tRT Riserate 0.1 100 ms tRR_GND Time tore-ramp(when VCC dropstoGND) 40 μs tRR_POR50 Time tore-ramp(when VCC dropstoVPOR_MIN – 50 mV) 40 μs LevelthatVCCP can glitchdown to,butnotcause a functionaldisruptionwhenVCC_GH 1.2 VVCCX_GW = 1 μs tGW Glitchwidththatwillnotcause a functionaldisruptionwhen VCCX_GH = 0.5× VCCx 10 μs VPORF VoltagetrippointofPOR on fallingVCC 0.86 1.22 V VPORR VoltagetrippointofPOR on risingVCC 1.1 1.34 V (1) Not tested.Specifiedby design.

ProductFolderLink(s):TCA7408

www.ti.com 15-Dec-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TCA7408ZSZR ACTIVE uCSP ZSZ 16 2500 Green (RoHS & no Sb/Br) 0.5NI,0.2AU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA7408ZSZR uCSP ZSZ 16 2500 338.1 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 2

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Summary

Low-Voltage 8-Bit I2C and SMBus I/O Expander with Interrupt Output, RESET, I/ODirection Registers, and Programmable Pull-up/Pull-down

Description

Low-Voltage 8-Bit I2C and SMBus I/O Expander with Interrupt Output, RESET, I/ODirection Registers, and Programmable Pull-up/Pull-down

Source title TCA7408 Datasheet(PDF) - Texas Instruments

Read TCA7408 online.

TCA7408 TI1 | Alldatasheet

Document overview

Technical content

DESCRIPTION

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ELECTRICAL CHARACTERISTICS

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APPLICATION INFORMATION

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TCA7408 specifications and overview.

More parts from the same family.