TCA6408ARGTRG4.A

TCA6408A TI | Alldatasheet

Document overview

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Technical content

TCA6408A Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output, Reset, and Configuration Registers

1 Features

• I2C to Parallel port expander
• Operating power-supply voltage range of 1.65 V to 5.5 V
• Allows bidirectional voltage-level translation and gpio expansion between 1.8-V, 2.5-V, 3.3-V, and 5-V I2C bus and P-ports
• Low standby current consumption of 1 μA
• 5-V Tolerant I/O ports
• 400-kHz Fast I2C bus
• Hardware address pin allows two TCA6408A Devices on the same I2C/SMBus bus
• Active-low reset ( RESET) input
• Open-drain active-low interrupt ( INT) output
• Input and output configuration register
• Polarity inversion register
• Internal power-on reset
• Power up with all channels configured as inputs
• No glitch on power up
• Noise filter on SCL and SDA inputs
• Latched outputs with high-current drive maximum capability for directly driving LEDs
• Latch-up performance exceeds 100 mA Per JESD 78, class II
• Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
• ESD Protection exceeds JESD 22 – 2000-V Human body model (A114-A) – 1000-V Charged-device model (C101)

2 Applications

• Servers
• Routers (telecom switching equipment)
• Personal computers
• Personal electronics (gaming consoles)
• Industrial automation
• Products with GPIO-limited processors

3 Description

The TCA6408A is a 16-pin device that provides 8- bits of general purpose parallel input/output (I/O) expansion for the two-line bidirectional I 2C bus (or SMBus) protocol. This device can operate with a power supply voltage ranging from 1.65 V to 5.5 V on both the I2C bus side (VCCI) and on the P-port side (VCCP). This allows the TCA6408A to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components such as LEDs remain at a 5-V power supply. The device supports both 100-kHz (Standard-mode) and 400-kHz (Fast-mode) clock frequencies. I/O expanders such as the TCA6408A provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and so forth.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM) TCA6408A TSSOP (16) 5.00 mm × 4.40 mm VQFN (16) 3.00 mm × 3.00 mm UQFN (16) 2.60 mm × 1.80 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. TCA6408A SDA I2C or SMBus Controller (e.g. Processor) SCL INT RESET VCCI VCCP GND ADDR Peripheral Devices RESET, EN or Control Inputs INT or status outputs LEDs Keypad Simplified Schematic TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.1 Receiving Notification of Documentation Updates..34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (July 2015) to Revision E (January 2023) Page Changes from Revision C (July 2009) to Revision D (July 2015) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
• VIH - Split SCL, SDA and RESET to different rows in the Recommended Operating Conditions table. Max TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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5 Pin Configuration and Functions

1 VCCI 16 V CCP

2 ADDR 15 SDA

4 P0 13 INT

5 P1 12 P7

6 P2 11 P6

7 P3 10 P5

8 GND 9 P4

Figure 5-1. PW Package, 16-Pin TSSOP (Top View)

16 ADDR5P3

15 VCCI 6GND

2 P0 11 INT

14 VCCP 7P4

3 P1 10 P7

13 SDA8P5

4 P2 9 P6

Figure 5-2. RGT Package, 16-Pin VQFN (Top View) Figure 5-3. RSV Package, 16-Pin UQFN (Top View) Table 5-1. Pin Functions PIN

DESCRIPTION

NAME TSSOP UQFN, VQFN ADDR 2 16 Address input. Connect directly to VCCP or ground. GND 8 6 Ground INT 13 11 Interrupt output. Connect to VCCI through a pull-up resistor. P0 4 2 P-port input/output (push-pull design structure). At power on, P0 is configured as an input. P1 5 3 P-port input/output (push-pull design structure). At power on, P1 is configured as an input. P2 6 4 P-port input/output (push-pull design structure). At power on, P2 is configured as an input. P3 7 5 P-port input/output (push-pull design structure). At power on, P3 is configured as an input. P4 9 7 P-port input/output (push-pull design structure). At power on, P4 is configured as an input. www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TCA6408A

Table 5-1. Pin Functions (continued) PIN NAME TSSOP UQFN, VQFN P5 10 8 P-port input/output (push-pull design structure). At power on, P5 is configured as an input. P6 11 9 P-port input/output (push-pull design structure). At power on, P6 is configured as an input. P7 12 10 P-port input/output (push-pull design structure). At power on, P7 is configured as an input. RESET 3 1 Active-low reset input. Connect to VCCI through a pull-up resistor, if no active connection is used. SCL 14 12 Serial clock bus. Connect to VCCI through a pull-up resistor. SDA 15 13 Serial data bus. Connect to VCCI through a pull-up resistor. VCCI 1 15 Supply voltage of I2C bus. Connect directly to the VCC of the external I2C controller. Provides voltage level translation. VCCP 16 14 Supply voltage of TCA6408A for P-ports TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (see (1)) MIN MAX UNIT VCCI Supply voltage for I2C pins –0.5 6.5 V VCCP Supply voltage for P-ports –0.5 6.5 V VI Input voltage(2) –0.5 6.5 V VO Output voltage(2) –0.5 6.5 V IIK Input clamp current ADDR, RESET, SCL VI < 0 ±20 mA IOK Output clamp current INT VO < 0 ±20 mA IIOK Input/output clamp current P-port VO < 0 or VO > VCCP ±20 mA SDA VO < 0 or VO > VCCI ±20 IOL Continuous output low current P-port VO = 0 to VCCP 50 mA Continuous output low current SDA, INT VO = 0 to VCCI 25 IOH Continuous output high current P-port VO = 0 to VCCP 50 mA ICC Continuous current through GND 200 mAContinuous current through VCCP 160 Continuous current through VCCI 10 Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

VCCI Supply voltage for I2C pins 1.65 5.5 V VCCP Supply voltage for P-ports 1.65 5.5 VIH High-level input voltage SCL, SDA 0.7 × VCCI VCCI VRESET 0.7 × VCCI 5.5 ADDR, P7–P0 0.7 × VCCP 5.5 VIL Low-level input voltage SCL, SDA, RESET –0.5 0.3 × VCCI V ADDR, P7–P0 –0.5 0.3 × VCCP IOH High-level output current P7–P0 10 mA IOL Low-level output current P7–P0 25 mA TA Operating free-air temperature –40 85 °C www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TCA6408A

6.4 Thermal Information

THERMAL METRIC(1) TCA6408A UNITPW (TSSOP) RGT (VQFN) RSV (UQFN)

16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 122 65.5 127.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.4 92.1 62.3 °C/W RθJB Junction-to-board thermal resistance 67.1 40.0 48.4 °C/W ψJT Junction-to-top characterization parameter 10.8 6.9 2.5 °C/W ψJB Junction-to-board characterization parameter 66.5 21.3 48.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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6.5 Electrical Characteristics

over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCP MIN TYP(1) MAX UNIT VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V –1.2 V VPOR Power-on reset voltage(2) VI = VCCP or GND, IO = 0 1.65 V to 5.5 V 1 1.4 V VOH P-port high-level output voltage IOH = –8 mA 1.65 V 1.2 V 2.3 V 1.8 3 V 2.6 4.5 V 4.1 IOH = –10 mA 1.65 V 1.1 2.3 V 1.7 3 V 2.5 4.5 V 4.0 VOL P-port low-level output voltage IOL = 8 mA 1.65 V 0.45 V 2.3 V 0.25 3 V 0.25 4.5 V 0.2 IOL = 10 mA 1.65 V 0.6 2.3 V 0.3 3 V 0.25 4.5 V 0.2 IOL SDA VOL = 0.4 V 1.65 V to 5.5 V mA INT 3 15 II SCL, SDA, RESET VI = VCCI or GND 1.65 V to 5.5 V ±0.1 μA ADDR VI = VCCP or GND ±0.1 IIH P-port VI = VCCP 1.65 V to 5.5 V 1 μA IIL P-port VI = GND 1 μA ICC (ICCI + ICCP) Operating mode SDA, P-port, ADDR, RESET VI on SDA and RESET= VCCI or GND, VI on P-port and ADDR = VCCP or GND, IO = 0, I/O = inputs, fSCL = 400 kHz 3.6 V to 5.5 V 10 20 μA 2.3 V to 3.6 V 6.5 15 1.65 V to 2.3 V 4 9 Standby mode SCL, SDA, P-port, ADDR, RESET VI on SCL, SDA and RESET = VCCI or GND, VI on P-Port and ADDR = VCCP or GND, IO = 0, I/O = inputs, fSCL = 0 3.6 V to 5.5 V 1.5 7 2.3 V to 3.6 V 1 3.2 1.65 V to 2.3 V 0.5 1.7 ΔICCI Additional current in standby mode SCL, SDA, RESET One input at VCCI – 0.6 V, Other inputs at VCCI or GND 1.65 V to 5.5 V 25 μA ΔICCP P-port, ADDR One input at VCCP – 0.6 V, Other inputs at VCCP or GND 1.65 V to 5.5 V 80 μA Ci SCL VI = VCCI or GND 1.65 V to 5.5 V 6 7 pF Cio SDA VIO = VCCI or GND 1.65 V to 5.5 V 7 8 pF P-port VIO = VCCP or GND 7.5 8.5 (1) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. (2) When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A in a reset condition until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6408A registers and I2C/SMBus state machine initialize to their default states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TCA6408A

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) STANDARD MODE I2C BUS FAST MODE I2C BUS UNIT MIN MAX MIN MAX fscl I2C clock frequency 0 100 0 400 kHz tsch I2C clock high time 4 0.6 μs tscl I2C clock low time 4.7 1.3 μs tsp I2C spike time 0 50 0 50 ns tsds I2C serial data setup time 250 100 ns tsdh I2C serial data hold time 0 0 ns ticr I2C input rise time 1000 20 + 0.1Cb 300 ns ticf I2C input fall time 300 20 + 0.1Cb 300 ns tocf I2C output fall time, 10-pF to 400-pF bus 300 20 + 0.1Cb 300 μs tbuf I2C bus free time between Stop and Start 4.7 1.3 μs tsts I2C Start or repeater Start condition setup time 4.7 0.6 μs tsth I2C Start or repeater Start condition hold time 4 0.6 μs tsps I2C Stop condition setup time 4 0.6 μs tvd(data) Valid data time, SCL low to SDA output valid 1 1 μs tvd(ack) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1 1 μs

6.7 Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-4) STANDARD MODE I2C BUS FAST MODE I2C BUS UNIT MIN MAX MIN MAX tW Reset pulse duration 4 4 ns tREC Reset recovery time 0 0 ns tRESET Time to reset 600 600 ns TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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6.8 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) STANDARD MODE I2C BUS FAST MODE I2C BUS UNIT MIN MAX MIN MAX tiv Interrupt valid time P-Port INT 4 4 μs tir Interrupt reset delay time SCL INT 4 4 μs tpv Output data valid SCL P7–P0 400 400 ns tps Input data setup time P-Port SCL 0 0 ns tph Input data hold time P-Port SCL 300 300 ns www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TCA6408A

6.9 Typical Characteristics

TA = 25°C (unless otherwise noted) 8535 6010-15-40 Temperature, °C)T (A Supply Current, µA) I (CC VCC = 3.3 V VCC = 2.5 V V = 5 VCC V = 5.5 VCC V = 1.8 VCC V = 1.65 VCC Figure 6-1. Supply Current vs Temperature Temperature, °C)T (A Supply Current, A) I (nCC 8535 6010–15–40 2000 200 400 600 800 1000 1200 1400 1600 1800 V = 1.8 VCC V = 1.65 VCC V = 2.5 VCC V = 3.3 VCC V = 5.5 VCC V = 5 VCC Figure 6-2. Standby Supply Current vs Temperature Supply Current, I (µA) CC Supply Voltage, V (V)CC 2.0 5.51.5 Figure 6-3. Supply Current vs Supply Voltage 0.0 0.5 Sink Current, (mA) ISINK Output Low Voltage, V)V (OL V = 1.65 VCC TA –= 40°C TA = 85°C T = 25°CA Figure 6-4. I/O Sink Current vs Output Low Voltage Sink Current, (mA) ISINK Output Low Voltage, V)V (OL V = 1.8 VCC TA = 40°C– TA = 85°C T = 25°CA Figure 6-5. I/O Sink Current vs Output Low Voltage Sink Current, (mA) ISINK Output Low Voltage, V)V (OL V = 2.5 VCC TA = 40°C– TA = 85°C T = 25°CA Figure 6-6. I/O Sink Current vs Output Low Voltage TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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6.9 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) Sink Current, (mA) ISINK Output Low Voltage, V)V (OL V = 3.3 VCC TA –= 40°C TA = 85°C T = 25°CA Figure 6-7. I/O Sink Current vs Output Low Voltage Sink Current, (mA) ISINK Output Low Voltage, V)V (OL V = 5.0 VCC TA = 40°C– TA = 85°C T = 25°CA Figure 6-8. I/O Sink Current vs Output Low Voltage Sink Current, (mA) ISINK Output Low Voltage, V)V (OL V = 5.5 VCC TA = 40°C– TA = 85°C T = 25°CA Figure 6-9. I/O Sink Current vs Output Low Voltage 8535 6010-15-40 100 150 200 250 0Output Low Voltage, mV) V (OL Temperature, °C)T (A V =□1.8□V,□I =□1□mACC SINK V =□5□V,□I =□10□mACC SINK V =□1.8□V,□I =□10□mACC SINK Figure 6-10. I/O Low Voltage vs Temperature 0.0 Source Current, mA) I (SOURCE V V (V)CCP OH– V = 1.65 VCC T = 40°C–A T = 25°CA T = 85°CA Figure 6-11. I/O Source Current vs Output High Voltage 0.0 Source Current, mA) I (SOURCE V V (V)CCP OH– V = 1.8 VCC T = 40°C–A T = 25°CA T = 85°CA Figure 6-12. I/O Source Current vs Output High Voltage www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TCA6408A

TA = 25°C (unless otherwise noted) 0.0 Source Current, mA) I (SOURCE V V (V)CCP OH– V = 2.5 VCC T = 40°C–A T = 25°CA T = 85°CA Figure 6-13. I/O Source Current vs Output High Voltage 0.0 Source Current, mA) I (SOURCE V V (V)CCP OH– V = 3.3 VCC T = 40°C–A T = 25°CA T = 85°CA Figure 6-14. I/O Source Current vs Output High Voltage 0.0 Source Current, mA) I (SOURCE V V (V)CCP OH– V = 5.0 VCC T = 40°CA – T = 25°CA T = 85°CA Figure 6-15. I/O Source Current vs Output High Voltage 0.0 Source Current, mA) I (SOURCE V V (V)CCP OH– V = 5.5 VCC T = 40°CA – T = 25°CA T = 85°CA Figure 6-16. I/O Source Current vs Output High Voltage 8535 6010-15-40 V V (mV)CC OH Temperature, °C)T (A 350 100 150 200 250 300 I = 10□mASOURCE – V =□5□VCC V =□1.8□VCC Figure 6-17. I/O High Voltage vs Temperature TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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7 Parameter Measurement Information

SDA LOAD□CONFIGURATION VCCI R =□1□kL /c87 C =□50□pF (see□Note A) L DUT SDA Two□Bytes□for□READ□□Input□□Port□Register (see□Figure□9) VOLTAGE□WAVEFORMS BYTE DESCRIPTION I C□address Input□register□port□data SCL SDA Stop Condition (P) Start Condition (S) Address Bit□7 (MSB) Address Bit□1 Bit□0 (LSB) W ACK (A) Data Bit□7 (MSB) Data Bit□0 (LSB) Stop Condition (P) 0.7 /c180VCCI 0.3 /c180VCCI Repeat□Start Condition Stop Condition 0.7 /c180VCCI 0.3 /c180VCCI tscl tsch tsp ticf ticf ticr tsth ticr tsds tsdh tocf tvd(ack) tvd tvd tsts tsps tbuf A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TCA6408A

AA AAS010000ADDR1 Data 11PData 2StartCondition8 Bits(One Data Byte)From PortData From PortTarget AddressR/W 87654321 AddressData 1Data 2INT BBAA Pn INTR/WAINT SCL View B− BView A− A ACKFrom TargetACKFrom TargetINTERRUPT LOAD CONFIGURATION VCCIR = 4.7 kLWC = 100 pFL(see Note A)DUTINT 0.7 V´CCI0.3 V´CCI0.5 V´CCI

0.5 V´CCI

0.5 V´CCP

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 7-2. Interrupt Load Circuit And Voltage Waveforms TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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UnstableDataLast Stable Bit SDA WRITE MODE (R/ = 0) WP0ASCL P3 READ MODE (R/ = 1) W DUT P-PORT LOAD CONFIGURATION Pn500 W500 W2 V´CCP 0.7 V´CCP0.3 V´CCI 0.7 V´CCI0.3 V´CCI0.5 V´CCP C = 50 pFL(see Note A) TargetACKtpv(see Note B) Pn Pn tpstph A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 7-3. P-Port Load Circuit And Timing Waveforms www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TCA6408A

ACK□or□Read□Cycle RESET Pn SDA LOAD□CONFIGURATION VCCI R =□1□k /c87L C =□50□pF (see□Note A) L DUT SDA DUT P-PORT□LOAD□CONFIGURATION Pn 500 /c87 500 /c87

2 V/c180 CCP

C =□50□pF (see□Note A) L

0.3 V/c180 CCI

A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 7-4. Reset Load Circuits And Voltage Waveforms TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The bidirectional voltage-level translation in the TCA6408A is provided through V CCI. VCCI should be connected to the V CC of the external SCL/SDA lines. This indicates the V CC level of the I 2C bus to the TCA6408A. The voltage level on the P-port of the TCA6408A is determined by VCCP. The TCA6408A consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) Register. At power on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output Register. The polarity of the Input Port Register can be inverted with the Polarity Inversion Register. All registers can be read by the system controller. The system controller can reset the TCA6408A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I 2C/ SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The TCA6408A open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port Register state and is used to indicate to the system controller that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6408A can remain a simple target device. The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I 2C address and allow up to two devices to share the same I2C bus or SMBus. www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TCA6408A

8.2 Functional Block Diagrams

8 BitsInput

P7–P0 A. All pin numbers shown are for the PW package. B. All I/Os are set to inputs at reset. Figure 8-1. Logic Diagram (Positive Logic) TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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D FF CK Q Q D FF CK Q Q D FF CK Q Q D FF CK Q Q Data From Shift Register Data From Shift Register A. On power up or reset, all registers return to default values. Figure 8-2. Simplified Schematic of P0 to P7 www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TCA6408A

8.3 Feature Description

8.3.1 Voltage Translation

Table 8-1 shows some common supply voltage options for voltage translation between the I 2C bus and the P-ports of the TCA6408A. Table 8-1. Voltage Translation VCCI (SCL AND SDA OF I2C CONTROLLER) (V) VCCP (P-PORT) (V) 1.8 1.8 1.8 2.5 1.8 3.3 1.8 5 2.5 1.8 2.5 2.5 2.5 3.3 2.5 5 3.3 1.8 3.3 2.5 3.3 3.3 3.3 5 5 1.8 5 2.5 5 3.3 5 5

8.3.2 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either V CC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.

8.3.3 Interrupt Output ( INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t iv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pull-up resistor to V CCP or V CCI, depending on the application. INT should be connected to the voltage source of the device that requires the interrupt information.

8.3.4 Reset Input ( RESET)

The RESET input can be asserted to initialize the system while keeping the V CCP at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of t W. The TCA6408A registers and TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P-port can be changed externally or through the controller. This input requires a pull-up resistor to VCCI, if no active connection is used.

8.4 Device Functional Modes

8.4.1 Power-On Reset (POR)

When power (from 0 V) is applied to V CCP, an internal power-on reset holds the TCA6408A in a reset condition until V CCP has reached V POR. At that time, the reset condition is released, and the TCA6408A registers and I2C/SMBus state machine initialize to their default states. After that, V CCP must be lowered to below V PORF and back up to the operating voltage for a power-reset cycle.

8.4.2 Powered-Up

When power has been applied to both V CCP and VCCI and a POR has taken place, the device is in a functioning mode. The device will always be ready to receive new requests via the I2C bus.

8.5 Programming

8.5.1 I2C Interface

The TCA6408A has a standard bidirectional I 2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I 2C bus has a specific device address to differentiate between other target devices that are on the same I 2C bus. Many target devices will require configuration upon startup to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I 2C lines. (For further details, refer to I2C Pull-up Resistor Calculation (SLVA689).) Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. The following is the general procedure for a controller to access a target device: 1. If a controller wants to send data to a target:

• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition. 2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter.
• Controller-receiver terminates the transfer with a STOP condition. SCL SDA START Condition STOP Condition Data Transfer Figure 8-3. Definition of Start and Stop Conditions www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TCA6408A

MSB Bit Bit Bit Bit Bit Bit LSB Byte: 1010 1010 ( 0xAAh ) 1 0 1 0 1 0 1 0 SDA line stable while SCL line is high ACK ACK Figure 8-4. Bit Transfer Table 8-2. Interface Definition BYTE BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C target address L H L L L L ADDR R/ W I/O data bus P7 P6 P5 P4 P3 P2 P1 P0

8.5.2 Bus Transactions

Data must be sent to and received from the target devices, and this is accomplished by reading from or writing to registers in the target device. Registers are locations in the memory of the target which contain information, whether it be the configuration information or some sampled data to send back to the controller. The controller must write information to these registers in order to instruct the target device to perform a task. While it is common to have registers in I 2C targets, note that not all target devices will have registers. Some devices are simple and contain only 1 register, which may be written to directly by sending the register data immediately after the target address, instead of addressing a register. An example of a single-register device would be an 8-bit I 2C switch, which is controlled via I 2C commands. Since it has 1 bit to enable or disable a channel, there is only 1 register needed, and the controller merely writes the register data after the target address, skipping the register number.

8.5.2.1 Writes

To write on the I 2C bus, the controller will send a START condition on the bus with the address of the target, as well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the controller will then send the register address of the register to which it wishes to write. The target will acknowledge again, letting the controller know it is ready. After this, the controller will start sending the register data to the target until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller will terminate the transmission with a STOP condition. Figure 8-5 shows an example of writing a single byte to a target register. TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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8.5.2.2 Reads

Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target, the controller must first instruct the target which register it wishes to read from. This is done by the controller starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. Once the target acknowledges this register address, the controller will send a START condition again, followed by the target address with the R/ W bit set to 1 (signifying a read). This time, the target will acknowledge the read request, and the controller will release the SDA bus but will continue supplying the clock to the target. During this part of the transaction, the controller will become the controller-receiver, and the target will become the target-transmitter. The controller will continue to send out the clock pulses, but will release the SDA line so that the target can transmit data. At the end of every byte of data, the controller will send an ACK to the target, letting the target know that it is ready for more data. Once the controller has received the number of bytes it is expecting, it will send a NACK, signaling to the target to halt communications and release the bus. The controller will follow this up with a STOP condition. Figure 8-7 shows an example of reading a single byte from a target register. 0S1 0 0 0 0ADDR0Controller controls SDA lineTarget controls SDA lineRead from one register in a deviceB7 B6B5B4B3Device (Target) Address (7 bits)AB2 B1 B0ASTARTACKRegister Address N (8 bits)ACK00Sr01000ADDR1ARepeated STARTDevice (Target) Address (7 bits)D7D6D5 D4D3D2 D1 D0 NAPACKNACKSTOPData Byte from Register N (8 bits)R/W=0R/W=1 Figure 8-7. Read from Register SCLSDA INT StartConditionR/WRead FromPortData IntoPort StopConditionACK FromControllerNACK FromControllerACK FromTargetData From PortTarget AddressData From Port1 9R765432001S000ADDR1AData 1Data 4A NAP Data 2Data 3Data 4Data 5INT is cleared by Read from PortStop not neededto clear INTtph tpstirtiv A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port Register). B. This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from P-port (see Figure 8-7). Figure 8-8. Read from Input Port Register TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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8.6 Register Map

8.6.1 Device Address

The address of the TCA6408A is shown in Figure 8-9. 0Target Address0100ADDRR/WFixedProgrammable0 Figure 8-9. TCA6408A Address Table 8-3. Address Reference ADDR I2C BUS TARGET ADDRESS L 32 (decimal), 20 (hexadecimal) H 33 (decimal), 21 (hexadecimal) The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which is stored in the Control Register in the TCA6408A. Two bits of this data byte will state both the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. B2 B1 B0B5 B4 B3B7 B6 Figure 8-10. Control Register Bits Table 8-4. Command Byte CONTROL REGISTER BITS COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULTB7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 00 Input Port Read byte xxxx xxxx 0 0 0 0 0 0 0 1 01 Output Port Read/write byte 1111 1111 0 0 0 0 0 0 1 0 02 Polarity Inversion Read/write byte 0000 0000 0 0 0 0 0 0 1 1 03 Configuration Read/write byte 1111 1111 www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TCA6408A

8.6.3 Register Descriptions

The Input Port Register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration Register. They act only on read operation. Writes to this register have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I 2C device that the Input Port Register will be accessed next. Table 8-5. Register 0 (Input Port Register) BIT I-7 I-6 I-5 I-4 I-3 I-2 I-1 I-0 DEFAULT X X X X X X X X The Output Port Register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 8-6. Register 1 (Output Port Register) BIT O-7 O-6 O-5 O-4 O-3 O-2 O-1 O-0 DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion Register (register 2) allows polarity inversion of pins defined as inputs by the Configuration Register. If a bit in this register is set (written with 1), the polarity of the corresponding port pin is inverted. If a bit in this register is cleared (written with a 0), the original polarity of the corresponding port pin is retained. Table 8-7. Register 2 (Polarity Inversion Register) BIT N-7 N-6 N-5 N-4 N-3 N-2 N-1 N-0 DEFAULT 0 0 0 0 0 0 0 0 The Configuration Register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 8-8. Register 3 (Configuration Register) BIT C-7 C-6 C-5 C-4 C-3 C-2 C-1 C-0 DEFAULT 1 1 1 1 1 1 1 1 TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

the I2C bus may contain any number of other target devices. The TCA6408A will be in a remote location from the controller, placed close to the GPIOs to which the controller needs to monitor or control. A typical application of the TCA6408A will operate with a lower voltage on the controller side (VCCI), and a higher voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of devices such as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured as inputs to receive data from interrupts, alarms, status outputs, or push buttons. www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TCA6408A

9.2 Typical Application

Figure 9-1 shows an application in which the TCA6408A can be used. ADDR P7P6P5P3P2P1 GNDINTSDASCL TCA6408A SDASCLINT GND Keypad ABENABLEController5679101112 141513 161RESET3RESET VCCIVCC VCCP10 kW ( 4)´ P0 ALARMSubsystem 1(e.g., Alarm)(see Note D)4100 k ( 3)W´VCCPVCCIVCCI(1.8 V) A. Device address configured as 0100000 for this example. B. P0 and P2–P4 are configured as inputs. C. P1 and P5–P7 are configured as outputs. D. Resistors are required for inputs (on P-port) that may float. If a driver to an input will never let the input float, a resistor is not needed. Outputs (in the P-port) do not need pull-up resistors. Figure 9-1. Typical Application Schematic

9.2.1 Design Requirements

Table 9-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE I2C input voltage (VCCI) 1.8 V P-port input/output voltage (VCCP) 5 V Output current rating, P-port sinking (IOL) 25 mA Output current rating, P-port sourcing (IOH) 10 mA I2C bus clock (SCL) speed 400 kHz TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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9.2.2 Detailed Design Procedure

The pull-up resistors, R P, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all targets on the I 2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL: CC OL(max) p(min) OL V V R I /c45 /c61 (1) The maximum pull-up resistance is a function of the maximum rise time, t r (300 ns for fast-mode operation, f SCL = 400 kHz) and bus capacitance, Cb: r p(max) b tR 0.8473 C/c61 /c180 (2) The maximum bus capacitance for an I 2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9538, C i for SCL or CIO for SDA, the capacitance of wires, connections, and traces, and the capacitance of additional targets on the bus.

9.2.2.1 Minimizing ICC When I/O is Used to Control LEDs

When the I/Os are used to control LEDs, normally they are connected to V CC through a resistor as shown in Figure 9-1. The LED acts as a diode, so when the LED is off, the I/O V IN is about 1.2 V less than V CC. The ΔICC parameter in Section 6.5 shows how ICC increases as VIN becomes lower than VCC. Designs that must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 9-2 shows a high-value resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V IN at or above V CC and prevent additional supply current consumption when the LED is off. Px LED 100 kΩVCC VCC Figure 9-2. High-Value Resistor in Parallel With LED www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TCA6408A

3.3 V Px LED 5 V VCC Figure 9-3. Device Supplied by a Low Voltage

9.2.3 Application Curves

Cb (pF) Rp(max) (kOhm) 0 50 100 150 200 250 300 350 400 450 D008 Standard-mode Fast-mode Standard-mode: fSCL= 100 kHz, tr = 1 µs Fast-mode: fSCL= 400 kHz, tr= 300 ns Figure 9-4. Maximum Pullup Resistance (Rp(max)) vs Bus Capacitance (Cb) VCC (V) Rp(min) (kOhm) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 D009 VCC > 2V VCC <= 2 VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V VOL = 0.4 V, IOL = 3 mA when VCC > 2 V Figure 9-5. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VCC) TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA6408A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. Ramping up the device VCCP before VCCI is recommended to prevent SDA from potentially being stuck LOW. The two types of power-on reset are shown in Figure 10-1 and Figure 10-2. VCC Ramp-Up Re-Ramp-Up Time to Re-Ramp Time Ramp-Down tFT tRTtRT tTRR_GND Figure 10-1. VCC is Lowered Below 0.2 V Or 0 V and then Ramped Up to VCC VCC Ramp-Up Time to Re-Ramp Time Ramp-Down VIN drops below POR levels tRTtFT tTRR_VPOR50 Figure 10-2. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC Table 10-1 specifies the performance of the power-on reset feature for TCA6408A for both types of power-on reset. Table 10-1. Recommended Supply Sequencing and Ramp Rates at TA = 25°C(1) PARAMETER MIN TYP MAX UNIT tFT Fall rate See Figure 10-1 0.1 2000 ms tRT Rise rate See Figure 10-1 0.1 2000 ms tRR_GND Time to re-ramp (when VCC drops to GND) See Figure 10-1 1 μs tRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 10-2 1 μs VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs See Figure 10-3 1.2 V tGW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx See Figure 10-3 10 μs VPORF Voltage trip point of POR on falling VCC 0.7 V VPORR Voltage trip point of POR on rising VCC 1.4 V (1) Not tested. Specified by design. www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TCA6408A

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tGW) and height (t GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more information on how to measure these specifications. VCC Time tGW tGH Figure 10-3. Glitch Width And Glitch Height VPOR is critical to the power-on reset. V POR is the voltage level at which the reset condition is released and all the registers and the I 2C/SMBus state machine are initialized to the default states. The value of V POR differs based on the V CC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this specification. VCC VPOR VPORF Time POR Time Figure 10-4. VPOR TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA6408A, common PCB layout practices should be followed, but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the V CCP pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These capacitors should be placed as close to the TCA6408A as possible. These best practices are shown in Section 11.2. For the layout example provided in Section 11.2, it would be possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (V CCI and V CCP) and ground (GND). However, a 4-layer board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to V CCI, VCCP, or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in Section 11.2.

11.2 Layout Example

= Via to GND Plane To CPU/MCU Figure 11-1. Example Layout (PW Package) www.ti.com TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TCA6408A

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TCA6408A SCPS192E – APRIL 2009 – REVISED JANUARY 2023 www.ti.com

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www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TCA6408APWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 PH408A TCA6408APWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PH408A TCA6408APWR.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PH408A TCA6408APWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PH408A TCA6408APWRG4.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PH408A TCA6408APWRG4.B Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PH408A TCA6408ARGTR Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVU TCA6408ARGTR.A Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVU TCA6408ARGTR.B Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVU TCA6408ARGTRG4 Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVU TCA6408ARGTRG4.A Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVU TCA6408ARGTRG4.B Active Production VQFN (RGT) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVU TCA6408ARSVR Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 ZVU TCA6408ARSVR.A Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 ZVU TCA6408ARSVR.B Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 ZVU (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 9-Nov-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TCA6408A :

• Automotive : TCA6408A-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA6408APWR TSSOP PW 16 2000 353.0 353.0 32.0 TCA6408APWRG4 TSSOP PW 16 2000 353.0 353.0 32.0 TCA6408ARGTR VQFN RGT 16 3000 353.0 353.0 32.0 TCA6408ARGTRG4 VQFN RGT 16 3000 353.0 353.0 32.0 TCA6408ARSVR UQFN RSV 16 3000 202.0 201.0 28.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. UQFN - 0.55 mm max heightRSV 16 ULTRA THIN QUAD FLATPACK - NO LEAD1.8 x 2.6, 0.4 mm pitch 4231225/A

www.ti.com PACKAGE OUTLINE C 1.85 1.75 2.65 2.55 0.55 0.45 0.05 0.00 2X 1.2 12X 0.4 2X 1.2 15X 0.45 0.35 16X 0.25 0.15 0.55 0.45 (0.13) TYP UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 0.05 C

0.07 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 ° X 0.1) SYMM SYMM 5 8 1316 SCALE 5.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.4) (R0.05) TYP

0.05 MAX

0.05 MIN

15X (0.6) 16X (0.2) (1.6) (2.4) (0.7) UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X SEE SOLDER MASK DETAIL 5 8 1316 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 15X (0.6) 16X (0.2) 12X (0.4) (1.6) (2.4) (R0.05) TYP (0.7) UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 25X SYMM SYMM 5 8 1316

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.45 0.1 16X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 VQFN - 1 mm max heightRGT0016A PLASTIC QUAD FLATPACK - NO LEAD 4219032/A 02/2017 PIN 1 INDEX AREA 0.08 SEATING PLANE 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Reference JEDEC registration MO-220 SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.475) TYP ( 1.45) (R0.05) ALL PAD CORNERS (0.475) TYP VQFN - 1 mm max heightRGT0016A PLASTIC QUAD FLATPACK - NO LEAD 4219032/A 02/2017 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.34) (R0.05) TYP VQFN - 1 mm max heightRGT0016A PLASTIC QUAD FLATPACK - NO LEAD 4219032/A 02/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

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